* Re: sa8775p-ride: What's a normal SMMU TLB sync time?
From: Bjorn Andersson @ 2024-04-05 3:25 UTC (permalink / raw)
To: Andrew Halaney
Cc: linux-arm-msm, robdclark, will, iommu, joro, linux-arm-kernel,
linux-kernel, quic_c_gdjako, quic_cgoldswo, quic_sukadev,
quic_pdaly, quic_sudaraja
In-Reply-To: <kord5qq6mywc7rbkzeoliz2cklrlljxm74qmrfwwjf6irx4fp7@6f5wsonafstt>
On Tue, Apr 02, 2024 at 04:22:31PM -0500, Andrew Halaney wrote:
> Hey,
>
> Sorry for the wide email, but I figured someone recently contributing
> to / maintaining the Qualcomm SMMU driver may have some proper insights
> into this.
>
> Recently I remembered that performance on some Qualcomm platforms
> takes a major hit when you use iommu.strict=1/CONFIG_IOMMU_DEFAULT_DMA_STRICT.
>
> On the sa8775p-ride, I see most TLB sync calls to be about 150 us long,
> with some spiking to 500 us, etc:
>
> [root@qti-snapdragon-ride4-sa8775p-09 ~]# trace-cmd start -p function_graph -g qcom_smmu_tlb_sync --max-graph-depth 1
> plugin 'function_graph'
> [root@qti-snapdragon-ride4-sa8775p-09 ~]# trace-cmd show
> # tracer: function_graph
> #
> # CPU DURATION FUNCTION CALLS
> # | | | | | | |
> 0) ! 144.062 us | qcom_smmu_tlb_sync();
>
> On my sc8280xp-lenovo-thinkpad-x13s (only other Qualcomm platform I can compare
> with) I see around 2-15 us with spikes up to 20-30 us. That's thanks to this
> patch[0], which I guess improved the platform from 1-2 ms to the ~10 us number.
>
> It's not entirely clear to me how a DPU specific programming affects system
> wide SMMU performance, but I'm curious if this is the only way to achieve this?
> sa8775p doesn't have the DPU described even right now, so that's a bummer
> as there's no way to make a similar immediate optimization, but I'm still struggling
> to understand what that patch really did to improve things so maybe I'm missing
> something.
>
The cause was that the TLB sync is synchronized with the display updates,
but without appropriate safe_lut_tlb values the display side wouldn't
play nice.
Regards,
Bjorn
> I'm honestly not even sure what a "typical" range for TLB sync time would be,
> but on sa8775p-ride its bad enough that some IRQs like UFS can cause RCU stalls
> (pretty easy to reproduce with fio basic-verify.fio for example on the platform).
> It also makes running with iommu.strict=1 impractical as performance for UFS,
> ethernet, etc drops 75-80%.
>
> Does anyone have any bright ideas on how to improve this, or if I'm even in
> the right for assuming that time is suspiciously long?
>
> Thanks,
> Andrew
>
> [0] https://lore.kernel.org/linux-arm-msm/CAF6AEGs9PLiCZdJ-g42-bE6f9yMR6cMyKRdWOY5m799vF9o4SQ@mail.gmail.com/
>
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^ permalink raw reply
* Re: [PATCH V17 0/9] arm64/perf: Enable branch stack sampling
From: Adam Young @ 2024-04-05 3:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20240405024639.1179064-1-anshuman.khandual@arm.com>
Will this apply on 6.8? We have been chasing getting this tested, and
are a revision behind you.
We are just testing on 6.8, and the fact that we don't have one that
works on stable revision has been one
of the reasons we have not provided feedback.
I did get to test an early version of the patch several months ago and
strictly speaking it works:
I used a quicksort built unoptimized and compared it with an AutoFDO
version consuming the output from BRBE. The AutoFDO version was
significantly faster, so we do get some optimization.
What is that actual Test framework you are using to test? I would like
to do an apples-to-apples comparison with this version of the patch set
or the most recent one I can get to apply.
On 4/4/24 22:46, Anshuman Khandual wrote:
> This series enables perf branch stack sampling support on arm64 platform
> via a new arch feature called Branch Record Buffer Extension (BRBE). All
> the relevant register definitions could be accessed here.
>
> https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers
>
> This series applies on 6.9-rc2.
>
> Also this series is being hosted below for quick access, review and test.
>
> https://git.gitlab.arm.com/linux-arm/linux-anshuman.git (brbe_v17)
>
> There are still some open questions regarding handling multiple perf events
> with different privilege branch filters getting on the same PMU, supporting
> guest branch stack tracing from the host etc. Finally also looking for some
> suggestions regarding supporting BRBE inside the guest. The series has been
> re-organized completely as suggested earlier.
>
> - Anshuman
>
> ========== Perf Branch Stack Sampling Support (arm64 platforms) ===========
>
> Currently arm64 platform does not support perf branch stack sampling. Hence
> any event requesting for branch stack records i.e PERF_SAMPLE_BRANCH_STACK
> marked in event->attr.sample_type, will be rejected in armpmu_event_init().
>
> static int armpmu_event_init(struct perf_event *event)
> {
> ........
> /* does not support taken branch sampling */
> if (has_branch_stack(event))
> return -EOPNOTSUPP;
> ........
> }
>
> $perf record -j any,u,k ls
> Error:
> cycles:P: PMU Hardware or event type doesn't support branch stack sampling.
>
> -------------------- CONFIG_ARM64_BRBE and FEAT_BRBE ----------------------
>
> After this series, perf branch stack sampling feature gets enabled on arm64
> platforms where FEAT_BRBE HW feature is supported, and CONFIG_ARM64_BRBE is
> also selected during build. Let's observe all all possible scenarios here.
>
> 1. Feature not built (!CONFIG_ARM64_BRBE):
>
> Falls back to the current behaviour i.e event gets rejected.
>
> 2. Feature built but HW not supported (CONFIG_ARM64_BRBE && !FEAT_BRBE):
>
> Falls back to the current behaviour i.e event gets rejected.
>
> 3. Feature built and HW supported (CONFIG_ARM64_BRBE && FEAT_BRBE):
>
> Platform supports branch stack sampling requests. Let's observe through a
> simple example here.
>
> $perf record -j any_call,u,k,save_type ls
>
> [Please refer perf-record man pages for all possible branch filter options]
>
> $perf report
> -------------------------- Snip ----------------------
> # Overhead Command Source Shared Object Source Symbol Target Symbol Basic Block Cycles
> # ........ ....... .................... ............................................ ............................................ ..................
> #
> 3.52% ls [kernel.kallsyms] [k] sched_clock_noinstr [k] arch_counter_get_cntpct 16
> 3.52% ls [kernel.kallsyms] [k] sched_clock [k] sched_clock_noinstr 9
> 1.85% ls [kernel.kallsyms] [k] sched_clock_cpu [k] sched_clock 5
> 1.80% ls [kernel.kallsyms] [k] irqtime_account_irq [k] sched_clock_cpu 20
> 1.58% ls [kernel.kallsyms] [k] gic_handle_irq [k] generic_handle_domain_irq 19
> 1.58% ls [kernel.kallsyms] [k] call_on_irq_stack [k] gic_handle_irq 9
> 1.58% ls [kernel.kallsyms] [k] do_interrupt_handler [k] call_on_irq_stack 23
> 1.58% ls [kernel.kallsyms] [k] generic_handle_domain_irq [k] __irq_resolve_mapping 6
> 1.58% ls [kernel.kallsyms] [k] __irq_resolve_mapping [k] __rcu_read_lock 10
> -------------------------- Snip ----------------------
>
> $perf report -D | grep cycles
> -------------------------- Snip ----------------------
> ..... 1: ffff800080dd3334 -> ffff800080dd759c 39 cycles P 0 IND_CALL
> ..... 2: ffff800080ffaea0 -> ffff800080ffb688 16 cycles P 0 IND_CALL
> ..... 3: ffff800080139918 -> ffff800080ffae64 9 cycles P 0 CALL
> ..... 4: ffff800080dd3324 -> ffff8000801398f8 7 cycles P 0 CALL
> ..... 5: ffff8000800f8548 -> ffff800080dd330c 21 cycles P 0 IND_CALL
> ..... 6: ffff8000800f864c -> ffff8000800f84ec 6 cycles P 0 CALL
> ..... 7: ffff8000800f86dc -> ffff8000800f8638 11 cycles P 0 CALL
> ..... 8: ffff8000800f86d4 -> ffff800081008630 16 cycles P 0 CALL
> -------------------------- Snip ----------------------
>
> perf script and other tooling can also be applied on the captured perf.data
> Similarly branch stack sampling records can be collected via direct system
> call i.e perf_event_open() method after setting 'struct perf_event_attr' as
> required.
>
> event->attr.sample_type |= PERF_SAMPLE_BRANCH_STACK
> event->attr.branch_sample_type |= PERF_SAMPLE_BRANCH_<FILTER_1> |
> PERF_SAMPLE_BRANCH_<FILTER_2> |
> PERF_SAMPLE_BRANCH_<FILTER_3> |
> ...............................
>
> But all branch filters might not be supported on the platform.
>
> ----------------------- BRBE Branch Filters Support -----------------------
>
> - Following branch filters are supported on arm64.
>
> PERF_SAMPLE_BRANCH_USER /* Branch privilege filters */
> PERF_SAMPLE_BRANCH_KERNEL
> PERF_SAMPLE_BRANCH_HV
>
> PERF_SAMPLE_BRANCH_ANY /* Branch type filters */
> PERF_SAMPLE_BRANCH_ANY_CALL
> PERF_SAMPLE_BRANCH_ANY_RETURN
> PERF_SAMPLE_BRANCH_IND_CALL
> PERF_SAMPLE_BRANCH_COND
> PERF_SAMPLE_BRANCH_IND_JUMP
> PERF_SAMPLE_BRANCH_CALL
>
> PERF_SAMPLE_BRANCH_NO_FLAGS /* Branch record flags */
> PERF_SAMPLE_BRANCH_NO_CYCLES
> PERF_SAMPLE_BRANCH_TYPE_SAVE
> PERF_SAMPLE_BRANCH_HW_INDEX
> PERF_SAMPLE_BRANCH_PRIV_SAVE
>
> - Following branch filters are not supported on arm64.
>
> PERF_SAMPLE_BRANCH_ABORT_TX
> PERF_SAMPLE_BRANCH_IN_TX
> PERF_SAMPLE_BRANCH_NO_TX
> PERF_SAMPLE_BRANCH_CALL_STACK
>
> Events requesting above non-supported branch filters get rejected.
>
> ------------------ Possible 'branch_sample_type' Mismatch -----------------
>
> Branch stack sampling attributes 'event->attr.branch_sample_type' generally
> remain the same for all the events during a perf record session.
>
> $perf record -e <event_1> -e <event_2> -j <branch_filters> [workload]
>
> event_1->attr.branch_sample_type == event_2->attr.branch_sample_type
>
> This 'branch_sample_type' is used to configure the BRBE hardware, when both
> events i.e <event_1> and <event_2> get scheduled on a given PMU. But during
> PMU HW event's privilege filter inheritance, 'branch_sample_type' does not
> remain the same for all events. Let's consider the following example
>
> $perf record -e cycles:u -e instructions:k -j any,save_type ls
>
> cycles->attr.branch_sample_type != instructions->attr.branch_sample_type
>
> Because cycles event inherits PERF_SAMPLE_BRANCH_USER and instruction event
> inherits PERF_SAMPLE_BRANCH_KERNEL. The proposed solution here configures
> BRBE hardware with 'branch_sample_type' from last event to be added in the
> PMU and hence captured branch records only get passed on to matching events
> during a PMU interrupt.
>
> static int
> armpmu_add(struct perf_event *event, int flags)
> {
> ........
> if (has_branch_stack(event)) {
> /*
> * Reset branch records buffer if a new task event gets
> * scheduled on a PMU which might have existing records.
> * Otherwise older branch records present in the buffer
> * might leak into the new task event.
> */
> if (event->ctx->task && hw_events->brbe_context != event->ctx) {
> hw_events->brbe_context = event->ctx;
> if (armpmu->branch_reset)
> armpmu->branch_reset();
> }
> hw_events->brbe_users++;
> Here -------> hw_events->brbe_sample_type = event->attr.branch_sample_type;
> }
> ........
> }
>
> Instead of overriding existing 'branch_sample_type', both could be merged.
>
> --------------------------- Virtualisation support ------------------------
>
> - Branch stack sampling is not currently supported inside the guest (TODO)
>
> - FEAT_BRBE advertised as absent via clearing ID_AA64DFR0_EL1.BRBE
> - Future support in guest requires emulating FEAT_BRBE
>
> - Branch stack sampling the guest is not supported in the host (TODO)
>
> - Tracing the guest with event->attr.exclude_guest = 0
> - There are multiple challenges involved regarding mixing events
> with mismatched branch_sample_type and exclude_guest and passing
> on captured BRBE records to intended events during PMU interrupt
>
> - Guest access for BRBE registers and instructions has been blocked
>
> - BRBE state save is not required for VHE host (EL2) guest (EL1) transition
>
> - BRBE state is saved for NVHE host (EL1) guest (EL1) transition
>
> -------------------------------- Testing ---------------------------------
>
> - Cross compiled for both arm64 and arm32 platforms
> - Passes all branch tests with 'perf test branch' on arm64
>
> -------------------------------- Questions -------------------------------
>
> - Instead of configuring the BRBE HW with branch_sample_type from the last
> event to be added on the PMU as proposed, could those be merged together
> e.g all privilege requests ORed, to form a common BRBE configuration and
> all events get branch records after a PMU interrupt ?
>
> Changes in V17:
>
> - Added back Reviewed-by tags from Mark Brown
> - Updated the commit message regarding the field BRBINFx_EL1_TYPE_IMPDEF_TRAP_EL3
> - Added leading 0s for all values as BRBIDR0_EL1.NUMREC is a 8 bit field
> - Added leading 0s for all values as BRBFCR_EL1.BANK is a 2 bit field
> - Reordered BRBCR_EL1/BRBCR_EL12/BRBCR_EL2 registers as per sysreg encodings
> - Renamed s/FIRST/BANK_0 and s/SECOND/BANK_1 in BRBFCR_EL1.BANK
> - Renamed s/UNCOND_DIRECT/DIRECT_UNCOND in BRBINFx_EL1.TYPE
> - Renamed s/COND_DIRECT/DIRECT_COND in BRBINFx_EL1.TYPE
> - Dropped __SYS_BRBINF/__SYS_BRBSRC/__SYS_BRBTGT and their expansions
> - Moved all existing BRBE registers from sysreg.h header to tools/sysreg format
> - Updated the commit message including about sys_insn_descs[]
> - Changed KVM to use existing SYS_BRBSRC/TGT/INF_EL1(n) format
> - Moved the BRBE instructions into sys_insn_descs[] array
> - ARM PMUV3 changes have been moved into the BRBE driver patch instead
> - Moved down branch_stack_add() in armpmu_add() after event's basic checks
> - Added new callbacks in struct arm_pmu e.g branch_stack_[init|add|del]()
> - Renamed struct arm_pmu callback branch_reset() as branch_stack_reset()
> - Dropped the comment in armpmu_event_init()
> - Renamed 'pmu_hw_events' elements from 'brbe_' to more generic 'branch_'
> - Separated out from the BRBE driver implementation patch
> - Dropped the comment in __init_el2_brbe()
> - Updated __init_el2_brbe() with BRBCR_EL2.MPRED requirements
> - Updated __init_el2_brbe() with __check_hvhe() constructs
> - Updated booting.rst regarding MPRED, MDCR_EL3 and fine grained control
> - Dropped Documentation/arch/arm64/brbe.rst
> - Renamed armv8pmu_branch_reset() as armv8pmu_branch_stack_reset()
> - Separated out booting.rst and EL2 boot requirements into a new patch
> - Dropped process_branch_aborts() completely
> - Added an warning if transaction states get detected unexpectedly
> - Dropped enum brbe_bank_idx from the driver
> - Defined armv8pmu_branch_stack_init/add/del() callbacks in the driver
> - Changed BRBE driver to use existing SYS_BRBSRC/TGT/INF_EL1(n) format
> - Dropped isb() call sites in __debug_[save|restore]_brbe()
> - Changed to [read|write]_sysreg_el1() accessors in __debug_[save|restore]_brbe()
>
> Changes in V16
>
> https://lore.kernel.org/all/20240125094119.2542332-1-anshuman.khandual@arm.com/
>
> - Updated BRBINFx_EL1.TYPE = 0b110000 as field IMPDEF_TRAP_EL3
> - Updated BRBCR_ELx[9] as field FZPSS
> - Updated BRBINFINJ_EL1 to use sysreg field BRBINFx_EL1
> - Added BRB_INF_SRC_TGT_EL1 macro for corresponding BRB_[INF|SRC|TGT] expansion
> - Renamed arm_brbe.h as arm_pmuv3_branch.h
> - Updated perf_sample_save_brstack()'s new argument requirements with NULL
> - Fixed typo (s/informations/information) in Documentation/arch/arm64/brbe.rst
> - Added SPDX-License-Identifier in Documentation/arch/arm64/brbe.rst
> - Added new PERF_SAMPLE_BRANCH_COUNTERS into BRBE_EXCLUDE_BRANCH_FILTERS
> - Dropped BRBFCR_EL1 and BRBCR_EL1 from enum vcpu_sysreg
> - Reverted back the KVM NVHE patch - use host_debug_state based 'brbcr_el1'
> element and dropped the previous dependency on Jame's coresight series
>
> Changes in V15:
>
> https://lore.kernel.org/all/20231201053906.1261704-1-anshuman.khandual@arm.com/
>
> - Added a comment for armv8pmu_branch_probe() regarding single cpu probe
> - Added a text in brbe.rst regarding single cpu probe
> - Dropped runtime BRBE enable for setting DEBUG_STATE_SAVE_BRBE
> - Dropped zero_branch_stack based zero branch records mechanism
> - Replaced BRBFCR_EL1_DEFAULT_CONFIG with BRBFCR_EL1_CONFIG_MASK
> - Added BRBFCR_EL1_CONFIG_MASK masking in branch_type_to_brbfcr()
> - Moved BRBE helpers from arm_brbe.h into arm_brbe.c
> - Moved armv8_pmu_xxx() declaration inside arm_brbe.h for arm64 (CONFIG_ARM64_BRBE)
> - Moved armv8_pmu_xxx() stub definitions inside arm_brbe.h for arm32 (!CONFIG_ARM64_BRBE)
> - Included arm_brbe.h header both in arm_pmuv3.c and arm_brbe.c
> - Dropped BRBE custom pr_fmt()
> - Dropped CONFIG_PERF_EVENTS wrapping from header entries
> - Flush branch records when a cpu bound event follows a task bound event
> - Dropped BRBFCR_EL1 from __debug_save_brbe()/__debug_restore_brbe()
> - Always save the live SYS_BRBCR_EL1 in host context and then check if
> BRBE was enabled before resetting SYS_BRBCR_EL1 for the host
>
> Changes in V14:
>
> https://lore.kernel.org/all/20231114051329.327572-1-anshuman.khandual@arm.com/
>
> - This series has been reorganised as suggested during V13
> - There are just eight patches now i.e 5 enablement and 3 perf branch tests
>
> - Fixed brackets problem in __SYS_BRBINFO/BRBSRC/BRBTGT() macros
> - Renamed the macro i.e s/__SYS_BRBINFO/__SYS_BRBINF/
> - Renamed s/BRB_IALL/BRB_IALL_INSN and s/BRBE_INJ/BRB_INJ_INSN
> - Moved BRB_IALL_INSN and SYS_BRB_INSN instructions to sysreg patch
> - Changed E1BRE as ExBRE in sysreg fields inside BRBCR_ELx
> - Used BRBCR_ELx for defining all BRBCR_EL1, BRBCR_EL2, and BRBCR_EL12 (new)
>
> - Folded the following three patches into a single patch i.e [PATCH 3/8]
>
> drivers: perf: arm_pmu: Add new sched_task() callback
> arm64/perf: Add branch stack support in struct arm_pmu
> arm64/perf: Add branch stack support in struct pmu_hw_events
> arm64/perf: Add branch stack support in ARMV8 PMU
> arm64/perf: Add PERF_ATTACH_TASK_DATA to events with has_branch_stack()
>
> - All armv8pmu_branch_xxxx() stub definitions have been moved inside
> include/linux/perf/arm_pmuv3.h for easy access from both arm32 and arm64
> - Added brbe_users, brbe_context and brbe_sample_type in struct pmu_hw_events
> - Added comments for all the above new elements in struct pmu_hw_events
> - Added branch_reset() and sched_task() callbacks
> - Changed and optimized branch records processing during a PMU IRQ
> - NO branch records get captured for event with mismatched brbe_sample_type
> - Branch record context is tracked from armpmu_del() & armpmu_add()
> - Branch record hardware is driven from armv8pmu_start() & armv8pmu_stop()
> - Dropped NULL check for 'pmu_ctx' inside armv8pmu_sched_task()
> - Moved down PERF_ATTACH_TASK_DATA assignment with a preceding comment
> - In conflicting branch sample type requests, first event takes precedence
>
> - Folded the following five patches from V13 into a single patch i.e
> [PATCH 4/8]
>
> arm64/perf: Enable branch stack events via FEAT_BRBE
> arm64/perf: Add struct brbe_regset helper functions
> arm64/perf: Implement branch records save on task sched out
> arm64/perf: Implement branch records save on PMU IRQ
>
> - Fixed the year in copyright statement
> - Added Documentation/arch/arm64/brbe.rst
> - Updated Documentation/arch/arm64/booting.rst (BRBCR_EL2.CC for EL1 entry)
> - Added __init_el2_brbe() which enables branch record cycle count support
> - Disabled EL2 traps in __init_el2_fgt() while accessing BRBE registers and
> executing instructions
> - Changed CONFIG_ARM64_BRBE user visible description
> - Fixed a typo in CONFIG_ARM64_BRBE config option description text
> - Added BUILD_BUG_ON() co-relating BRBE_BANK_MAX_ENTRIES and MAX_BRANCH_RECORDS
> - Dropped arm64_create_brbe_task_ctx_kmem_cache()
> - Moved down comment for PERF_SAMPLE_BRANCH_KERNEL in branch_type_to_brbcr()
> - Renamed BRBCR_ELx_DEFAULT_CONFIG as BRBCR_ELx_CONFIG_MASK
> - Replaced BRBCR_ELx_DEFAULT_TS with BRBCR_ELx_TS_MASK in BRBCR_ELx_CONFIG_MASK
> - Replaced BRBCR_ELx_E1BRE instances with BRBCR_ELx_ExBRE
>
> - Added BRBE specific branch stack sampling perf test patches into the series
> - Added a patch to prevent guest accesses into BRBE registers and instructions
> - Added a patch to save the BRBE host context in NVHE environment
> - Updated most commit messages
>
> Changes in V13:
>
> https://lore.kernel.org/all/20230711082455.215983-1-anshuman.khandual@arm.com/
> https://lore.kernel.org/all/20230622065351.1092893-1-anshuman.khandual@arm.com/
>
> - Added branch callback stubs for aarch32 pmuv3 based platforms
> - Updated the comments for capture_brbe_regset()
> - Deleted the comments in __read_brbe_regset()
> - Reversed the arguments order in capture_brbe_regset() and brbe_branch_save()
> - Fixed BRBE_BANK[0|1]_IDX_MAX indices comparison in armv8pmu_branch_read()
> - Fixed BRBE_BANK[0|1]_IDX_MAX indices comparison in capture_brbe_regset()
>
> Changes in V12:
>
> https://lore.kernel.org/all/20230615133239.442736-1-anshuman.khandual@arm.com/
>
> - Replaced branch types with complete DIRECT/INDIRECT prefixes/suffixes
> - Replaced branch types with complete INSN/ALIGN prefixes/suffixes
> - Replaced return branch types as simple RET/ERET
> - Replaced time field GST_PHYSICAL as GUEST_PHYSICAL
> - Added 0 padding for BRBIDR0_EL1.NUMREC enum values
> - Dropped helper arm_pmu_branch_stack_supported()
> - Renamed armv8pmu_branch_valid() as armv8pmu_branch_attr_valid()
> - Separated perf_task_ctx_cache setup from arm_pmu private allocation
> - Collected changes to branch_records_alloc() in a single patch [5/10]
> - Reworked and cleaned up branch_records_alloc()
> - Reworked armv8pmu_branch_read() with new loop iterations in patch [6/10]
> - Reworked capture_brbe_regset() with new loop iterations in patch [8/10]
> - Updated the comment in branch_type_to_brbcr()
> - Fixed the comment before stitch_stored_live_entries()
> - Fixed BRBINFINJ_EL1 definition for VALID_FULL enum field
> - Factored out helper __read_brbe_regset() from capture_brbe_regset()
> - Dropped the helper copy_brbe_regset()
> - Simplified stitch_stored_live_entries() with memcpy(), memmove()
> - Reworked armv8pmu_probe_pmu() to bail out early with !probe.present
> - Rework brbe_attributes_probe() without 'struct brbe_hw_attr'
> - Dropped 'struct brbe_hw_attr' argument from capture_brbe_regset()
> - Dropped 'struct brbe_hw_attr' argument from brbe_branch_save()
> - Dropped arm_pmu->private and added arm_pmu->reg_trbidr instead
>
> Changes in V11:
>
> https://lore.kernel.org/all/20230531040428.501523-1-anshuman.khandual@arm.com/
>
> - Fixed the crash for per-cpu events without event->pmu_ctx->task_ctx_data
>
> Changes in V10:
>
> https://lore.kernel.org/all/20230517022410.722287-1-anshuman.khandual@arm.com/
>
> - Rebased the series on v6.4-rc2
> - Moved ARMV8 PMUV3 changes inside drivers/perf/arm_pmuv3.c
> - Moved BRBE driver changes inside drivers/perf/arm_brbe.[c|h]
> - Moved the WARN_ON() inside the if condition in armv8pmu_handle_irq()
>
> Changes in V9:
>
> https://lore.kernel.org/all/20230315051444.1683170-1-anshuman.khandual@arm.com/
>
> - Fixed build problem with has_branch_stack() in arm64 header
> - BRBINF_EL1 definition has been changed from 'Sysreg' to 'SysregFields'
> - Renamed all BRBINF_EL1 call sites as BRBINFx_EL1
> - Dropped static const char branch_filter_error_msg[]
> - Implemented a positive list check for BRBE supported perf branch filters
> - Added a comment in armv8pmu_handle_irq()
> - Implemented per-cpu allocation for struct branch_record records
> - Skipped looping through bank 1 if an invalid record is detected in bank 0
> - Added comment in armv8pmu_branch_read() explaining prohibited region etc
> - Added comment warning about erroneously marking transactions as aborted
> - Replaced the first argument (perf_branch_entry) in capture_brbe_flags()
> - Dropped the last argument (idx) in capture_brbe_flags()
> - Dropped the brbcr argument from capture_brbe_flags()
> - Used perf_sample_save_brstack() to capture branch records for perf_sample_data
> - Added comment explaining rationale for setting BRBCR_EL1_FZP for user only traces
> - Dropped BRBE prohibited state mechanism while in armv8pmu_branch_read()
> - Implemented event task context based branch records save mechanism
>
> Changes in V8:
>
> https://lore.kernel.org/all/20230123125956.1350336-1-anshuman.khandual@arm.com/
>
> - Replaced arm_pmu->features as arm_pmu->has_branch_stack, updated its helper
> - Added a comment and line break before arm_pmu->private element
> - Added WARN_ON_ONCE() in helpers i.e armv8pmu_branch_[read|valid|enable|disable]()
> - Dropped comments in armv8pmu_enable_event() and armv8pmu_disable_event()
> - Replaced open bank encoding in BRBFCR_EL1 with SYS_FIELD_PREP()
> - Changed brbe_hw_attr->brbe_version from 'bool' to 'int'
> - Updated pr_warn() as pr_warn_once() with values in brbe_get_perf_[type|priv]()
> - Replaced all pr_warn_once() as pr_debug_once() in armv8pmu_branch_valid()
> - Added a comment in branch_type_to_brbcr() for the BRBCR_EL1 privilege settings
> - Modified the comment related to BRBINFx_EL1.LASTFAILED in capture_brbe_flags()
> - Modified brbe_get_perf_entry_type() as brbe_set_perf_entry_type()
> - Renamed brbe_valid() as brbe_record_is_complete()
> - Renamed brbe_source() as brbe_record_is_source_only()
> - Renamed brbe_target() as brbe_record_is_target_only()
> - Inverted checks for !brbe_record_is_[target|source]_only() for info capture
> - Replaced 'fetch' with 'get' in all helpers that extract field value
> - Dropped 'static int brbe_current_bank' optimization in select_brbe_bank()
> - Dropped select_brbe_bank_index() completely, added capture_branch_entry()
> - Process captured branch entries in two separate loops one for each BRBE bank
> - Moved branch_records_alloc() inside armv8pmu_probe_pmu()
> - Added a forward declaration for the helper has_branch_stack()
> - Added new callbacks armv8pmu_private_alloc() and armv8pmu_private_free()
> - Updated armv8pmu_probe_pmu() to allocate the private structure before SMP call
>
> Changes in V7:
>
> https://lore.kernel.org/all/20230105031039.207972-1-anshuman.khandual@arm.com/
>
> - Folded [PATCH 7/7] into [PATCH 3/7] which enables branch stack sampling event
> - Defined BRBFCR_EL1_BRANCH_FILTERS, BRBCR_EL1_DEFAULT_CONFIG in the header
> - Defined BRBFCR_EL1_DEFAULT_CONFIG in the header
> - Updated BRBCR_EL1_DEFAULT_CONFIG with BRBCR_EL1_FZP
> - Defined BRBCR_EL1_DEFAULT_TS in the header
> - Updated BRBCR_EL1_DEFAULT_CONFIG with BRBCR_EL1_DEFAULT_TS
> - Moved BRBCR_EL1_DEFAULT_CONFIG check inside branch_type_to_brbcr()
> - Moved down BRBCR_EL1_CC, BRBCR_EL1_MPRED later in branch_type_to_brbcr()
> - Also set BRBE in paused state in armv8pmu_branch_disable()
> - Dropped brbe_paused(), set_brbe_paused() helpers
> - Extracted error string via branch_filter_error_msg[] for armv8pmu_branch_valid()
> - Replaced brbe_v1p1 with brbe_version in struct brbe_hw_attr
> - Added valid_brbe_[cc, format, version]() helpers
> - Split a separate brbe_attributes_probe() from armv8pmu_branch_probe()
> - Capture event->attr.branch_sample_type earlier in armv8pmu_branch_valid()
> - Defined enum brbe_bank_idx with possible values for BRBE bank indices
> - Changed armpmu->hw_attr into armpmu->private
> - Added missing space in stub definition for armv8pmu_branch_valid()
> - Replaced both kmalloc() with kzalloc()
> - Added BRBE_BANK_MAX_ENTRIES
> - Updated comment for capture_brbe_flags()
> - Updated comment for struct brbe_hw_attr
> - Dropped space after type cast in couple of places
> - Replaced inverse with negation for testing BRBCR_EL1_FZP in armv8pmu_branch_read()
> - Captured cpuc->branches->branch_entries[idx] in a local variable
> - Dropped saved_priv from armv8pmu_branch_read()
> - Reorganize PERF_SAMPLE_BRANCH_NO_[CYCLES|NO_FLAGS] related configuration
> - Replaced with FIELD_GET() and FIELD_PREP() wherever applicable
> - Replaced BRBCR_EL1_TS_PHYSICAL with BRBCR_EL1_TS_VIRTUAL
> - Moved valid_brbe_nr(), valid_brbe_cc(), valid_brbe_format(), valid_brbe_version()
> select_brbe_bank(), select_brbe_bank_index() helpers inside the C implementation
> - Reorganized brbe_valid_nr() and dropped the pr_warn() message
> - Changed probe sequence in brbe_attributes_probe()
> - Added 'brbcr' argument into capture_brbe_flags() to ascertain correct state
> - Disable BRBE before disabling the PMU event counter
> - Enable PERF_SAMPLE_BRANCH_HV filters when is_kernel_in_hyp_mode()
> - Guard armv8pmu_reset() & armv8pmu_sched_task() with arm_pmu_branch_stack_supported()
>
> Changes in V6:
>
> https://lore.kernel.org/linux-arm-kernel/20221208084402.863310-1-anshuman.khandual@arm.com/
>
> - Restore the exception level privilege after reading the branch records
> - Unpause the buffer after reading the branch records
> - Decouple BRBCR_EL1_EXCEPTION/ERTN from perf event privilege level
> - Reworked BRBE implementation and branch stack sampling support on arm pmu
> - BRBE implementation is now part of overall ARMV8 PMU implementation
> - BRBE implementation moved from drivers/perf/ to inside arch/arm64/kernel/
> - CONFIG_ARM_BRBE_PMU renamed as CONFIG_ARM64_BRBE in arch/arm64/Kconfig
> - File moved - drivers/perf/arm_pmu_brbe.c -> arch/arm64/kernel/brbe.c
> - File moved - drivers/perf/arm_pmu_brbe.h -> arch/arm64/kernel/brbe.h
> - BRBE name has been dropped from struct arm_pmu and struct hw_pmu_events
> - BRBE name has been abstracted out as 'branches' in arm_pmu and hw_pmu_events
> - BRBE name has been abstracted out as 'branches' in ARMV8 PMU implementation
> - Added sched_task() callback into struct arm_pmu
> - Added 'hw_attr' into struct arm_pmu encapsulating possible PMU HW attributes
> - Dropped explicit attributes brbe_(v1p1, nr, cc, format) from struct arm_pmu
> - Dropped brbfcr, brbcr, registers scratch area from struct hw_pmu_events
> - Dropped brbe_users, brbe_context tracking in struct hw_pmu_events
> - Added 'features' tracking into struct arm_pmu with ARM_PMU_BRANCH_STACK flag
> - armpmu->hw_attr maps into 'struct brbe_hw_attr' inside BRBE implementation
> - Set ARM_PMU_BRANCH_STACK in 'arm_pmu->features' after successful BRBE probe
> - Added armv8pmu_branch_reset() inside armv8pmu_branch_enable()
> - Dropped brbe_supported() as events will be rejected via ARM_PMU_BRANCH_STACK
> - Dropped set_brbe_disabled() as well
> - Reformated armv8pmu_branch_valid() warnings while rejecting unsupported events
>
> Changes in V5:
>
> https://lore.kernel.org/linux-arm-kernel/20221107062514.2851047-1-anshuman.khandual@arm.com/
>
> - Changed BRBCR_EL1.VIRTUAL from 0b1 to 0b01
> - Changed BRBFCR_EL1.EnL into BRBFCR_EL1.EnI
> - Changed config ARM_BRBE_PMU from 'tristate' to 'bool'
>
> Changes in V4:
>
> https://lore.kernel.org/all/20221017055713.451092-1-anshuman.khandual@arm.com/
>
> - Changed ../tools/sysreg declarations as suggested
> - Set PERF_SAMPLE_BRANCH_STACK in data.sample_flags
> - Dropped perfmon_capable() check in armpmu_event_init()
> - s/pr_warn_once/pr_info in armpmu_event_init()
> - Added brbe_format element into struct pmu_hw_events
> - Changed v1p1 as brbe_v1p1 in struct pmu_hw_events
> - Dropped pr_info() from arm64_pmu_brbe_probe(), solved LOCKDEP warning
>
> Changes in V3:
>
> https://lore.kernel.org/all/20220929075857.158358-1-anshuman.khandual@arm.com/
>
> - Moved brbe_stack from the stack and now dynamically allocated
> - Return PERF_BR_PRIV_UNKNOWN instead of -1 in brbe_fetch_perf_priv()
> - Moved BRBIDR0, BRBCR, BRBFCR registers and fields into tools/sysreg
> - Created dummy BRBINF_EL1 field definitions in tools/sysreg
> - Dropped ARMPMU_EVT_PRIV framework which cached perfmon_capable()
> - Both exception and exception return branche records are now captured
> only if the event has PERF_SAMPLE_BRANCH_KERNEL which would already
> been checked in generic perf via perf_allow_kernel()
>
> Changes in V2:
>
> https://lore.kernel.org/all/20220908051046.465307-1-anshuman.khandual@arm.com/
>
> - Dropped branch sample filter helpers consolidation patch from this series
> - Added new hw_perf_event.flags element ARMPMU_EVT_PRIV to cache perfmon_capable()
> - Use cached perfmon_capable() while configuring BRBE branch record filters
>
> Changes in V1:
>
> https://lore.kernel.org/linux-arm-kernel/20220613100119.684673-1-anshuman.khandual@arm.com/
>
> - Added CONFIG_PERF_EVENTS wrapper for all branch sample filter helpers
> - Process new perf branch types via PERF_BR_EXTEND_ABI
>
> Changes in RFC V2:
>
> https://lore.kernel.org/linux-arm-kernel/20220412115455.293119-1-anshuman.khandual@arm.com/
>
> - Added branch_sample_priv() while consolidating other branch sample filter helpers
> - Changed all SYS_BRBXXXN_EL1 register definition encodings per Marc
> - Changed the BRBE driver as per proposed BRBE related perf ABI changes (V5)
> - Added documentation for struct arm_pmu changes, updated commit message
> - Updated commit message for BRBE detection infrastructure patch
> - PERF_SAMPLE_BRANCH_KERNEL gets checked during arm event init (outside the driver)
> - Branch privilege state capture mechanism has now moved inside the driver
>
> Changes in RFC V1:
>
> https://lore.kernel.org/all/1642998653-21377-1-git-send-email-anshuman.khandual@arm.com/
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: James Clark <james.clark@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-perf-users@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
>
> Anshuman Khandual (6):
> arm64/sysreg: Add BRBE registers and fields
> KVM: arm64: Explicitly handle BRBE traps as UNDEFINED
> drivers: perf: arm_pmu: Add infrastructure for branch stack sampling
> arm64/boot: Enable EL2 requirements for BRBE
> drivers: perf: arm_pmuv3: Enable branch stack sampling via FEAT_BRBE
> KVM: arm64: nvhe: Disable branch generation in nVHE guests
>
> James Clark (3):
> perf: test: Speed up running brstack test on an Arm model
> perf: test: Remove empty lines from branch filter test output
> perf: test: Extend branch stack sampling test for Arm64 BRBE
>
> Documentation/arch/arm64/booting.rst | 26 +
> arch/arm64/include/asm/el2_setup.h | 90 ++-
> arch/arm64/include/asm/kvm_host.h | 5 +-
> arch/arm64/include/asm/sysreg.h | 17 +-
> arch/arm64/kvm/debug.c | 5 +
> arch/arm64/kvm/hyp/nvhe/debug-sr.c | 31 +
> arch/arm64/kvm/sys_regs.c | 56 ++
> arch/arm64/tools/sysreg | 131 ++++
> drivers/perf/Kconfig | 11 +
> drivers/perf/Makefile | 1 +
> drivers/perf/arm_brbe.c | 968 +++++++++++++++++++++++++
> drivers/perf/arm_pmu.c | 25 +-
> drivers/perf/arm_pmuv3.c | 146 +++-
> drivers/perf/arm_pmuv3_branch.h | 73 ++
> include/linux/perf/arm_pmu.h | 37 +-
> tools/perf/tests/builtin-test.c | 1 +
> tools/perf/tests/shell/test_brstack.sh | 57 +-
> tools/perf/tests/tests.h | 1 +
> tools/perf/tests/workloads/Build | 2 +
> tools/perf/tests/workloads/traploop.c | 39 +
> 20 files changed, 1696 insertions(+), 26 deletions(-)
> create mode 100644 drivers/perf/arm_brbe.c
> create mode 100644 drivers/perf/arm_pmuv3_branch.h
> create mode 100644 tools/perf/tests/workloads/traploop.c
>
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^ permalink raw reply
* [PATCH v3 1/3] arm64: tlb: Fix TLBI RANGE operand
From: Gavin Shan @ 2024-04-05 3:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: catalin.marinas, will, gshan, akpm, maz, oliver.upton,
ryan.roberts, apopple, rananta, mark.rutland, v-songbaohua,
yangyicong, shahuang, yihyu, shan.gavin
In-Reply-To: <20240405035852.1532010-1-gshan@redhat.com>
KVM/arm64 relies on TLBI RANGE feature to flush TLBs when the dirty
pages are collected by VMM and the page table entries become write
protected during live migration. Unfortunately, the operand passed
to the TLBI RANGE instruction isn't correctly sorted out due to the
commit 117940aa6e5f ("KVM: arm64: Define kvm_tlb_flush_vmid_range()").
It leads to crash on the destination VM after live migration because
TLBs aren't flushed completely and some of the dirty pages are missed.
For example, I have a VM where 8GB memory is assigned, starting from
0x40000000 (1GB). Note that the host has 4KB as the base page size.
In the middile of migration, kvm_tlb_flush_vmid_range() is executed
to flush TLBs. It passes MAX_TLBI_RANGE_PAGES as the argument to
__kvm_tlb_flush_vmid_range() and __flush_s2_tlb_range_op(). SCALE#3
and NUM#31, corresponding to MAX_TLBI_RANGE_PAGES, isn't supported
by __TLBI_RANGE_NUM(). In this specific case, -1 has been returned
from __TLBI_RANGE_NUM() for SCALE#3/2/1/0 and rejected by the loop
in the __flush_tlb_range_op() until the variable @scale underflows
and becomes -9, 0xffff708000040000 is set as the operand. The operand
is wrong since it's sorted out by __TLBI_VADDR_RANGE() according to
invalid @scale and @num.
Fix it by extending __TLBI_RANGE_NUM() to support the combination of
SCALE#3 and NUM#31. With the changes, [-1 31] instead of [-1 30] can
be returned from the macro, meaning the TLBs for 0x200000 pages in the
above example can be flushed in one shoot with SCALE#3 and NUM#31. The
macro TLBI_RANGE_MASK is dropped since no one uses it any more. The
comments are also adjusted accordingly.
Fixes: 117940aa6e5f ("KVM: arm64: Define kvm_tlb_flush_vmid_range()")
Cc: stable@kernel.org # v6.6+
Reported-by: Yihuang Yu <yihyu@redhat.com>
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
---
arch/arm64/include/asm/tlbflush.h | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 3b0e8248e1a4..a75de2665d84 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -161,12 +161,18 @@ static inline unsigned long get_trans_granule(void)
#define MAX_TLBI_RANGE_PAGES __TLBI_RANGE_PAGES(31, 3)
/*
- * Generate 'num' values from -1 to 30 with -1 rejected by the
- * __flush_tlb_range() loop below.
+ * Generate 'num' values from -1 to 31 with -1 rejected by the
+ * __flush_tlb_range() loop below. Its return value is only
+ * significant for a maximum of MAX_TLBI_RANGE_PAGES pages. If
+ * 'pages' is more than that, you must iterate over the overall
+ * range.
*/
-#define TLBI_RANGE_MASK GENMASK_ULL(4, 0)
-#define __TLBI_RANGE_NUM(pages, scale) \
- ((((pages) >> (5 * (scale) + 1)) & TLBI_RANGE_MASK) - 1)
+#define __TLBI_RANGE_NUM(pages, scale) \
+ ({ \
+ int __pages = min((pages), \
+ __TLBI_RANGE_PAGES(31, (scale))); \
+ (__pages >> (5 * (scale) + 1)) - 1; \
+ })
/*
* TLB Invalidation
@@ -379,10 +385,6 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
* 3. If there is 1 page remaining, flush it through non-range operations. Range
* operations can only span an even number of pages. We save this for last to
* ensure 64KB start alignment is maintained for the LPA2 case.
- *
- * Note that certain ranges can be represented by either num = 31 and
- * scale or num = 0 and scale + 1. The loop below favours the latter
- * since num is limited to 30 by the __TLBI_RANGE_NUM() macro.
*/
#define __flush_tlb_range_op(op, start, pages, stride, \
asid, tlb_level, tlbi_user, lpa2) \
--
2.44.0
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^ permalink raw reply related
* [PATCH v3 0/3] arm64: tlb: Fix TLBI RANGE operand
From: Gavin Shan @ 2024-04-05 3:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: catalin.marinas, will, gshan, akpm, maz, oliver.upton,
ryan.roberts, apopple, rananta, mark.rutland, v-songbaohua,
yangyicong, shahuang, yihyu, shan.gavin
A kernel crash on the destination VM after the live migration was
reported by Yihuang Yu. The issue is only reproducible on NVidia's
grace-hopper where TLBI RANGE feature is available. The kernel crash
is caused by incomplete TLB flush and missed dirty page. For the
root cause and analysis, please refer to PATCH[v3 1/3]'s commit log.
Thanks to Marc Zyngier who proposed all the code changes.
PATCH[1] fixes the kernel crash by extending __TLBI_RANGE_NUM() so that
the TLBI RANGE on the area with MAX_TLBI_RANGE_PAGES pages can
be supported
PATCH[2] improves __TLBI_VADDR_RANGE() with masks and FIELD_PREP()
PATCH[3] allows TLBI RANGE operation on the area with MAX_TLBI_RANGE_PAGES
pages in __flush_tlb_range_nosync()
v2: https://lists.infradead.org/pipermail/linux-arm-kernel/2024-April/917432.html
v1: https://lists.infradead.org/pipermail/linux-arm-kernel/2024-April/916972.html
Changelog
=========
v3:
Improve __TLBI_RANGE_NUM() and its comments. Added patches
to improve __TLBI_VADDR_RANGE() and __flush_tlb_range_nosync() (Marc)
v2:
Improve __TLBI_RANGE_NUM() (Marc)
Gavin Shan (3):
arm64: tlb: Fix TLBI RANGE operand
arm64: tlb: Improve __TLBI_VADDR_RANGE()
arm64: tlb: Allow range operation for MAX_TLBI_RANGE_PAGES
arch/arm64/include/asm/tlbflush.h | 53 ++++++++++++++++++-------------
1 file changed, 31 insertions(+), 22 deletions(-)
--
2.44.0
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^ permalink raw reply
* [PATCH v3 2/3] arm64: tlb: Improve __TLBI_VADDR_RANGE()
From: Gavin Shan @ 2024-04-05 3:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: catalin.marinas, will, gshan, akpm, maz, oliver.upton,
ryan.roberts, apopple, rananta, mark.rutland, v-songbaohua,
yangyicong, shahuang, yihyu, shan.gavin
In-Reply-To: <20240405035852.1532010-1-gshan@redhat.com>
The macro returns the operand of TLBI RANGE instruction. A mask needs
to be applied to each individual field upon producing the operand, to
avoid the adjacent fields can interfere with each other when invalid
arguments have been provided. The code looks more tidy at least with
a mask and FIELD_PREP().
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
---
arch/arm64/include/asm/tlbflush.h | 29 ++++++++++++++++++-----------
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index a75de2665d84..243d71f7bc1f 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -142,17 +142,24 @@ static inline unsigned long get_trans_granule(void)
* EL1, Inner Shareable".
*
*/
-#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \
- ({ \
- unsigned long __ta = (baddr); \
- unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \
- __ta &= GENMASK_ULL(36, 0); \
- __ta |= __ttl << 37; \
- __ta |= (unsigned long)(num) << 39; \
- __ta |= (unsigned long)(scale) << 44; \
- __ta |= get_trans_granule() << 46; \
- __ta |= (unsigned long)(asid) << 48; \
- __ta; \
+#define TLBIR_ASID_MASK GENMASK_ULL(63, 48)
+#define TLBIR_TG_MASK GENMASK_ULL(47, 46)
+#define TLBIR_SCALE_MASK GENMASK_ULL(45, 44)
+#define TLBIR_NUM_MASK GENMASK_ULL(43, 39)
+#define TLBIR_TTL_MASK GENMASK_ULL(38, 37)
+#define TLBIR_BADDR_MASK GENMASK_ULL(36, 0)
+
+#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \
+ ({ \
+ unsigned long __ta = 0; \
+ unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \
+ __ta |= FIELD_PREP(TLBIR_BADDR_MASK, baddr); \
+ __ta |= FIELD_PREP(TLBIR_TTL_MASK, __ttl); \
+ __ta |= FIELD_PREP(TLBIR_NUM_MASK, num); \
+ __ta |= FIELD_PREP(TLBIR_SCALE_MASK, scale); \
+ __ta |= FIELD_PREP(TLBIR_TG_MASK, get_trans_granule()); \
+ __ta |= FIELD_PREP(TLBIR_ASID_MASK, asid); \
+ __ta; \
})
/* These macros are used by the TLBI RANGE feature. */
--
2.44.0
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^ permalink raw reply related
* [PATCH v3 3/3] arm64: tlb: Allow range operation for MAX_TLBI_RANGE_PAGES
From: Gavin Shan @ 2024-04-05 3:58 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: catalin.marinas, will, gshan, akpm, maz, oliver.upton,
ryan.roberts, apopple, rananta, mark.rutland, v-songbaohua,
yangyicong, shahuang, yihyu, shan.gavin
In-Reply-To: <20240405035852.1532010-1-gshan@redhat.com>
MAX_TLBI_RANGE_PAGES pages is covered by SCALE#3 and NUM#31 and it's
supported now. Allow TLBI RANGE operation when the number of pages is
equal to MAX_TLBI_RANGE_PAGES in __flush_tlb_range_nosync().
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
---
arch/arm64/include/asm/tlbflush.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 243d71f7bc1f..95fbc8c05607 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -446,11 +446,11 @@ static inline void __flush_tlb_range_nosync(struct vm_area_struct *vma,
* When not uses TLB range ops, we can handle up to
* (MAX_DVM_OPS - 1) pages;
* When uses TLB range ops, we can handle up to
- * (MAX_TLBI_RANGE_PAGES - 1) pages.
+ * MAX_TLBI_RANGE_PAGES pages.
*/
if ((!system_supports_tlb_range() &&
(end - start) >= (MAX_DVM_OPS * stride)) ||
- pages >= MAX_TLBI_RANGE_PAGES) {
+ pages > MAX_TLBI_RANGE_PAGES) {
flush_tlb_mm(vma->vm_mm);
return;
}
--
2.44.0
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^ permalink raw reply related
* Re: [PATCH v2] arm64: tlb: Fix TLBI RANGE operand
From: Gavin Shan @ 2024-04-05 4:05 UTC (permalink / raw)
To: Marc Zyngier
Cc: linux-arm-kernel, linux-kernel, catalin.marinas, will, akpm,
oliver.upton, mark.rutland, ryan.roberts, apopple, rananta,
yangyicong, v-songbaohua, yezhenyu2, yihyu, shan.gavin
In-Reply-To: <87frw1rq1v.wl-maz@kernel.org>
On 4/5/24 03:33, Marc Zyngier wrote:
> On Thu, 04 Apr 2024 11:26:20 +0100,
> Gavin Shan <gshan@redhat.com> wrote:
>>
>> In summary, we need 3 patches but the one fixing __TLBI_RANGE_NUM needs to be
>> PATCH[1/3] so that it can be easily picked by stable kernel. PATCH[2/3] would
>> be to improve __TLBI_VADDR_RANGE with masks. PATCH[3/3] will allow __flush_tlb_range_nosync()
>> to do range-based TLB flush for MAX_TLBI_RANGE_PAGES.
>
> That's about it indeed.
>
Thanks Marc. v3 was posted for further review.
https://lists.infradead.org/pipermail/linux-arm-kernel/2024-April/917700.html
Thanks,
Gavin
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* [PATCH v5 2/4] drm/bridge: add lvds controller support for sam9x7
From: Dharma Balasubiramani @ 2024-04-05 4:35 UTC (permalink / raw)
To: andrzej . hajda @ intel . com, neil . armstrong @ linaro . org,
rfoss @ kernel . org, Laurent . pinchart @ ideasonboard . com,
jonas @ kwiboo . se, jernej . skrabec @ gmail . com,
maarten . lankhorst @ linux . intel . com, mripard @ kernel . org,
tzimmermann @ suse . de, airlied @ gmail . com,
daniel @ ffwll . ch, robh+dt @ kernel . org,
krzysztof . kozlowski+dt @ linaro . org, conor+dt @ kernel . org,
linux @ armlinux . org . uk, Nicolas . Ferre @ microchip . com,
alexandre . belloni @ bootlin . com,
claudiu . beznea @ tuxon . dev, Manikandan . M @ microchip . com,
Dharma . B @ microchip . com, arnd @ arndb . de,
geert+renesas @ glider . be, Jason @ zx2c4 . com,
mpe @ ellerman . id . au, gerg @ linux-m68k . org,
rdunlap @ infradead . org, vbabka @ suse . cz,
dri-devel @ lists . freedesktop . org,
devicetree @ vger . kernel . org,
linux-kernel @ vger . kernel . org,
linux-arm-kernel @ lists . infradead . org,
Hari . PrasathGE @ microchip . com, akpm @ linux-foundation . org,
deller @ gmx . de
Cc: Dharma Balasubiramani, Manikandan Muralidharan
In-Reply-To: <20240405043536.274220-1-dharma.b@microchip.com>
Add a new LVDS controller driver for sam9x7 which does the following:
- Prepares and enables the LVDS Peripheral clock
- Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself
to the global bridge list.
- Identifies its output endpoint as panel and adds it to the encoder
display pipeline
- Enables the LVDS serializer
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
---
Changelog
v4 -> v5
- Drop the unused variable 'format'.
- Use DRM wrapper for dev_err() to maintain uniformity.
- return -ENODEV instead of -EINVAL to maintain consistency with other DRM
bridge drivers.
v3 -> v4
- No changes.
v2 ->v3
- Correct Typo error "serializer".
- Consolidate get() and prepare() functions and use devm_clk_get_prepared().
- Remove unused variable 'ret' in probe().
- Use devm_pm_runtime_enable() and drop the mchp_lvds_remove().
v1 -> v2
- Drop 'res' variable and combine two lines into one.
- Handle deferred probe properly, use dev_err_probe().
- Don't print anything on deferred probe. Dropped print.
- Remove the MODULE_ALIAS and add MODULE_DEVICE_TABLE().
- symbol 'mchp_lvds_driver' was not declared. It should be static.
---
drivers/gpu/drm/bridge/Kconfig | 7 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/microchip-lvds.c | 228 ++++++++++++++++++++++++
3 files changed, 236 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/microchip-lvds.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index efd996f6c138..889098e2d65f 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -190,6 +190,13 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW
to DP++. This is used with the i.MX6 imx-ldb
driver. You are likely to say N here.
+config DRM_MICROCHIP_LVDS_SERIALIZER
+ tristate "Microchip LVDS serializer support"
+ depends on OF
+ depends on DRM_ATMEL_HLCDC
+ help
+ Support for Microchip's LVDS serializer.
+
config DRM_NWL_MIPI_DSI
tristate "Northwest Logic MIPI DSI Host controller"
depends on DRM
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 017b5832733b..7df87b582dca 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o
+obj-$(CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER) += microchip-lvds.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/bridge/microchip-lvds.c
new file mode 100644
index 000000000000..149704f498a6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/microchip-lvds.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Manikandan Muralidharan <manikandan.m@microchip.com>
+ * Author: Dharma Balasubiramani <dharma.b@microchip.com>
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/pinctrl/devinfo.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#define LVDS_POLL_TIMEOUT_MS 1000
+
+/* LVDSC register offsets */
+#define LVDSC_CR 0x00
+#define LVDSC_CFGR 0x04
+#define LVDSC_SR 0x0C
+#define LVDSC_WPMR 0xE4
+
+/* Bitfields in LVDSC_CR (Control Register) */
+#define LVDSC_CR_SER_EN BIT(0)
+
+/* Bitfields in LVDSC_CFGR (Configuration Register) */
+#define LVDSC_CFGR_PIXSIZE_24BITS 0
+#define LVDSC_CFGR_DEN_POL_HIGH 0
+#define LVDSC_CFGR_DC_UNBALANCED 0
+#define LVDSC_CFGR_MAPPING_JEIDA BIT(6)
+
+/*Bitfields in LVDSC_SR */
+#define LVDSC_SR_CS BIT(0)
+
+/* Bitfields in LVDSC_WPMR (Write Protection Mode Register) */
+#define LVDSC_WPMR_WPKEY_MASK GENMASK(31, 8)
+#define LVDSC_WPMR_WPKEY_PSSWD 0x4C5644
+
+struct mchp_lvds {
+ struct device *dev;
+ void __iomem *regs;
+ struct clk *pclk;
+ struct drm_panel *panel;
+ struct drm_bridge bridge;
+ struct drm_bridge *panel_bridge;
+};
+
+static inline struct mchp_lvds *bridge_to_lvds(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct mchp_lvds, bridge);
+}
+
+static inline u32 lvds_readl(struct mchp_lvds *lvds, u32 offset)
+{
+ return readl_relaxed(lvds->regs + offset);
+}
+
+static inline void lvds_writel(struct mchp_lvds *lvds, u32 offset, u32 val)
+{
+ writel_relaxed(val, lvds->regs + offset);
+}
+
+static void lvds_serialiser_on(struct mchp_lvds *lvds)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS);
+
+ /* The LVDSC registers can only be written if WPEN is cleared */
+ lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD &
+ LVDSC_WPMR_WPKEY_MASK));
+
+ /* Wait for the status of configuration registers to be changed */
+ while (lvds_readl(lvds, LVDSC_SR) & LVDSC_SR_CS) {
+ if (time_after(jiffies, timeout)) {
+ DRM_DEV_ERROR(lvds->dev, "%s: timeout error\n",
+ __func__);
+ return;
+ }
+ usleep_range(1000, 2000);
+ }
+
+ /* Configure the LVDSC */
+ lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA |
+ LVDSC_CFGR_DC_UNBALANCED |
+ LVDSC_CFGR_DEN_POL_HIGH |
+ LVDSC_CFGR_PIXSIZE_24BITS));
+
+ /* Enable the LVDS serializer */
+ lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN);
+}
+
+static int mchp_lvds_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct mchp_lvds *lvds = bridge_to_lvds(bridge);
+
+ bridge->encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
+
+ return drm_bridge_attach(bridge->encoder, lvds->panel_bridge,
+ bridge, flags);
+}
+
+static void mchp_lvds_enable(struct drm_bridge *bridge)
+{
+ struct mchp_lvds *lvds = bridge_to_lvds(bridge);
+ int ret;
+
+ ret = clk_enable(lvds->pclk);
+ if (ret < 0) {
+ DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret);
+ return;
+ }
+
+ ret = pm_runtime_get_sync(lvds->dev);
+ if (ret < 0) {
+ DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
+ clk_disable(lvds->pclk);
+ return;
+ }
+
+ lvds_serialiser_on(lvds);
+}
+
+static void mchp_lvds_disable(struct drm_bridge *bridge)
+{
+ struct mchp_lvds *lvds = bridge_to_lvds(bridge);
+
+ pm_runtime_put(lvds->dev);
+ clk_disable(lvds->pclk);
+}
+
+static const struct drm_bridge_funcs mchp_lvds_bridge_funcs = {
+ .attach = mchp_lvds_attach,
+ .enable = mchp_lvds_enable,
+ .disable = mchp_lvds_disable,
+};
+
+static int mchp_lvds_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mchp_lvds *lvds;
+ struct device_node *port;
+
+ if (!dev->of_node)
+ return -ENODEV;
+
+ lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
+ if (!lvds)
+ return -ENOMEM;
+
+ lvds->dev = dev;
+
+ lvds->regs = devm_ioremap_resource(lvds->dev,
+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
+ if (IS_ERR(lvds->regs))
+ return PTR_ERR(lvds->regs);
+
+ lvds->pclk = devm_clk_get_prepared(lvds->dev, "pclk");
+ if (IS_ERR(lvds->pclk))
+ return dev_err_probe(lvds->dev, PTR_ERR(lvds->pclk),
+ "could not get pclk_lvds prepared\n");
+
+ port = of_graph_get_remote_node(dev->of_node, 1, 0);
+ if (!port) {
+ DRM_DEV_ERROR(dev,
+ "can't find port point, please init lvds panel port!\n");
+ return -ENODEV;
+ }
+
+ lvds->panel = of_drm_find_panel(port);
+ of_node_put(port);
+
+ if (IS_ERR(lvds->panel))
+ return -EPROBE_DEFER;
+
+ lvds->panel_bridge = devm_drm_panel_bridge_add(dev, lvds->panel);
+
+ if (IS_ERR(lvds->panel_bridge))
+ return PTR_ERR(lvds->panel_bridge);
+
+ lvds->bridge.of_node = dev->of_node;
+ lvds->bridge.type = DRM_MODE_CONNECTOR_LVDS;
+ lvds->bridge.funcs = &mchp_lvds_bridge_funcs;
+
+ dev_set_drvdata(dev, lvds);
+ devm_pm_runtime_enable(dev);
+
+ drm_bridge_add(&lvds->bridge);
+
+ return 0;
+}
+
+static const struct of_device_id mchp_lvds_dt_ids[] = {
+ {
+ .compatible = "microchip,sam9x75-lvds",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mchp_lvds_dt_ids);
+
+static struct platform_driver mchp_lvds_driver = {
+ .probe = mchp_lvds_probe,
+ .driver = {
+ .name = "microchip-lvds",
+ .of_match_table = mchp_lvds_dt_ids,
+ },
+};
+module_platform_driver(mchp_lvds_driver);
+
+MODULE_AUTHOR("Manikandan Muralidharan <manikandan.m@microchip.com>");
+MODULE_AUTHOR("Dharma Balasubiramani <dharma.b@microchip.com>");
+MODULE_DESCRIPTION("Low Voltage Differential Signaling Controller Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
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^ permalink raw reply related
* [PATCH v5 0/4] LVDS Controller Support for SAM9X75 SoC
From: Dharma Balasubiramani @ 2024-04-05 4:35 UTC (permalink / raw)
To: andrzej . hajda @ intel . com, neil . armstrong @ linaro . org,
rfoss @ kernel . org, Laurent . pinchart @ ideasonboard . com,
jonas @ kwiboo . se, jernej . skrabec @ gmail . com,
maarten . lankhorst @ linux . intel . com, mripard @ kernel . org,
tzimmermann @ suse . de, airlied @ gmail . com,
daniel @ ffwll . ch, robh+dt @ kernel . org,
krzysztof . kozlowski+dt @ linaro . org, conor+dt @ kernel . org,
linux @ armlinux . org . uk, Nicolas . Ferre @ microchip . com,
alexandre . belloni @ bootlin . com,
claudiu . beznea @ tuxon . dev, Manikandan . M @ microchip . com,
Dharma . B @ microchip . com, arnd @ arndb . de,
geert+renesas @ glider . be, Jason @ zx2c4 . com,
mpe @ ellerman . id . au, gerg @ linux-m68k . org,
rdunlap @ infradead . org, vbabka @ suse . cz,
dri-devel @ lists . freedesktop . org,
devicetree @ vger . kernel . org,
linux-kernel @ vger . kernel . org,
linux-arm-kernel @ lists . infradead . org,
Hari . PrasathGE @ microchip . com, akpm @ linux-foundation . org,
deller @ gmx . de
Cc: Dharma Balasubiramani
This patch series introduces LVDS controller support for the SAM9X75 SoC. The
LVDS controller is designed to work with Microchip's sam9x7 series
System-on-Chip (SoC) devices, providing Low Voltage Differential Signaling
capabilities.
Patch series Changelog:
- Include configs: at91: Enable LVDS serializer
- include all necessary To/Cc entries.
The Individual Changelogs are available on the respective patches.
Dharma Balasubiramani (4):
dt-bindings: display: bridge: add sam9x75-lvds binding
drm/bridge: add lvds controller support for sam9x7
MAINTAINERS: add SAM9X7 SoC's LVDS controller
ARM: configs: at91: Enable LVDS serializer support
.../bridge/microchip,sam9x75-lvds.yaml | 55 +++++
MAINTAINERS | 8 +
arch/arm/configs/at91_dt_defconfig | 1 +
drivers/gpu/drm/bridge/Kconfig | 7 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/microchip-lvds.c | 228 ++++++++++++++++++
6 files changed, 300 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml
create mode 100644 drivers/gpu/drm/bridge/microchip-lvds.c
--
2.25.1
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^ permalink raw reply
* [PATCH v5 1/4] dt-bindings: display: bridge: add sam9x75-lvds binding
From: Dharma Balasubiramani @ 2024-04-05 4:35 UTC (permalink / raw)
To: andrzej . hajda @ intel . com, neil . armstrong @ linaro . org,
rfoss @ kernel . org, Laurent . pinchart @ ideasonboard . com,
jonas @ kwiboo . se, jernej . skrabec @ gmail . com,
maarten . lankhorst @ linux . intel . com, mripard @ kernel . org,
tzimmermann @ suse . de, airlied @ gmail . com,
daniel @ ffwll . ch, robh+dt @ kernel . org,
krzysztof . kozlowski+dt @ linaro . org, conor+dt @ kernel . org,
linux @ armlinux . org . uk, Nicolas . Ferre @ microchip . com,
alexandre . belloni @ bootlin . com,
claudiu . beznea @ tuxon . dev, Manikandan . M @ microchip . com,
Dharma . B @ microchip . com, arnd @ arndb . de,
geert+renesas @ glider . be, Jason @ zx2c4 . com,
mpe @ ellerman . id . au, gerg @ linux-m68k . org,
rdunlap @ infradead . org, vbabka @ suse . cz,
dri-devel @ lists . freedesktop . org,
devicetree @ vger . kernel . org,
linux-kernel @ vger . kernel . org,
linux-arm-kernel @ lists . infradead . org,
Hari . PrasathGE @ microchip . com, akpm @ linux-foundation . org,
deller @ gmx . de
Cc: Dharma Balasubiramani, Rob Herring
In-Reply-To: <20240405043536.274220-1-dharma.b@microchip.com>
Add the 'sam9x75-lvds' compatible binding, which describes the Low Voltage
Differential Signaling (LVDS) Controller found on some Microchip's sam9x7
series System-on-Chip (SoC) devices. This binding will be used to define
the properties and configuration for the LVDS Controller in DT.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changelog
v4 -> v5
- No changes.
v3 -> v4
- Rephrase the commit subject.
v2 -> v3
- No changes.
v1 -> v2
- Remove '|' in description, as there is no formatting to preserve.
- Remove 'gclk' from clock-names as there is only one clock(pclk).
- Remove the unused headers and include only used ones.
- Change the compatible name specific to SoC (sam9x75) instead of entire series.
- Change file name to match the compatible name.
---
.../bridge/microchip,sam9x75-lvds.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml
new file mode 100644
index 000000000000..862ef441ac9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip SAM9X75 LVDS Controller
+
+maintainers:
+ - Dharma Balasubiramani <dharma.b@microchip.com>
+
+description:
+ The Low Voltage Differential Signaling Controller (LVDSC) manages data
+ format conversion from the LCD Controller internal DPI bus to OpenLDI
+ LVDS output signals. LVDSC functions include bit mapping, balanced mode
+ management, and serializer.
+
+properties:
+ compatible:
+ const: microchip,sam9x75-lvds
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Peripheral Bus Clock
+
+ clock-names:
+ items:
+ - const: pclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/at91.h>
+ lvds-controller@f8060000 {
+ compatible = "microchip,sam9x75-lvds";
+ reg = <0xf8060000 0x100>;
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
+ clock-names = "pclk";
+ };
--
2.25.1
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^ permalink raw reply related
* [PATCH v5 3/4] MAINTAINERS: add SAM9X7 SoC's LVDS controller
From: Dharma Balasubiramani @ 2024-04-05 4:35 UTC (permalink / raw)
To: andrzej . hajda @ intel . com, neil . armstrong @ linaro . org,
rfoss @ kernel . org, Laurent . pinchart @ ideasonboard . com,
jonas @ kwiboo . se, jernej . skrabec @ gmail . com,
maarten . lankhorst @ linux . intel . com, mripard @ kernel . org,
tzimmermann @ suse . de, airlied @ gmail . com,
daniel @ ffwll . ch, robh+dt @ kernel . org,
krzysztof . kozlowski+dt @ linaro . org, conor+dt @ kernel . org,
linux @ armlinux . org . uk, Nicolas . Ferre @ microchip . com,
alexandre . belloni @ bootlin . com,
claudiu . beznea @ tuxon . dev, Manikandan . M @ microchip . com,
Dharma . B @ microchip . com, arnd @ arndb . de,
geert+renesas @ glider . be, Jason @ zx2c4 . com,
mpe @ ellerman . id . au, gerg @ linux-m68k . org,
rdunlap @ infradead . org, vbabka @ suse . cz,
dri-devel @ lists . freedesktop . org,
devicetree @ vger . kernel . org,
linux-kernel @ vger . kernel . org,
linux-arm-kernel @ lists . infradead . org,
Hari . PrasathGE @ microchip . com, akpm @ linux-foundation . org,
deller @ gmx . de
Cc: Dharma Balasubiramani
In-Reply-To: <20240405043536.274220-1-dharma.b@microchip.com>
Add the newly added LVDS controller for the SAM9X7 SoC to the existing
MAINTAINERS entry.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
Changelog
v4 -> v5
v3 -> v4
- No changes.
v2 -> v3
- Move the entry before "MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER".
v1 -> v2
- No Changes.
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa3b947fb080..3dd93dbe9542 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14562,6 +14562,14 @@ S: Supported
F: Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml
F: drivers/pwm/pwm-atmel.c
+MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER
+M: Manikandan Muralidharan <manikandan.m@microchip.com>
+M: Dharma Balasubiramani <dharma.b@microchip.com>
+L: dri-devel@lists.freedesktop.org
+S: Supported
+F: Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.yaml
+F: drivers/gpu/drm/bridge/microchip-lvds.c
+
MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER
M: Eugen Hristev <eugen.hristev@microchip.com>
L: linux-iio@vger.kernel.org
--
2.25.1
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^ permalink raw reply related
* [PATCH v5 4/4] ARM: configs: at91: Enable LVDS serializer support
From: Dharma Balasubiramani @ 2024-04-05 4:35 UTC (permalink / raw)
To: andrzej . hajda @ intel . com, neil . armstrong @ linaro . org,
rfoss @ kernel . org, Laurent . pinchart @ ideasonboard . com,
jonas @ kwiboo . se, jernej . skrabec @ gmail . com,
maarten . lankhorst @ linux . intel . com, mripard @ kernel . org,
tzimmermann @ suse . de, airlied @ gmail . com,
daniel @ ffwll . ch, robh+dt @ kernel . org,
krzysztof . kozlowski+dt @ linaro . org, conor+dt @ kernel . org,
linux @ armlinux . org . uk, Nicolas . Ferre @ microchip . com,
alexandre . belloni @ bootlin . com,
claudiu . beznea @ tuxon . dev, Manikandan . M @ microchip . com,
Dharma . B @ microchip . com, arnd @ arndb . de,
geert+renesas @ glider . be, Jason @ zx2c4 . com,
mpe @ ellerman . id . au, gerg @ linux-m68k . org,
rdunlap @ infradead . org, vbabka @ suse . cz,
dri-devel @ lists . freedesktop . org,
devicetree @ vger . kernel . org,
linux-kernel @ vger . kernel . org,
linux-arm-kernel @ lists . infradead . org,
Hari . PrasathGE @ microchip . com, akpm @ linux-foundation . org,
deller @ gmx . de
Cc: Hari Prasath Gujulan Elango, Dharma Balasubiramani
In-Reply-To: <20240405043536.274220-1-dharma.b@microchip.com>
Enable LVDS serializer support for display pipeline.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Acked-by: Hari Prasath Gujulan Elango <hari.prasathge@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
Changelog
v4 -> v5
v3 -> v4
v2 -> v3
- No Changes.
---
arch/arm/configs/at91_dt_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 1d53aec4c836..6eabe2313c9a 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -143,6 +143,7 @@ CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV7740=m
CONFIG_DRM=y
CONFIG_DRM_ATMEL_HLCDC=y
+CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=y
CONFIG_FB_ATMEL=y
--
2.25.1
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^ permalink raw reply related
* RE: [PATCH 00/11] drm/exynos: drop driver owner initialization
From: 대인기/Tizen Platform Lab(SR)/삼성전자 @ 2024-04-05 5:11 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', 'Seung-Woo Kim',
'Kyungmin Park', 'David Airlie',
'Daniel Vetter', 'Alim Akhtar'
Cc: dri-devel, linux-arm-kernel, linux-samsung-soc, linux-kernel
In-Reply-To: <20240330-b4-module-owner-drm-exynos-v1-0-3fa30e2c7e5a@linaro.org>
Hi Krzysztof,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Sunday, March 31, 2024 5:33 AM
> To: Inki Dae <inki.dae@samsung.com>; Seung-Woo Kim
> <sw0312.kim@samsung.com>; Kyungmin Park <kyungmin.park@samsung.com>; David
> Airlie <airlied@gmail.com>; Daniel Vetter <daniel@ffwll.ch>; Krzysztof
> Kozlowski <krzysztof.kozlowski@linaro.org>; Alim Akhtar
> <alim.akhtar@samsung.com>
> Cc: dri-devel@lists.freedesktop.org; linux-arm-kernel@lists.infradead.org;
> linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH 00/11] drm/exynos: drop driver owner initialization
>
> Simplify the code by dropping unnecessary .owner initialization in the
> driver.
Applied.
Thanks. :)
Inki Dae
>
> Best regards,
> Krzysztof
>
> ---
> Krzysztof Kozlowski (11):
> drm/exynos: fimc: drop driver owner initialization
> drm/exynos: fimd: drop driver owner initialization
> drm/exynos: dsi: drop driver owner initialization
> drm/exynos: g2d: drop driver owner initialization
> drm/exynos: gsc: drop driver owner initialization
> drm/exynos: mic: drop driver owner initialization
> drm/exynos: rotator: drop driver owner initialization
> drm/exynos: scaler: drop driver owner initialization
> drm/exynos: vidi: drop driver owner initialization
> drm/exynos: hdmi: drop driver owner initialization
> drm/exynos: mixer: drop driver owner initialization
>
> drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_fimc.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_g2d.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_gsc.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_mic.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_rotator.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_scaler.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_vidi.c | 1 -
> drivers/gpu/drm/exynos/exynos_hdmi.c | 1 -
> drivers/gpu/drm/exynos/exynos_mixer.c | 1 -
> 11 files changed, 11 deletions(-)
> ---
> base-commit: 7fdcff3312e16ba8d1419f8a18f465c5cc235ecf
> change-id: 20240330-b4-module-owner-drm-exynos-d2f1b2d48af3
>
> Best regards,
> --
> Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
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^ permalink raw reply
* Re: [PATCH] dt-bindings: mfd: syscon: Add ti,am62p-cpsw-mac-efuse compatible
From: Siddharth Vadapalli @ 2024-04-05 5:21 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Siddharth Vadapalli, lee, robh, krzk+dt, conor+dt, devicetree,
linux-kernel, linux-arm-kernel, srk
In-Reply-To: <a895ddc8-5c18-49d7-86c4-b995bb946914@ti.com>
On Thu, Apr 04, 2024 at 02:02:21PM +0530, Siddharth Vadapalli wrote:
> On Wed, Apr 03, 2024 at 12:18:10PM +0530, Siddharth Vadapalli wrote:
> > On Wed, Apr 03, 2024 at 08:40:19AM +0200, Krzysztof Kozlowski wrote:
> > > On 03/04/2024 08:32, Siddharth Vadapalli wrote:
> > > > On Wed, Apr 03, 2024 at 08:27:06AM +0200, Krzysztof Kozlowski wrote:
> > > >> On 03/04/2024 07:35, Siddharth Vadapalli wrote:
> > > >>> On Tue, Apr 02, 2024 at 08:06:27PM +0200, Krzysztof Kozlowski wrote:
> > > >>>> On 02/04/2024 14:30, Siddharth Vadapalli wrote:
> > > >>>>> On Tue, Apr 02, 2024 at 02:08:32PM +0200, Krzysztof Kozlowski wrote:
> > > >>>>>> On 02/04/2024 12:57, Siddharth Vadapalli wrote:
> > > >>>>>>> The CTRLMMR_MAC_IDx registers within the CTRL_MMR space of TI's AM62p SoC
> > > >>>>>>> contain the MAC Address programmed in the eFuse. Add compatible for
> > > >>>>>>> allowing the CPSW driver to obtain a regmap for the CTRLMMR_MAC_IDx
> > > >>>>>>> registers within the System Controller device-tree node. The default MAC
> > > >>>>>>> Address for the interface corresponding to the first MAC port will be set
> > > >>>>>>> to the value programmed in the eFuse.
> > > >>>>>>>
> > > >>>>>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > >>>>>>> ---
> > > >>>>>>>
> > > >>>>>>> This patch is based on linux-next tagged next-20240402.
> > > >>>>>>
> > > >>>>>> Where is the DTS using it?
> > > >>>>>
> > > >>>>> The current implementation in the device-tree for older TI K3 SoCs is as
> > > >>>>> follows:
> > > >>>>>
> > > >>>>> cpsw_port1: port@1 {
> > > >>>>> reg = <1>;
> > > >>>>> ti,mac-only;
> > > >>>>> label = "port1";
> > > >>>>> phys = <&phy_gmii_sel 1>;
> > > >>>>> mac-address = [00 00 00 00 00 00];
> > > >>>>> ti,syscon-efuse = <&wkup_conf 0x200>;
> > > >>>>> };
> > > >>>>>
> > > >>>>> The "ti,syscon-efuse" property passes the reference to the System
> > > >>>>> Controller node as well as the offset to the CTRLMMR_MAC_IDx registers
> > > >>>>> within the CTRL_MMR space.
> > > >>>>
> > > >>>> Please reference upstream DTS or lore link to patch under review.
> > > >>>
> > > >>> An example of the existing implementation in the device-tree for AM64x
> > > >>> is:
> > > >>> https://github.com/torvalds/linux/blob/d4e8c8ad5d14ad51ed8813442d81c43019fd669d/arch/arm64/boot/dts/ti/k3-am64-main.dtsi#L697
> > > >>> It uses:
> > > >>> ti,syscon-efuse = <&main_conf 0x200>;
> > > >>>
> > > >>> and "main_conf" node is defined at:
> > > >>> https://github.com/torvalds/linux/blob/d4e8c8ad5d14ad51ed8813442d81c43019fd669d/arch/arm64/boot/dts/ti/k3-am64-main.dtsi#L40
> > > >>
> > > >> It is quite different than your bindings, so your bindings are incorrect.
> > > >
> > > > Sorry I didn't understand what you mean. The references I have provided
> > > > are for existing DTS where "main_conf"/"wkup_conf" (System Controller
> > > > nodes) have the compatible "syscon", unlike in AM62p at:
> > > > https://github.com/torvalds/linux/blob/20f8173afaac90dd9dca11be4aa602a47776077f/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi#L8
> > > > which has the "simple-bus" compatible for the "wkup_conf" node.
> > > >
> > > > Also, shouldn't the device-tree bindings patches be posted first and get
> > > > merged before I post the device-tree patches that utilize the
> > > > compatible/properties that have been added in the bindings? That is the
> > > > reason why I had shared the "DIFF" for the DTS changes that I will be
> > > > posting once this patch for the new compatible is accepted.
> > > >
> > >
> > > That's not the process. I will be NAKing bindings which do not have any
> > > users, because I do not trust you test them.
> > >
> > > The process is almost always:
> > > 1. Send bindings,
> > > 2. Send driver changes (if applicable) in the same patchset.
> > > 3. Send DTS, usually in separate patches and provide lore link to the
> > > bindings in the changelog or cover letter.
> >
> > Thank you for clarifying. I will post the DTS patches corresponding to
> > this patch and reference this patch in the DTS patch series.
>
> I have posted the DTS patch at:
> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240404081845.622707-1-s-vadapalli@ti.com/
> indicating the dependency on this bindings patch.
Hello Krzysztof,
Do I have to post a v2 for this patch? You had Acked it initially but I
am not sure if the discussion so far will make it unclear to readers
regarding the acceptance of this patch. Thank you for Acking the v3 DTS
patch at:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240404124614.891416-1-s-vadapalli@ti.com/
Since the v3 DTS patch mentions this bindings patch as a dependency, I
wanted to be sure whether I have to post a v2 for this or that won't be
required.
Regards,
Siddharth.
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^ permalink raw reply
* [PATCH 14/15] tty: atmel_serial: define macro for RX size
From: Jiri Slaby (SUSE) @ 2024-04-05 6:08 UTC (permalink / raw)
To: gregkh
Cc: Alexandre Belloni, Richard Genoud, linux-kernel, linux-serial,
Claudiu Beznea, Jiri Slaby (SUSE), linux-arm-kernel
In-Reply-To: <20240405060826.2521-1-jirislaby@kernel.org>
It is repeated in the code and there is also a big warning by
ATMEL_SERIAL_RINGSIZE. So define ATMEL_SERIAL_RX_SIZE and use it
appropriatelly.
The macro uses array_size() and kmalloc_array() is switched to
kmalloc().
Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org>
Cc: Richard Genoud <richard.genoud@gmail.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: linux-arm-kernel@lists.infradead.org
---
drivers/tty/serial/atmel_serial.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 69ec80ffc97b..5cde5077c429 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -96,7 +96,9 @@ struct atmel_uart_char {
* can contain up to 1024 characters in PIO mode and up to 4096 characters in
* DMA mode.
*/
-#define ATMEL_SERIAL_RINGSIZE 1024
+#define ATMEL_SERIAL_RINGSIZE 1024
+#define ATMEL_SERIAL_RX_SIZE array_size(sizeof(struct atmel_uart_char), \
+ ATMEL_SERIAL_RINGSIZE)
/*
* at91: 6 USARTs and one DBGU port (SAM9260)
@@ -1208,7 +1210,7 @@ static int atmel_prepare_rx_dma(struct uart_port *port)
BUG_ON(!PAGE_ALIGNED(ring->buf));
sg_set_page(&atmel_port->sg_rx,
virt_to_page(ring->buf),
- sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
+ ATMEL_SERIAL_RX_SIZE,
offset_in_page(ring->buf));
nent = dma_map_sg(port->dev,
&atmel_port->sg_rx,
@@ -2947,9 +2949,7 @@ static int atmel_serial_probe(struct platform_device *pdev)
if (!atmel_use_pdc_rx(&atmel_port->uart)) {
ret = -ENOMEM;
- data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
- sizeof(struct atmel_uart_char),
- GFP_KERNEL);
+ data = kmalloc(ATMEL_SERIAL_RX_SIZE, GFP_KERNEL);
if (!data)
goto err_clk_disable_unprepare;
atmel_port->rx_ring.buf = data;
--
2.44.0
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^ permalink raw reply related
* [PATCH 15/15] tty: atmel_serial: use single DMA mapping for RX
From: Jiri Slaby (SUSE) @ 2024-04-05 6:08 UTC (permalink / raw)
To: gregkh
Cc: Alexandre Belloni, Richard Genoud, linux-kernel, linux-serial,
Claudiu Beznea, Jiri Slaby (SUSE), linux-arm-kernel
In-Reply-To: <20240405060826.2521-1-jirislaby@kernel.org>
dma_map_single() provides much easier interface for simple mappings as
used for RX in atmel_serial. So switch to that, removing all the s-g
unnecessary handling.
Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org>
Cc: Richard Genoud <richard.genoud@gmail.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: linux-arm-kernel@lists.infradead.org
---
drivers/tty/serial/atmel_serial.c | 56 ++++++++++++-------------------
1 file changed, 22 insertions(+), 34 deletions(-)
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 5cde5077c429..0a90964d6d10 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -135,7 +135,7 @@ struct atmel_uart_port {
dma_cookie_t cookie_tx;
dma_cookie_t cookie_rx;
dma_addr_t tx_phys;
- struct scatterlist sg_rx;
+ dma_addr_t rx_phys;
struct tasklet_struct tasklet_rx;
struct tasklet_struct tasklet_tx;
atomic_t tasklet_shutdown;
@@ -1088,8 +1088,8 @@ static void atmel_release_rx_dma(struct uart_port *port)
if (chan) {
dmaengine_terminate_all(chan);
dma_release_channel(chan);
- dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
- DMA_FROM_DEVICE);
+ dma_unmap_single(port->dev, atmel_port->rx_phys,
+ ATMEL_SERIAL_RX_SIZE, DMA_FROM_DEVICE);
}
atmel_port->desc_rx = NULL;
@@ -1122,10 +1122,8 @@ static void atmel_rx_from_dma(struct uart_port *port)
}
/* CPU claims ownership of RX DMA buffer */
- dma_sync_sg_for_cpu(port->dev,
- &atmel_port->sg_rx,
- 1,
- DMA_FROM_DEVICE);
+ dma_sync_single_for_cpu(port->dev, atmel_port->rx_phys,
+ ATMEL_SERIAL_RX_SIZE, DMA_FROM_DEVICE);
/*
* ring->head points to the end of data already written by the DMA.
@@ -1134,8 +1132,8 @@ static void atmel_rx_from_dma(struct uart_port *port)
* The current transfer size should not be larger than the dma buffer
* length.
*/
- ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
- BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
+ ring->head = ATMEL_SERIAL_RX_SIZE - state.residue;
+ BUG_ON(ring->head > ATMEL_SERIAL_RX_SIZE);
/*
* At this point ring->head may point to the first byte right after the
* last byte of the dma buffer:
@@ -1149,7 +1147,7 @@ static void atmel_rx_from_dma(struct uart_port *port)
* tail to the end of the buffer then reset tail.
*/
if (ring->head < ring->tail) {
- count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
+ count = ATMEL_SERIAL_RX_SIZE - ring->tail;
tty_insert_flip_string(tport, ring->buf + ring->tail, count);
ring->tail = 0;
@@ -1162,17 +1160,15 @@ static void atmel_rx_from_dma(struct uart_port *port)
tty_insert_flip_string(tport, ring->buf + ring->tail, count);
/* Wrap ring->head if needed */
- if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
+ if (ring->head >= ATMEL_SERIAL_RX_SIZE)
ring->head = 0;
ring->tail = ring->head;
port->icount.rx += count;
}
/* USART retreives ownership of RX DMA buffer */
- dma_sync_sg_for_device(port->dev,
- &atmel_port->sg_rx,
- 1,
- DMA_FROM_DEVICE);
+ dma_sync_single_for_device(port->dev, atmel_port->rx_phys,
+ ATMEL_SERIAL_RX_SIZE, DMA_FROM_DEVICE);
tty_flip_buffer_push(tport);
@@ -1188,7 +1184,7 @@ static int atmel_prepare_rx_dma(struct uart_port *port)
struct dma_slave_config config;
struct circ_buf *ring;
struct dma_chan *chan;
- int ret, nent;
+ int ret;
ring = &atmel_port->rx_ring;
@@ -1205,26 +1201,18 @@ static int atmel_prepare_rx_dma(struct uart_port *port)
dma_chan_name(atmel_port->chan_rx));
spin_lock_init(&atmel_port->lock_rx);
- sg_init_table(&atmel_port->sg_rx, 1);
/* UART circular rx buffer is an aligned page. */
BUG_ON(!PAGE_ALIGNED(ring->buf));
- sg_set_page(&atmel_port->sg_rx,
- virt_to_page(ring->buf),
- ATMEL_SERIAL_RX_SIZE,
- offset_in_page(ring->buf));
- nent = dma_map_sg(port->dev,
- &atmel_port->sg_rx,
- 1,
- DMA_FROM_DEVICE);
-
- if (!nent) {
+ atmel_port->rx_phys = dma_map_single(port->dev, ring->buf,
+ ATMEL_SERIAL_RX_SIZE,
+ DMA_FROM_DEVICE);
+
+ if (dma_mapping_error(port->dev, atmel_port->rx_phys)) {
dev_dbg(port->dev, "need to release resource of dma\n");
goto chan_err;
} else {
- dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
- sg_dma_len(&atmel_port->sg_rx),
- ring->buf,
- &sg_dma_address(&atmel_port->sg_rx));
+ dev_dbg(port->dev, "%s: mapped %zu@%p to %pad\n", __func__,
+ ATMEL_SERIAL_RX_SIZE, ring->buf, &atmel_port->rx_phys);
}
/* Configure the slave DMA */
@@ -1245,9 +1233,9 @@ static int atmel_prepare_rx_dma(struct uart_port *port)
* each one is half ring buffer size
*/
desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
- sg_dma_address(&atmel_port->sg_rx),
- sg_dma_len(&atmel_port->sg_rx),
- sg_dma_len(&atmel_port->sg_rx)/2,
+ atmel_port->rx_phys,
+ ATMEL_SERIAL_RX_SIZE,
+ ATMEL_SERIAL_RX_SIZE / 2,
DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT);
if (!desc) {
--
2.44.0
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^ permalink raw reply related
* [PATCH 13/15] tty: atmel_serial: use single DMA mapping for TX
From: Jiri Slaby (SUSE) @ 2024-04-05 6:08 UTC (permalink / raw)
To: gregkh
Cc: Alexandre Belloni, Richard Genoud, linux-kernel, linux-serial,
Claudiu Beznea, Jiri Slaby (SUSE), linux-arm-kernel
In-Reply-To: <20240405060826.2521-1-jirislaby@kernel.org>
dma_map_single() provides much easier interface for simple mappings as
used for TX in atmel_serial. So switch to that, removing all the s-g
unnecessary handling.
Note that it is not easy (maybe impossible) to use kfifo_dma_* API for
atmel's serial purposes. It handles DMA very specially.
Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org>
Cc: Richard Genoud <richard.genoud@gmail.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: linux-arm-kernel@lists.infradead.org
---
drivers/tty/serial/atmel_serial.c | 35 +++++++++++++------------------
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 5bb5e4303754..69ec80ffc97b 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -132,7 +132,7 @@ struct atmel_uart_port {
struct dma_async_tx_descriptor *desc_rx;
dma_cookie_t cookie_tx;
dma_cookie_t cookie_rx;
- struct scatterlist sg_tx;
+ dma_addr_t tx_phys;
struct scatterlist sg_rx;
struct tasklet_struct tasklet_rx;
struct tasklet_struct tasklet_tx;
@@ -904,8 +904,8 @@ static void atmel_release_tx_dma(struct uart_port *port)
if (chan) {
dmaengine_terminate_all(chan);
dma_release_channel(chan);
- dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
- DMA_TO_DEVICE);
+ dma_unmap_single(port->dev, atmel_port->tx_phys,
+ UART_XMIT_SIZE, DMA_TO_DEVICE);
}
atmel_port->desc_tx = NULL;
@@ -922,7 +922,7 @@ static void atmel_tx_dma(struct uart_port *port)
struct tty_port *tport = &port->state->port;
struct dma_chan *chan = atmel_port->chan_tx;
struct dma_async_tx_descriptor *desc;
- struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
+ struct scatterlist sgl[2], *sg;
unsigned int tx_len, tail, part1_len, part2_len, sg_len;
dma_addr_t phys_addr;
@@ -955,7 +955,7 @@ static void atmel_tx_dma(struct uart_port *port)
sg_init_table(sgl, 2);
sg_len = 0;
- phys_addr = sg_dma_address(sg_tx) + tail;
+ phys_addr = atmel_port->tx_phys + tail;
if (part1_len) {
sg = &sgl[sg_len++];
sg_dma_address(sg) = phys_addr;
@@ -987,7 +987,8 @@ static void atmel_tx_dma(struct uart_port *port)
return;
}
- dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
+ dma_sync_single_for_device(port->dev, atmel_port->tx_phys,
+ UART_XMIT_SIZE, DMA_TO_DEVICE);
atmel_port->desc_tx = desc;
desc->callback = atmel_complete_tx_dma;
@@ -1014,7 +1015,7 @@ static int atmel_prepare_tx_dma(struct uart_port *port)
dma_cap_mask_t mask;
struct dma_slave_config config;
struct dma_chan *chan;
- int ret, nent;
+ int ret;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
@@ -1029,26 +1030,18 @@ static int atmel_prepare_tx_dma(struct uart_port *port)
dma_chan_name(atmel_port->chan_tx));
spin_lock_init(&atmel_port->lock_tx);
- sg_init_table(&atmel_port->sg_tx, 1);
/* UART circular tx buffer is an aligned page. */
BUG_ON(!PAGE_ALIGNED(tport->xmit_buf));
- sg_set_page(&atmel_port->sg_tx,
- virt_to_page(tport->xmit_buf),
- UART_XMIT_SIZE,
- offset_in_page(tport->xmit_buf));
- nent = dma_map_sg(port->dev,
- &atmel_port->sg_tx,
- 1,
- DMA_TO_DEVICE);
+ atmel_port->tx_phys = dma_map_single(port->dev, tport->xmit_buf,
+ UART_XMIT_SIZE, DMA_TO_DEVICE);
- if (!nent) {
+ if (dma_mapping_error(port->dev, atmel_port->tx_phys)) {
dev_dbg(port->dev, "need to release resource of dma\n");
goto chan_err;
} else {
- dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
- sg_dma_len(&atmel_port->sg_tx),
- tport->xmit_buf,
- &sg_dma_address(&atmel_port->sg_tx));
+ dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", __func__,
+ UART_XMIT_SIZE, tport->xmit_buf,
+ &atmel_port->tx_phys);
}
/* Configure the slave DMA */
--
2.44.0
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^ permalink raw reply related
* Re: [PATCH 1/1] arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960/wm8962 and sai[0,1,4,5]
From: Francesco Dolcini @ 2024-04-05 6:36 UTC (permalink / raw)
To: Frank Li
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <20240404161914.1655305-1-Frank.Li@nxp.com>
Hello Frank,
On Thu, Apr 04, 2024 at 12:19:13PM -0400, Frank Li wrote:
> imx8qxp-mek use two kind audio codec, wm8960 and wm8962. Using dummy gpio
> i2c bus mux to connect both i2c devices. One will probe failure and other
> will probe success when devices driver check whoami. So one dtb can cover
> both board configuration.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 210 ++++++++++++++++++
> 1 file changed, 210 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index 8360bb851ac03..adff87c7cf305 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -44,6 +51,105 @@ usb3_data_ss: endpoint {
[...]
> + /*
> + * This dummy i2c mux. GPIO actually will not impact selection. At actual boards, only 1
> + * device connectted. I2C client driver will check ID when probe. Only matched ID's driver
> + * probe successfully.
> + */
> + i2cvmux: i2cmux {
> + compatible = "i2c-mux-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mux-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; /* use an unused gpio */
There is for sure people that have more experience and competency that
me and it would be interesting to hear their feedback, but this
looks like a bad hack, and you are just playing with the driver
behavior to ensure that you get what you need.
Francesco
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* Re: [PATCH 1/1] arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960/wm8962 and sai[0,1,4,5]
From: Krzysztof Kozlowski @ 2024-04-05 6:41 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <20240404161914.1655305-1-Frank.Li@nxp.com>
On 04/04/2024 18:19, Frank Li wrote:
> imx8qxp-mek use two kind audio codec, wm8960 and wm8962. Using dummy gpio
> i2c bus mux to connect both i2c devices. One will probe failure and other
> will probe success when devices driver check whoami. So one dtb can cover
> both board configuration.
I don't understand it. Either you add real device or not. If one board
has two devices, then why do you need to check for failures?
Anyway, don't add fake stuff to DTS.
NAK.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 210 ++++++++++++++++++
> 1 file changed, 210 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index 8360bb851ac03..adff87c7cf305 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -30,6 +30,13 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
> enable-active-high;
> };
>
> + reg_audio: regulator-wm8962 {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_aud";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> gpio-sbu-mux {
> compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
> pinctrl-names = "default";
> @@ -44,6 +51,105 @@ usb3_data_ss: endpoint {
> };
> };
> };
> +
> + sound-wm8960 {
> + compatible = "fsl,imx-audio-wm8960";
> + model = "wm8960-audio";
> + audio-cpu = <&sai1>;
> + audio-codec = <&wm8960>;
> + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
> + audio-routing =
> + "Headphone Jack", "HP_L",
> + "Headphone Jack", "HP_R",
> + "Ext Spk", "SPK_LP",
> + "Ext Spk", "SPK_LN",
> + "Ext Spk", "SPK_RP",
> + "Ext Spk", "SPK_RN",
> + "LINPUT1", "Mic Jack",
> + "Mic Jack", "MICB";
> + };
> +
> + sound-wm8962 {
> + compatible = "fsl,imx-audio-wm8962";
> + model = "wm8962-audio";
> + audio-cpu = <&sai1>;
> + audio-codec = <&wm8962>;
> + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
> + audio-routing =
> + "Headphone Jack", "HPOUTL",
> + "Headphone Jack", "HPOUTR",
> + "Ext Spk", "SPKOUTL",
> + "Ext Spk", "SPKOUTR",
> + "AMIC", "MICBIAS",
> + "IN3R", "AMIC",
> + "IN1R", "AMIC";
> + };
> +
> + /*
> + * This dummy i2c mux. GPIO actually will not impact selection. At actual boards, only 1
> + * device connectted. I2C client driver will check ID when probe. Only matched ID's driver
> + * probe successfully.
NAK
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH v2 1/5] ARM: dts: aspeed: greatlakes: correct Mellanox multi-host property
From: Krzysztof Kozlowski @ 2024-04-05 6:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Cc: Krzysztof Kozlowski
"mlx,multi-host" is using incorrect vendor prefix and is not documented.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v2:
1. None
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
index 7a53f54833a0..9a6757dd203f 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
@@ -66,7 +66,7 @@ &mac3 {
pinctrl-0 = <&pinctrl_rmii4_default>;
no-hw-checksum;
use-ncsi;
- mlx,multi-host;
+ mellanox,multi-host;
ncsi-ctrl,start-redo-probe;
ncsi-ctrl,no-channel-monitor;
ncsi-package = <1>;
--
2.34.1
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* [PATCH v2 3/5] ARM: dts: aspeed: yosemitev2: correct Mellanox multi-host property
From: Krzysztof Kozlowski @ 2024-04-05 6:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20240405064624.18997-1-krzysztof.kozlowski@linaro.org>
"mlx,multi-host" is using incorrect vendor prefix and is not documented.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v2:
1. None
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts
index 6bf2ff85a40e..5143f85fbd70 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts
@@ -95,7 +95,7 @@ &mac0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
- mlx,multi-host;
+ mellanox,multi-host;
};
&adc {
--
2.34.1
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* [PATCH v2 2/5] ARM: dts: aspeed: yosemite4: correct Mellanox multi-host property
From: Krzysztof Kozlowski @ 2024-04-05 6:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20240405064624.18997-1-krzysztof.kozlowski@linaro.org>
"mlx,multi-host" is using incorrect vendor prefix and is not documented.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v2:
1. None
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 64075cc41d92..1bd555a6c3ba 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -88,7 +88,7 @@ &mac2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii3_default>;
use-ncsi;
- mlx,multi-host;
+ mellanox,multi-host;
};
&mac3 {
@@ -96,7 +96,7 @@ &mac3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii4_default>;
use-ncsi;
- mlx,multi-host;
+ mellanox,multi-host;
};
&fmc {
--
2.34.1
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* [PATCH v2 5/5] ARM: dts: aspeed: drop unused ref_voltage ADC property
From: Krzysztof Kozlowski @ 2024-04-05 6:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20240405064624.18997-1-krzysztof.kozlowski@linaro.org>
Aspeed ADC "ref_voltage" property is neither documented nor used.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v2:
1. None
---
arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts | 1 -
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts | 2 --
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 2 --
3 files changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
index 7b540880cef9..3c8925034a8c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
@@ -813,7 +813,6 @@ bmc_ast2600_cpu: temperature-sensor@35 {
};
&adc0 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
index 9a6757dd203f..998598c15fd0 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts
@@ -211,7 +211,6 @@ &i2c13 {
};
&adc0 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
@@ -220,7 +219,6 @@ &pinctrl_adc4_default &pinctrl_adc5_default
};
&adc1 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc10_default
&pinctrl_adc11_default &pinctrl_adc12_default
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 1bd555a6c3ba..b4d003cbae8b 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -596,7 +596,6 @@ i2c-mux@72 {
};
&adc0 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
@@ -605,7 +604,6 @@ &pinctrl_adc4_default &pinctrl_adc5_default
};
&adc1 {
- ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>;
};
--
2.34.1
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* [PATCH v2 4/5] ARM: dts: aspeed: harma: correct Mellanox multi-host property
From: Krzysztof Kozlowski @ 2024-04-05 6:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20240405064624.18997-1-krzysztof.kozlowski@linaro.org>
"mlx,multi-host" is using incorrect vendor prefix and is not documented.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v2:
1. New patch
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
index bbbab8023cd6..b2834399f3d1 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts
@@ -137,7 +137,7 @@ &mac3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii4_default>;
use-ncsi;
- mlx,multi-host;
+ mellanox,multi-host;
};
&rtc {
--
2.34.1
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* Re: [PATCH 1/4] ARM: dts: aspeed: greatlakes: correct Mellanox multi-host property
From: Krzysztof Kozlowski @ 2024-04-05 6:48 UTC (permalink / raw)
To: Andrew Jeffery, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <65060691d4649c4a8da46e5ba762a3c905ade690.camel@codeconstruct.com.au>
On 05/04/2024 01:21, Andrew Jeffery wrote:
>>>
>>> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au>
>>>
>>> I'm working to stay on top of things a bit more now than I have in the
>>> recent past, so hopefully I won't miss patches again in the future.
>>
>> Stephen reported conflict, although trivial, but maybe better if you
>> take them?
>>
>
> Yeah, happy to.
>
>> I can rebase and resend.
I dropped these patches (and one more) from my tree, rebased and resent
everything as v2.
Thanks!
Best regards,
Krzysztof
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