* Re: [PATCH v3 06/10] perf/dwc_pcie: Avoid placing cpumask on the stack
From: Shuai Xue @ 2024-04-08 0:30 UTC (permalink / raw)
To: Dawei Li, will, mark.rutland, yury.norov, linux
Cc: renyu.zj, yangyicong, jonathan.cameron, andersson, konrad.dybcio,
linux-arm-kernel, linux-kernel, linux-arm-msm
In-Reply-To: <20240403155950.2068109-7-dawei.li@shingroup.cn>
On 2024/4/3 23:59, Dawei Li wrote:
> In general it's preferable to avoid placing cpumasks on the stack, as
> for large values of NR_CPUS these can consume significant amounts of
> stack space and make stack overflows more likely.
>
> Use cpumask_any_and_but() to avoid the need for a temporary cpumask on
> the stack.
>
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Reviewed-by: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Dawei Li <dawei.li@shingroup.cn>
Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com>
Thank you.
Shuai
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [RFC PATCH v2 4/5] clk: meson: a1: add the audio clock controller driver
From: Jan Dakinevich @ 2024-04-08 1:07 UTC (permalink / raw)
To: Jerome Brunet
Cc: Neil Armstrong, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Martin Blumenstingl, Philipp Zabel, linux-amlogic, linux-clk,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <1j34s3iy9c.fsf@starbuckisacylon.baylibre.com>
On 4/2/24 18:11, Jerome Brunet wrote:
>
> On Thu 28 Mar 2024 at 04:08, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>
>> This controller provides clocks and reset functionality for audio
>> peripherals on Amlogic A1 SoC family.
>>
>> The driver is almost identical to 'axg-audio', however it would be better
>> to keep it separate due to following reasons:
>>
>> - significant amount of bits has another definition. I will bring there
>> a mess of new defines with A1_ suffixes.
>>
>> - registers of this controller are located in two separate regions. It
>> will give a lot of complications for 'axg-audio' to support this.
>>
>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> ---
>> drivers/clk/meson/Kconfig | 13 +
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/a1-audio.c | 624 +++++++++++++++++++++++++++++++++++
>> drivers/clk/meson/a1-audio.h | 45 +++
>> 4 files changed, 683 insertions(+)
>> create mode 100644 drivers/clk/meson/a1-audio.c
>> create mode 100644 drivers/clk/meson/a1-audio.h
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index d6a2fa5f7e88..80c4a18c83d2 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -133,6 +133,19 @@ config COMMON_CLK_A1_PERIPHERALS
>> device, A1 SoC Family. Say Y if you want A1 Peripherals clock
>> controller to work.
>>
>> +config COMMON_CLK_A1_AUDIO
>> + tristate "Amlogic A1 SoC Audio clock controller support"
>> + depends on ARM64
>> + select COMMON_CLK_MESON_REGMAP
>> + select COMMON_CLK_MESON_CLKC_UTILS
>> + select COMMON_CLK_MESON_PHASE
>> + select COMMON_CLK_MESON_SCLK_DIV
>> + select COMMON_CLK_MESON_AUDIO_RSTC
>> + help
>> + Support for the Audio clock controller on Amlogic A113L based
>> + device, A1 SoC Family. Say Y if you want A1 Audio clock controller
>> + to work.
>> +
>> config COMMON_CLK_G12A
>> tristate "G12 and SM1 SoC clock controllers support"
>> depends on ARM64
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 88d94921a4dc..4968fc7ad555 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
>> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
>> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
>> +obj-$(CONFIG_COMMON_CLK_A1_AUDIO) += a1-audio.o
>> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
>> diff --git a/drivers/clk/meson/a1-audio.c b/drivers/clk/meson/a1-audio.c
>> new file mode 100644
>> index 000000000000..bd2b6dde75d4
>> --- /dev/null
>> +++ b/drivers/clk/meson/a1-audio.c
>> @@ -0,0 +1,624 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/*
>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>> + *
>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/init.h>
>> +#include <linux/of_device.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/reset.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/slab.h>
>> +
>> +#include "meson-clkc-utils.h"
>> +#include "meson-audio-rstc.h"
>> +#include "meson-audio.h"
>> +#include "clk-regmap.h"
>> +#include "clk-phase.h"
>> +#include "sclk-div.h"
>> +#include "a1-audio.h"
>> +
>> +static const struct clk_parent_data a1_pclk_pdata[] = {
>> + { .fw_name = "pclk" },
>> +};
>
> Shouldn't you go through AUD2_CLKID_AUDIOTOP instead ?
>
>> +
>> +#define AUD_PCLK_GATE(_name, _reg, _bit) { \
>> + .data = &(struct clk_regmap_gate_data){ \
>> + .offset = (_reg), \
>> + .bit_idx = (_bit), \
>> + }, \
>> + .hw.init = &(struct clk_init_data) { \
>> + .name = "aud_"#_name, \
>> + .ops = &clk_regmap_gate_ops, \
>> + .parent_data = a1_pclk_pdata, \
>> + .num_parents = 1, \
>> + }, \
>> +}
>> +
>> +struct clk_regmap aud_ddr_arb =
>> + AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN0, 0);
>> +struct clk_regmap aud_tdmin_a =
>> + AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN0, 1);
>> +struct clk_regmap aud_tdmin_b =
>> + AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN0, 2);
>> +struct clk_regmap aud_tdmin_lb =
>> + AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN0, 3);
>> +struct clk_regmap aud_loopback =
>> + AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN0, 4);
>> +struct clk_regmap aud_tdmout_a =
>> + AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN0, 5);
>> +struct clk_regmap aud_tdmout_b =
>> + AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN0, 6);
>> +struct clk_regmap aud_frddr_a =
>> + AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN0, 7);
>> +struct clk_regmap aud_frddr_b =
>> + AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN0, 8);
>> +struct clk_regmap aud_toddr_a =
>> + AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN0, 9);
>> +struct clk_regmap aud_toddr_b =
>> + AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN0, 10);
>> +struct clk_regmap aud_spdifin =
>> + AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN0, 11);
>> +struct clk_regmap aud_resample =
>> + AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN0, 12);
>> +struct clk_regmap aud_eqdrc =
>> + AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN0, 13);
>> +struct clk_regmap aud_audiolocker =
>> + AUD_PCLK_GATE(audiolocker, AUDIO_CLK_GATE_EN0, 14);
>> +
>> +struct clk_regmap aud2_ddr_arb =
>> + AUD_PCLK_GATE(2_ddr_arb, AUDIO2_CLK_GATE_EN0, 0);
>> +struct clk_regmap aud2_pdm =
>> + AUD_PCLK_GATE(2_pdm, AUDIO2_CLK_GATE_EN0, 1);
>> +struct clk_regmap aud2_tdmin_vad =
>> + AUD_PCLK_GATE(2_tdmin_vad, AUDIO2_CLK_GATE_EN0, 2);
>> +struct clk_regmap aud2_toddr_vad =
>> + AUD_PCLK_GATE(2_toddr_vad, AUDIO2_CLK_GATE_EN0, 3);
>> +struct clk_regmap aud2_vad =
>> + AUD_PCLK_GATE(2_vad, AUDIO2_CLK_GATE_EN0, 4);
>> +struct clk_regmap aud2_audiotop =
>> + AUD_PCLK_GATE(2_audiotop, AUDIO2_CLK_GATE_EN0, 7);
>> +
>> +static const struct clk_parent_data a1_mst_pdata[] = {
>> + { .fw_name = "dds_in" },
>> + { .fw_name = "fclk_div2" },
>> + { .fw_name = "fclk_div3" },
>> + { .fw_name = "hifi_pll" },
>> + { .fw_name = "xtal" },
>> +};
>> +
>> +#define AUD_MST_MCLK_MUX(_name, _reg) \
>> + AUD_MUX(_name##_sel, _reg, 0x7, 24, CLK_MUX_ROUND_CLOSEST, \
>> + a1_mst_pdata, 0)
>> +#define AUD_MST_MCLK_DIV(_name, _reg) \
>> + AUD_DIV(_name##_div, _reg, 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \
>> + aud_##_name##_sel, CLK_SET_RATE_PARENT)
>> +#define AUD_MST_MCLK_GATE(_name, _reg) \
>> + AUD_GATE(_name, _reg, 31, aud_##_name##_div, \
>> + CLK_SET_RATE_PARENT)
>> +
>> +struct clk_regmap aud_mst_a_mclk_mux =
>> + AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
>> +struct clk_regmap aud_mst_a_mclk_div =
>> + AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
>> +struct clk_regmap aud_mst_a_mclk =
>> + AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
>> +
>> +struct clk_regmap aud_mst_b_mclk_mux =
>> + AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
>> +struct clk_regmap aud_mst_b_mclk_div =
>> + AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
>> +struct clk_regmap aud_mst_b_mclk =
>> + AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
>> +
>> +struct clk_regmap aud_mst_c_mclk_mux =
>> + AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
>> +struct clk_regmap aud_mst_c_mclk_div =
>> + AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
>> +struct clk_regmap aud_mst_c_mclk =
>> + AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
>> +
>> +struct clk_regmap aud_mst_d_mclk_mux =
>> + AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
>> +struct clk_regmap aud_mst_d_mclk_div =
>> + AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
>> +struct clk_regmap aud_mst_d_mclk =
>> + AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
>> +
>> +struct clk_regmap aud_spdifin_clk_mux =
>> + AUD_MST_MCLK_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
>> +struct clk_regmap aud_spdifin_clk_div =
>> + AUD_MST_MCLK_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
>> +struct clk_regmap aud_spdifin_clk =
>> + AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
>> +
>> +struct clk_regmap aud_eqdrc_clk_mux =
>> + AUD_MST_MCLK_MUX(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL);
>> +struct clk_regmap aud_eqdrc_clk_div =
>> + AUD_MST_MCLK_DIV(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL);
>> +struct clk_regmap aud_eqdrc_clk =
>> + AUD_MST_MCLK_GATE(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL);
>> +
>> +struct clk_regmap aud_resample_clk_mux =
>> + AUD_MUX(resample_clk_sel, AUDIO_CLK_RESAMPLE_CTRL, 0xf, 24,
>> + CLK_MUX_ROUND_CLOSEST, a1_mst_pdata, CLK_SET_RATE_PARENT);
>> +struct clk_regmap aud_resample_clk_div =
>> + AUD_DIV(resample_clk_div, AUDIO_CLK_RESAMPLE_CTRL, 0, 8,
>> + CLK_DIVIDER_ROUND_CLOSEST, resample_clk_sel, CLK_SET_RATE_PARENT);
>> +struct clk_regmap aud_resample_clk =
>> + AUD_GATE(resample_clk, AUDIO_CLK_RESAMPLE_CTRL, 31,
>> + resample_clk_div, CLK_SET_RATE_PARENT);
>> +
>> +struct clk_regmap aud_locker_in_clk_mux =
>> + AUD_MUX(locker_in_clk_sel, AUDIO_CLK_LOCKER_CTRL, 0xf, 8,
>> + CLK_MUX_ROUND_CLOSEST, a1_mst_pdata, CLK_SET_RATE_PARENT);
>> +struct clk_regmap aud_locker_in_clk_div =
>> + AUD_DIV(locker_in_clk_div, AUDIO_CLK_LOCKER_CTRL, 0, 8,
>> + CLK_DIVIDER_ROUND_CLOSEST, locker_in_clk_sel, CLK_SET_RATE_PARENT);
>> +struct clk_regmap aud_locker_in_clk =
>> + AUD_GATE(locker_in_clk, AUDIO_CLK_LOCKER_CTRL, 15,
>> + locker_in_clk_div, CLK_SET_RATE_PARENT);
>> +
>> +struct clk_regmap aud_locker_out_clk_mux =
>> + AUD_MUX(locker_out_clk_sel, AUDIO_CLK_LOCKER_CTRL, 0xf, 24,
>> + CLK_MUX_ROUND_CLOSEST, a1_mst_pdata, CLK_SET_RATE_PARENT);
>> +struct clk_regmap aud_locker_out_clk_div =
>> + AUD_DIV(locker_out_clk_div, AUDIO_CLK_LOCKER_CTRL, 16, 8,
>> + CLK_DIVIDER_ROUND_CLOSEST, locker_out_clk_sel, CLK_SET_RATE_PARENT);
>> +struct clk_regmap aud_locker_out_clk =
>> + AUD_GATE(locker_out_clk, AUDIO_CLK_LOCKER_CTRL, 31,
>> + locker_out_clk_div, CLK_SET_RATE_PARENT);
>> +
>> +struct clk_regmap aud2_vad_mclk_mux =
>> + AUD_MST_MCLK_MUX(2_vad_mclk, AUDIO2_MCLK_VAD_CTRL);
>> +struct clk_regmap aud2_vad_mclk_div =
>> + AUD_MST_MCLK_DIV(2_vad_mclk, AUDIO2_MCLK_VAD_CTRL);
>> +struct clk_regmap aud2_vad_mclk =
>> + AUD_MST_MCLK_GATE(2_vad_mclk, AUDIO2_MCLK_VAD_CTRL);
>> +
>> +struct clk_regmap aud2_vad_clk_mux =
>> + AUD_MST_MCLK_MUX(2_vad_clk, AUDIO2_CLK_VAD_CTRL);
>> +struct clk_regmap aud2_vad_clk_div =
>> + AUD_MST_MCLK_DIV(2_vad_clk, AUDIO2_CLK_VAD_CTRL);
>> +struct clk_regmap aud2_vad_clk =
>> + AUD_MST_MCLK_GATE(2_vad_clk, AUDIO2_CLK_VAD_CTRL);
>> +
>> +struct clk_regmap aud2_pdm_dclk_mux =
>> + AUD_MST_MCLK_MUX(2_pdm_dclk, AUDIO2_CLK_PDMIN_CTRL0);
>> +struct clk_regmap aud2_pdm_dclk_div =
>> + AUD_MST_MCLK_DIV(2_pdm_dclk, AUDIO2_CLK_PDMIN_CTRL0);
>> +struct clk_regmap aud2_pdm_dclk =
>> + AUD_MST_MCLK_GATE(2_pdm_dclk, AUDIO2_CLK_PDMIN_CTRL0);
>> +
>> +struct clk_regmap aud2_pdm_sysclk_mux =
>> + AUD_MST_MCLK_MUX(2_pdm_sysclk, AUDIO2_CLK_PDMIN_CTRL1);
>> +struct clk_regmap aud2_pdm_sysclk_div =
>> + AUD_MST_MCLK_DIV(2_pdm_sysclk, AUDIO2_CLK_PDMIN_CTRL1);
>> +struct clk_regmap aud2_pdm_sysclk =
>> + AUD_MST_MCLK_GATE(2_pdm_sysclk, AUDIO2_CLK_PDMIN_CTRL1);
>> +
>> +#define AUD_MST_SCLK_PRE_EN(_name, _reg, _pname) \
>> + AUD_GATE(_name##_pre_en, _reg, 31, \
>> + aud_##_pname, 0)
>> +#define AUD_MST_SCLK_DIV(_name, _reg) \
>> + AUD_SCLK_DIV(_name##_div, _reg, 20, 10, 0, 0, \
>> + aud_##_name##_pre_en, CLK_SET_RATE_PARENT)
>> +#define AUD_MST_SCLK_POST_EN(_name, _reg) \
>> + AUD_GATE(_name##_post_en, _reg, 30, \
>> + aud_##_name##_div, CLK_SET_RATE_PARENT)
>> +#define AUD_MST_SCLK(_name, _reg) \
>> + AUD_TRIPHASE(_name, _reg, 1, 0, 2, 4, \
>> + aud_##_name##_post_en, CLK_SET_RATE_PARENT)
>> +
>> +struct clk_regmap aud_mst_a_sclk_pre_en =
>> + AUD_MST_SCLK_PRE_EN(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0, mst_a_mclk);
>> +struct clk_regmap aud_mst_a_sclk_div =
>> + AUD_MST_SCLK_DIV(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0);
>> +struct clk_regmap aud_mst_a_sclk_post_en =
>> + AUD_MST_SCLK_POST_EN(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0);
>> +struct clk_regmap aud_mst_a_sclk =
>> + AUD_MST_SCLK(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL1);
>> +
>> +struct clk_regmap aud_mst_b_sclk_pre_en =
>> + AUD_MST_SCLK_PRE_EN(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0, mst_b_mclk);
>> +struct clk_regmap aud_mst_b_sclk_div =
>> + AUD_MST_SCLK_DIV(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0);
>> +struct clk_regmap aud_mst_b_sclk_post_en =
>> + AUD_MST_SCLK_POST_EN(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0);
>> +struct clk_regmap aud_mst_b_sclk =
>> + AUD_MST_SCLK(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL1);
>> +
>> +struct clk_regmap aud_mst_c_sclk_pre_en =
>> + AUD_MST_SCLK_PRE_EN(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0, mst_c_mclk);
>> +struct clk_regmap aud_mst_c_sclk_div =
>> + AUD_MST_SCLK_DIV(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0);
>> +struct clk_regmap aud_mst_c_sclk_post_en =
>> + AUD_MST_SCLK_POST_EN(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0);
>> +struct clk_regmap aud_mst_c_sclk =
>> + AUD_MST_SCLK(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL1);
>> +
>> +struct clk_regmap aud_mst_d_sclk_pre_en =
>> + AUD_MST_SCLK_PRE_EN(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0, mst_d_mclk);
>> +struct clk_regmap aud_mst_d_sclk_div =
>> + AUD_MST_SCLK_DIV(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0);
>> +struct clk_regmap aud_mst_d_sclk_post_en =
>> + AUD_MST_SCLK_POST_EN(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0);
>> +struct clk_regmap aud_mst_d_sclk =
>> + AUD_MST_SCLK(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL1);
>> +
>> +#define AUD_MST_LRCLK_DIV(_name, _reg, _pname) \
>> + AUD_SCLK_DIV(_name##_div, _reg, 0, 10, 10, 10, \
>> + aud_##_pname, 0)
>> +#define AUD_MST_LRCLK(_name, _reg) \
>> + AUD_TRIPHASE(_name, _reg, 1, 1, 3, 5, \
>> + aud_##_name##_div, CLK_SET_RATE_PARENT)
>> +
>> +struct clk_regmap aud_mst_a_lrclk_div =
>> + AUD_MST_LRCLK_DIV(mst_a_lrclk, AUDIO_MST_A_SCLK_CTRL0, mst_a_sclk_post_en);
>> +struct clk_regmap aud_mst_a_lrclk =
>> + AUD_MST_LRCLK(mst_a_lrclk, AUDIO_MST_A_SCLK_CTRL1);
>> +
>> +struct clk_regmap aud_mst_b_lrclk_div =
>> + AUD_MST_LRCLK_DIV(mst_b_lrclk, AUDIO_MST_B_SCLK_CTRL0, mst_b_sclk_post_en);
>> +struct clk_regmap aud_mst_b_lrclk =
>> + AUD_MST_LRCLK(mst_b_lrclk, AUDIO_MST_B_SCLK_CTRL1);
>> +
>> +struct clk_regmap aud_mst_c_lrclk_div =
>> + AUD_MST_LRCLK_DIV(mst_c_lrclk, AUDIO_MST_C_SCLK_CTRL0, mst_c_sclk_post_en);
>> +struct clk_regmap aud_mst_c_lrclk =
>> + AUD_MST_LRCLK(mst_c_lrclk, AUDIO_MST_C_SCLK_CTRL1);
>> +
>> +struct clk_regmap aud_mst_d_lrclk_div =
>> + AUD_MST_LRCLK_DIV(mst_d_lrclk, AUDIO_MST_D_SCLK_CTRL0, mst_d_sclk_post_en);
>> +struct clk_regmap aud_mst_d_lrclk =
>> + AUD_MST_LRCLK(mst_d_lrclk, AUDIO_MST_D_SCLK_CTRL1);
>> +
>> +static const struct clk_parent_data a1_mst_sclk_pdata[] = {
>> + { .hw = &aud_mst_a_sclk.hw, .index = -1 },
>> + { .hw = &aud_mst_b_sclk.hw, .index = -1 },
>> + { .hw = &aud_mst_c_sclk.hw, .index = -1 },
>> + { .hw = &aud_mst_d_sclk.hw, .index = -1 },
>> + { .fw_name = "slv_sclk0" },
>> + { .fw_name = "slv_sclk1" },
>> + { .fw_name = "slv_sclk2" },
>> + { .fw_name = "slv_sclk3" },
>> + { .fw_name = "slv_sclk4" },
>> + { .fw_name = "slv_sclk5" },
>> + { .fw_name = "slv_sclk6" },
>> + { .fw_name = "slv_sclk7" },
>> + { .fw_name = "slv_sclk8" },
>> + { .fw_name = "slv_sclk9" },
>> +};
>> +
>> +static const struct clk_parent_data a1_mst_lrclk_pdata[] = {
>> + { .hw = &aud_mst_a_lrclk.hw, .index = -1 },
>> + { .hw = &aud_mst_b_lrclk.hw, .index = -1 },
>> + { .hw = &aud_mst_c_lrclk.hw, .index = -1 },
>> + { .hw = &aud_mst_d_lrclk.hw, .index = -1 },
>> + { .fw_name = "slv_lrclk0" },
>> + { .fw_name = "slv_lrclk1" },
>> + { .fw_name = "slv_lrclk2" },
>> + { .fw_name = "slv_lrclk3" },
>> + { .fw_name = "slv_lrclk4" },
>> + { .fw_name = "slv_lrclk5" },
>> + { .fw_name = "slv_lrclk6" },
>> + { .fw_name = "slv_lrclk7" },
>> + { .fw_name = "slv_lrclk8" },
>> + { .fw_name = "slv_lrclk9" },
>> +};
>> +
>> +#define AUD_TDM_SCLK_MUX(_name, _reg) \
>> + AUD_MUX(_name##_sel, _reg, 0xf, 24, \
>> + CLK_MUX_ROUND_CLOSEST, a1_mst_sclk_pdata, 0)
>> +#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
>> + AUD_GATE(_name##_pre_en, _reg, 31, \
>> + aud_##_name##_sel, CLK_SET_RATE_PARENT)
>> +#define AUD_TDM_SCLK_POST_EN(_name, _reg) \
>> + AUD_GATE(_name##_post_en, _reg, 30, \
>> + aud_##_name##_pre_en, CLK_SET_RATE_PARENT)
>> +#define AUD_TDM_SCLK_WS(_name, _reg) \
>> + AUD_SCLK_WS(_name, _reg, 1, 29, 28, \
>> + aud_##_name##_post_en, \
>> + CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
>> +
>> +#define AUD_TDM_LRLCK(_name, _reg) \
>> + AUD_MUX(_name, _reg, 0xf, 20, \
>> + CLK_MUX_ROUND_CLOSEST, a1_mst_lrclk_pdata, \
>> + CLK_SET_RATE_PARENT)
>> +
>> +struct clk_regmap aud_tdmin_a_sclk_mux =
>> + AUD_TDM_SCLK_MUX(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL);
>> +struct clk_regmap aud_tdmin_a_sclk_pre_en =
>> + AUD_TDM_SCLK_PRE_EN(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL);
>> +struct clk_regmap aud_tdmin_a_sclk_post_en =
>> + AUD_TDM_SCLK_POST_EN(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL);
>> +struct clk_regmap aud_tdmin_a_sclk =
>> + AUD_TDM_SCLK_WS(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL);
>> +struct clk_regmap aud_tdmin_a_lrclk =
>> + AUD_TDM_LRLCK(tdmin_a_lrclk, AUDIO_CLK_TDMIN_A_CTRL);
>> +
>> +struct clk_regmap aud_tdmin_b_sclk_mux =
>> + AUD_TDM_SCLK_MUX(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL);
>> +struct clk_regmap aud_tdmin_b_sclk_pre_en =
>> + AUD_TDM_SCLK_PRE_EN(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL);
>> +struct clk_regmap aud_tdmin_b_sclk_post_en =
>> + AUD_TDM_SCLK_POST_EN(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL);
>> +struct clk_regmap aud_tdmin_b_sclk =
>> + AUD_TDM_SCLK_WS(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL);
>> +struct clk_regmap aud_tdmin_b_lrclk =
>> + AUD_TDM_LRLCK(tdmin_b_lrclk, AUDIO_CLK_TDMIN_B_CTRL);
>> +
>> +struct clk_regmap aud_tdmin_lb_sclk_mux =
>> + AUD_TDM_SCLK_MUX(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL);
>> +struct clk_regmap aud_tdmin_lb_sclk_pre_en =
>> + AUD_TDM_SCLK_PRE_EN(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL);
>> +struct clk_regmap aud_tdmin_lb_sclk_post_en =
>> + AUD_TDM_SCLK_POST_EN(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL);
>> +struct clk_regmap aud_tdmin_lb_sclk =
>> + AUD_TDM_SCLK_WS(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL);
>> +struct clk_regmap aud_tdmin_lb_lrclk =
>> + AUD_TDM_LRLCK(tdmin_lb_lrclk, AUDIO_CLK_TDMIN_LB_CTRL);
>> +
>> +struct clk_regmap aud_tdmout_a_sclk_mux =
>> + AUD_TDM_SCLK_MUX(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL);
>> +struct clk_regmap aud_tdmout_a_sclk_pre_en =
>> + AUD_TDM_SCLK_PRE_EN(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL);
>> +struct clk_regmap aud_tdmout_a_sclk_post_en =
>> + AUD_TDM_SCLK_POST_EN(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL);
>> +struct clk_regmap aud_tdmout_a_sclk =
>> + AUD_TDM_SCLK_WS(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL);
>> +struct clk_regmap aud_tdmout_a_lrclk =
>> + AUD_TDM_LRLCK(tdmout_a_lrclk, AUDIO_CLK_TDMOUT_A_CTRL);
>> +
>> +struct clk_regmap aud_tdmout_b_sclk_mux =
>> + AUD_TDM_SCLK_MUX(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL);
>> +struct clk_regmap aud_tdmout_b_sclk_pre_en =
>> + AUD_TDM_SCLK_PRE_EN(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL);
>> +struct clk_regmap aud_tdmout_b_sclk_post_en =
>> + AUD_TDM_SCLK_POST_EN(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL);
>> +struct clk_regmap aud_tdmout_b_sclk =
>> + AUD_TDM_SCLK_WS(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL);
>> +struct clk_regmap aud_tdmout_b_lrclk =
>> + AUD_TDM_LRLCK(tdmout_b_lrclk, AUDIO_CLK_TDMOUT_B_CTRL);
>> +
>> +static struct clk_hw *a1_audio_hw_clks[] = {
>> + [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw,
>> + [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw,
>> + [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw,
>> + [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw,
>> + [AUD_CLKID_LOOPBACK] = &aud_loopback.hw,
>> + [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw,
>> + [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw,
>> + [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw,
>> + [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw,
>> + [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw,
>> + [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw,
>> + [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw,
>> + [AUD_CLKID_RESAMPLE] = &aud_resample.hw,
>> + [AUD_CLKID_EQDRC] = &aud_eqdrc.hw,
>> + [AUD_CLKID_LOCKER] = &aud_audiolocker.hw,
>> + [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_mux.hw,
>> + [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw,
>> + [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw,
>> + [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_mux.hw,
>> + [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw,
>> + [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw,
>> + [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_mux.hw,
>> + [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw,
>> + [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw,
>> + [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_mux.hw,
>> + [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw,
>> + [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw,
>> + [AUD_CLKID_RESAMPLE_CLK_SEL] = &aud_resample_clk_mux.hw,
>> + [AUD_CLKID_RESAMPLE_CLK_DIV] = &aud_resample_clk_div.hw,
>> + [AUD_CLKID_RESAMPLE_CLK] = &aud_resample_clk.hw,
>> + [AUD_CLKID_LOCKER_IN_CLK_SEL] = &aud_locker_in_clk_mux.hw,
>> + [AUD_CLKID_LOCKER_IN_CLK_DIV] = &aud_locker_in_clk_div.hw,
>> + [AUD_CLKID_LOCKER_IN_CLK] = &aud_locker_in_clk.hw,
>> + [AUD_CLKID_LOCKER_OUT_CLK_SEL] = &aud_locker_out_clk_mux.hw,
>> + [AUD_CLKID_LOCKER_OUT_CLK_DIV] = &aud_locker_out_clk_div.hw,
>> + [AUD_CLKID_LOCKER_OUT_CLK] = &aud_locker_out_clk.hw,
>> + [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_mux.hw,
>> + [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw,
>> + [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw,
>> + [AUD_CLKID_EQDRC_CLK_SEL] = &aud_eqdrc_clk_mux.hw,
>> + [AUD_CLKID_EQDRC_CLK_DIV] = &aud_eqdrc_clk_div.hw,
>> + [AUD_CLKID_EQDRC_CLK] = &aud_eqdrc_clk.hw,
>> + [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw,
>> + [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw,
>> + [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw,
>> + [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw,
>> + [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw,
>> + [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw,
>> + [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw,
>> + [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw,
>> + [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw,
>> + [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw,
>> + [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw,
>> + [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw,
>> + [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw,
>> + [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw,
>> + [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw,
>> + [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw,
>> + [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw,
>> + [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw,
>> + [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw,
>> + [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw,
>> + [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw,
>> + [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw,
>> + [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw,
>> + [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw,
>> + [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_mux.hw,
>> + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
>> + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
>> + [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw,
>> + [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw,
>> + [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_mux.hw,
>> + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
>> + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
>> + [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw,
>> + [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw,
>> + [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_mux.hw,
>> + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
>> + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
>> + [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw,
>> + [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw,
>> + [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_mux.hw,
>> + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
>> + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
>> + [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw,
>> + [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw,
>> + [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_mux.hw,
>> + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
>> + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
>> + [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw,
>> + [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw,
>> +};
>> +
>> +static struct clk_hw *a1_audio2_hw_clks[] = {
>> + [AUD2_CLKID_DDR_ARB] = &aud2_ddr_arb.hw,
>> + [AUD2_CLKID_PDM] = &aud2_pdm.hw,
>> + [AUD2_CLKID_TDMIN_VAD] = &aud2_tdmin_vad.hw,
>> + [AUD2_CLKID_TODDR_VAD] = &aud2_toddr_vad.hw,
>> + [AUD2_CLKID_VAD] = &aud2_vad.hw,
>> + [AUD2_CLKID_AUDIOTOP] = &aud2_audiotop.hw,
>> + [AUD2_CLKID_VAD_MCLK_SEL] = &aud2_vad_mclk_mux.hw,
>> + [AUD2_CLKID_VAD_MCLK_DIV] = &aud2_vad_mclk_div.hw,
>> + [AUD2_CLKID_VAD_MCLK] = &aud2_vad_mclk.hw,
>> + [AUD2_CLKID_VAD_CLK_SEL] = &aud2_vad_clk_mux.hw,
>> + [AUD2_CLKID_VAD_CLK_DIV] = &aud2_vad_clk_div.hw,
>> + [AUD2_CLKID_VAD_CLK] = &aud2_vad_clk.hw,
>> + [AUD2_CLKID_PDM_DCLK_SEL] = &aud2_pdm_dclk_mux.hw,
>> + [AUD2_CLKID_PDM_DCLK_DIV] = &aud2_pdm_dclk_div.hw,
>> + [AUD2_CLKID_PDM_DCLK] = &aud2_pdm_dclk.hw,
>> + [AUD2_CLKID_PDM_SYSCLK_SEL] = &aud2_pdm_sysclk_mux.hw,
>> + [AUD2_CLKID_PDM_SYSCLK_DIV] = &aud2_pdm_sysclk_div.hw,
>> + [AUD2_CLKID_PDM_SYSCLK] = &aud2_pdm_sysclk.hw,
>> +};
>
> I think you already got that comment but audio2 is a terrible name.
>> Given that the 2nd controller is mostly about VAD (PDM is there only to
> feed it) and that it is just a name, I'd prefer something like a1_audio_vad.
>
Do you mean something like this?
static struct clk_hw *a1_audio_vad_hw_clks[] = {
[AUD_CLKID_VAD_DDR_ARB] = &aud_vad_ddr_arb.hw,
[AUD_CLKID_VAD_PDM] = &aud_vad_pdm.hw,
[AUD_CLKID_VAD_TDMIN] = &aud_vad_tdmin.hw,
[AUD_CLKID_VAD_TODDR] = &aud_vad_toddr.hw,
[AUD_CLKID_VAD] = &aud_vad.hw,
...
>> +
>> +static int a1_register_clk(struct platform_device *pdev, struct regmap *map,
>> + struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = container_of(hw, struct clk_regmap, hw);
>> +
>> + if (!hw)
>> + return 0;
>> +
>> + clk->map = map;
>> +
>> + return devm_clk_hw_register(&pdev->dev, hw);
>> +}
>
> Why do you have to do that and cannot do it like the rest of the
> modules ?
>
Originally, it was used twice. But you're right, now it can be placed
into the loop in a1_audio_clkc_probe().
>> +
>> +struct a1_audio_data {
>> + struct meson_clk_hw_data hw_clks;
>> + int core_clkid;
>> + const char *core_fwname;
>> + unsigned int reset_offset;
>> + unsigned int reset_num;
>> +};
>> +
>> +static const struct regmap_config a1_audio_regmap_cfg = {
>> + .reg_bits = 32,
>> + .val_bits = 32,
>> + .reg_stride = 4,
>> +};
>> +
>> +static int a1_audio_clkc_probe(struct platform_device *pdev)
>> +{
>> + const struct a1_audio_data *data;
>> + struct regmap *map;
>> + void __iomem *base;
>> + struct clk *clk;
>> + unsigned int i;
>> + int ret;
>> +
>> + data = of_device_get_match_data(&pdev->dev);
>> + if (!data)
>> + return -EINVAL;
>> +
>> + if (data->core_fwname) {
>
> That is really over-complicated for what it does ....
>
>> + clk = devm_clk_get_enabled(&pdev->dev, data->core_fwname);
>
> It does not make a lot of sense that one of the 2 controllers as 2nd
> pclk.
> > You should consider using the AUD2_CLKID_AUDIOTOP as a parent of audio
> gates instead. You would not have to that.
>
>> + if (IS_ERR(clk))
>> + return PTR_ERR(clk);
>> + }
>
>
>
>> +
>> + base = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + map = devm_regmap_init_mmio(&pdev->dev, base, &a1_audio_regmap_cfg);
>> + if (IS_ERR(map))
>> + return PTR_ERR(map);
>> +
>> + clk = devm_clk_get_enabled(&pdev->dev, "pclk");
>> + if (IS_ERR(clk))
>> + return PTR_ERR(clk);
>> +
>> + for (i = 0; i < data->hw_clks.num; i++) {
>> + struct clk_hw *hw = data->hw_clks.hws[i];
>> +
>> + ret = a1_register_clk(pdev, map, hw);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + ret = devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get,
>> + (void *)&data->hw_clks);
>> + if (ret)
>> + return ret;
>> +
>> + if (!data->reset_num)
>> + return 0;
>> +
>> + return meson_audio_rstc_register(&pdev->dev, map, data->reset_offset,
>> + data->reset_num);
>> +}>
> Again this is over-complicated.> Just make an external function for the register, use it for axg, a1,
> a1-vad, then make one file for each controller. That will keep the code
> clean and readable.
>
It's a bit unclear here. Is this a general recommendation or is it
specific to _this_ location in the code?
> Just make an external function for the register
Dou you suggest to share something like a1_register_clk()? Currently, it
is not good idea, axg-audio uses slightly different way to register
their clocks.
> keep it simple please.
>
>> +
>> +struct a1_audio_data a1_audio_data = {
>> + .hw_clks = {
>> + .hws = a1_audio_hw_clks,
>> + .num = ARRAY_SIZE(a1_audio_hw_clks),
>> + },
>> + .core_fwname = "core",
>> + .reset_offset = AUDIO_SW_RESET0,
>> + .reset_num = 32,
>> +};
>> +
>> +struct a1_audio_data a1_audio2_data = {
>> + .hw_clks = {
>> + .hws = a1_audio2_hw_clks,
>> + .num = ARRAY_SIZE(a1_audio2_hw_clks),
>> + },
>> +};
>> +
>> +static const struct of_device_id a1_audio_clkc_match_table[] = {
>> + {
>> + .compatible = "amlogic,a1-audio-clkc",
>> + .data = &a1_audio_data,
>> + },
>> + {
>> + .compatible = "amlogic,a1-audio2-clkc",
>> + .data = &a1_audio2_data,
>> + },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, a1_audio_clkc_match_table);
>> +
>> +static struct platform_driver a1_audio_clkc_driver = {
>> + .probe = a1_audio_clkc_probe,
>> + .driver = {
>> + .name = "a1-audio-clkc",
>> + .of_match_table = a1_audio_clkc_match_table,
>> + },
>> +};
>> +module_platform_driver(a1_audio_clkc_driver);
>> +
>> +MODULE_DESCRIPTION("Amlogic A1 Audio Clock driver");
>> +MODULE_AUTHOR("Jan Dakinevich <jan.dakinevich@salutedevices.com>");
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/clk/meson/a1-audio.h b/drivers/clk/meson/a1-audio.h
>> new file mode 100644
>> index 000000000000..9ea9da21ff9b
>> --- /dev/null
>> +++ b/drivers/clk/meson/a1-audio.h
>> @@ -0,0 +1,45 @@
>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>> +/*
>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>> + *
>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> + */
>> +
>> +#ifndef __A1_AUDIO_H
>> +#define __A1_AUDIO_H
>> +
>> +#define AUDIO_CLK_GATE_EN0 0x000
>> +#define AUDIO_MCLK_A_CTRL 0x008
>> +#define AUDIO_MCLK_B_CTRL 0x00c
>> +#define AUDIO_MCLK_C_CTRL 0x010
>> +#define AUDIO_MCLK_D_CTRL 0x014
>> +#define AUDIO_MCLK_E_CTRL 0x018
>> +#define AUDIO_MCLK_F_CTRL 0x01c
>> +#define AUDIO_SW_RESET0 0x028
>> +#define AUDIO_MST_A_SCLK_CTRL0 0x040
>> +#define AUDIO_MST_A_SCLK_CTRL1 0x044
>> +#define AUDIO_MST_B_SCLK_CTRL0 0x048
>> +#define AUDIO_MST_B_SCLK_CTRL1 0x04c
>> +#define AUDIO_MST_C_SCLK_CTRL0 0x050
>> +#define AUDIO_MST_C_SCLK_CTRL1 0x054
>> +#define AUDIO_MST_D_SCLK_CTRL0 0x058
>> +#define AUDIO_MST_D_SCLK_CTRL1 0x05c
>> +#define AUDIO_CLK_TDMIN_A_CTRL 0x080
>> +#define AUDIO_CLK_TDMIN_B_CTRL 0x084
>> +#define AUDIO_CLK_TDMIN_LB_CTRL 0x08c
>> +#define AUDIO_CLK_TDMOUT_A_CTRL 0x090
>> +#define AUDIO_CLK_TDMOUT_B_CTRL 0x094
>> +#define AUDIO_CLK_SPDIFIN_CTRL 0x09c
>> +#define AUDIO_CLK_RESAMPLE_CTRL 0x0a4
>> +#define AUDIO_CLK_LOCKER_CTRL 0x0a8
>> +#define AUDIO_CLK_EQDRC_CTRL 0x0c0
>> +
>> +#define AUDIO2_CLK_GATE_EN0 0x00c
>> +#define AUDIO2_MCLK_VAD_CTRL 0x040
>> +#define AUDIO2_CLK_VAD_CTRL 0x044
>> +#define AUDIO2_CLK_PDMIN_CTRL0 0x058
>> +#define AUDIO2_CLK_PDMIN_CTRL1 0x05c
>
> Same remark - header is useless.
>
Do you suggest to move these defines to source file and kill this header?
>> +
>> +#include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
>> +
>> +#endif /* __A1_AUDIO_H */
>
>
--
Best regards
Jan Dakinevich
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 2/2] mailbox: arm_mhuv3: Add driver
From: Jassi Brar @ 2024-04-08 1:14 UTC (permalink / raw)
To: Cristian Marussi
Cc: linux-kernel, linux-arm-kernel, devicetree, sudeep.holla, robh+dt,
krzysztof.kozlowski+dt, conor+dt
In-Reply-To: <20240404062347.3219795-3-cristian.marussi@arm.com>
On Thu, Apr 4, 2024 at 1:25 AM Cristian Marussi
<cristian.marussi@arm.com> wrote:
>
> Add support for ARM MHUv3 mailbox controller.
>
> Support is limited to the MHUv3 Doorbell extension using only the PBX/MBX
> combined interrupts.
>
> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
> ---
> v1 -> v2
> - fixed checkpatch warnings about side-effects
> - fixed sparse errors as reported
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202403290015.tCLXudqC-lkp@intel.com/
> ---
> MAINTAINERS | 9 +
> drivers/mailbox/Kconfig | 11 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/arm_mhuv3.c | 1063 +++++++++++++++++++++++++++++++++++
> 4 files changed, 1085 insertions(+)
> create mode 100644 drivers/mailbox/arm_mhuv3.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index aa3b947fb080..e957b9d9e32a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -12998,6 +12998,15 @@ F: Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
> F: drivers/mailbox/arm_mhuv2.c
> F: include/linux/mailbox/arm_mhuv2_message.h
>
> +MAILBOX ARM MHUv3
> +M: Sudeep Holla <sudeep.holla@arm.com>
> +M: Cristian Marussi <cristian.marussi@arm.com>
> +L: linux-kernel@vger.kernel.org
> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S: Maintained
> +F: Documentation/devicetree/bindings/mailbox/arm,mhuv3.yaml
> +F: drivers/mailbox/arm_mhuv3.c
> +
> MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7
> M: Alejandro Colomar <alx@kernel.org>
> L: linux-man@vger.kernel.org
> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
> index 42940108a187..d20cdae65cfe 100644
> --- a/drivers/mailbox/Kconfig
> +++ b/drivers/mailbox/Kconfig
> @@ -23,6 +23,17 @@ config ARM_MHU_V2
> Say Y here if you want to build the ARM MHUv2 controller driver,
> which provides unidirectional mailboxes between processing elements.
>
> +config ARM_MHU_V3
> + tristate "ARM MHUv3 Mailbox"
> + depends on ARM64 || COMPILE_TEST
> + help
> + Say Y here if you want to build the ARM MHUv3 controller driver,
> + which provides unidirectional mailboxes between processing elements.
> +
> + ARM MHUv3 controllers can implement a varying number of extensions
> + that provides different means of transports: supported extensions
> + will be discovered and possibly managed at probe-time.
> +
> config IMX_MBOX
> tristate "i.MX Mailbox"
> depends on ARCH_MXC || COMPILE_TEST
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
> index 18793e6caa2f..5cf2f54debaf 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -9,6 +9,8 @@ obj-$(CONFIG_ARM_MHU) += arm_mhu.o arm_mhu_db.o
>
> obj-$(CONFIG_ARM_MHU_V2) += arm_mhuv2.o
>
> +obj-$(CONFIG_ARM_MHU_V3) += arm_mhuv3.o
> +
> obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
>
> obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o
> diff --git a/drivers/mailbox/arm_mhuv3.c b/drivers/mailbox/arm_mhuv3.c
> new file mode 100644
> index 000000000000..e4125568bec0
> --- /dev/null
> +++ b/drivers/mailbox/arm_mhuv3.c
> @@ -0,0 +1,1063 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * ARM Message Handling Unit Version 3 (MHUv3) driver.
> + *
> + * Copyright (C) 2024 ARM Ltd.
> + *
> + * Based on ARM MHUv2 driver.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/interrupt.h>
> +#include <linux/mailbox_controller.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +/* ====== MHUv3 Registers ====== */
> +
> +/* Maximum number of Doorbell channel windows */
> +#define MHUV3_DBCW_MAX 128
> +/* Number of DBCH combined interrupt status registers */
> +#define MHUV3_DBCH_CMB_INT_ST_REG_CNT 4
> +#define MHUV3_INVALID_DOORBELL 0xFFFFFFFFUL
> +
> +/* Number of FFCH combined interrupt status registers */
> +#define MHUV3_FFCH_CMB_INT_ST_REG_CNT 2
> +
> +#define MHUV3_STAT_BYTES (sizeof(u32))
>
Simply 4 please.
> +#define MHUV3_STAT_BITS (MHUV3_STAT_BYTES * __CHAR_BIT__)
>
just 32.
> +
> +/* Not a typo ... */
> +#define MHUV3_MAJOR_VERSION 2
> +
> +enum {
> + MHUV3_MBOX_CELL_TYPE,
> + MHUV3_MBOX_CELL_CHWN,
> + MHUV3_MBOX_CELL_PARAM,
> + MHUV3_MBOX_CELLS
> +};
> +
> +/* CTRL_Page */
> +
> +struct blk_id {
> + u32 blk_id : 4;
Please avoid name clashes.
> + u32 pad : 28;
> +} __packed;
> +
> +struct feat_spt0 {
> + u32 dbe_spt : 4;
> + u32 fe_spt : 4;
> + u32 fce_spt : 4;
> + u32 tze_spt : 4;
> + u32 rme_spt : 4;
> + u32 rase_spt : 4;
> + u32 pad: 8;
> +} __packed;
> +
> +struct feat_spt1 {
> + u32 auto_op_spt : 4;
> + u32 pad: 28;
> +} __packed;
> +
> +struct dbch_cfg0 {
> + u32 num_dbch : 8;
> + u32 pad: 24;
> +} __packed;
> +
> +struct ffch_cfg0 {
> + u32 num_ffch : 8;
> + u32 x8ba_spt : 1;
> + u32 x16ba_spt : 1;
> + u32 x32ba_spt : 1;
> + u32 x64ba_spt : 1;
> + u32 pad : 4;
> + u32 ffch_depth : 10;
> + u32 pad2 : 6;
> +} __packed;
> +
> +struct fch_cfg0 {
> + u32 num_fch : 10;
> + /* MBX only registers */
> + u32 fcgi_spt : 1;
> + /* ------------------ */
> + u32 num_fcg : 5;
> + u32 num_fch_per_grp : 5;
> + u32 fch_ws : 8;
> + u32 pad : 3;
> +} __packed;
> +
> +struct ctrl {
> + u32 op_req : 1;
> + u32 ch_op_mask : 1;
> + u32 pad : 30;
> +} __packed;
> +
> +struct fch_ctrl {
> + u32 pad : 2;
> + u32 int_en : 1;
> + u32 pad2 : 29;
> +} __packed;
> +
> +struct iidr {
> + u32 implementer : 12;
> + u32 revision : 4;
> + u32 variant : 4;
> + u32 product_id : 12;
> +} __packed;
> +
> +struct aidr {
> + u32 arch_minor_rev : 4;
> + u32 arch_major_rev : 4;
> + u32 pad : 24;
> +} __packed;
> +
I am not sure about using bitfields on register values. I know v2
driver also uses bitfields but this still is not very portable and is
dependent on compiler behaviour. We may actually save some loc by not
having unused fields if we use shifts and masks. Though I don't
strongly feel either way.
> +struct ctrl_page {
> + struct blk_id blk_id;
> + u8 pad[0x10 - 0x4];
> + struct feat_spt0 feat_spt0;
> + struct feat_spt1 feat_spt1;
> + u8 pad1[0x20 - 0x18];
> + struct dbch_cfg0 dbch_cfg0;
> + u8 pad2[0x30 - 0x24];
> + struct ffch_cfg0 ffch_cfg0;
> + u8 pad3[0x40 - 0x34];
> + struct fch_cfg0 fch_cfg0;
> + u8 pad4[0x100 - 0x44];
> + struct ctrl ctrl;
> + /* MBX only registers */
> + u8 pad5[0x140 - 0x104];
> + struct fch_ctrl fch_ctrl;
> + u32 fcg_int_en;
> + u8 pad6[0x400 - 0x148];
> + /* ------------------ */
Why the decoration ? Maybe comment on what different starts from here.
> + u32 dbch_int_st[MHUV3_DBCH_CMB_INT_ST_REG_CNT];
> + u32 ffch_int_st[MHUV3_FFCH_CMB_INT_ST_REG_CNT];
> + /* MBX only registers */
> + u8 pad7[0x470 - 0x418];
> + u32 fcg_int_st;
> + u8 pad8[0x480 - 0x474];
> + u32 fcg_grp_int_st[32];
> + u8 pad9[0xFC8 - 0x500];
> + /* ------------------ */
> + struct iidr iidr;
> + struct aidr aidr;
> + u32 imp_def_id[12];
> +} __packed;
> +
> +/* DBCW_Page */
> +
> +struct xbcw_ctrl {
> + u32 comb_en : 1;
> + u32 pad : 31;
> +} __packed;
> +
> +struct pdbcw_int {
> + u32 tfr_ack : 1;
> + u32 pad : 31;
> +} __packed;
> +
> +struct pdbcw_page {
> + u32 st;
> + u8 pad[0xC - 0x4];
> + u32 set;
> + struct pdbcw_int int_st;
> + struct pdbcw_int int_clr;
> + struct pdbcw_int int_en;
> + struct xbcw_ctrl ctrl;
> +} __packed;
> +
> +struct mdbcw_page {
> + u32 st;
> + u32 st_msk;
> + u32 clr;
> + u8 pad[0x10 - 0xC];
> + u32 msk_st;
> + u32 msk_set;
> + u32 msk_clr;
> + struct xbcw_ctrl ctrl;
> +} __packed;
> +
> +struct dummy_page {
> + u8 pad[0x1000];
> +} __packed;
> +
> +struct mhu3_pbx_frame_reg {
> + struct ctrl_page ctrl;
> + struct pdbcw_page dbcw[MHUV3_DBCW_MAX];
> + struct dummy_page ffcw;
> + struct dummy_page fcw;
> + u8 pad[0xF000 - 0x4000];
> + struct dummy_page impdef;
> +} __packed;
> +
> +struct mhu3_mbx_frame_reg {
> + struct ctrl_page ctrl;
> + struct mdbcw_page dbcw[MHUV3_DBCW_MAX];
> + struct dummy_page ffcw;
> + struct dummy_page fcw;
> + u8 pad[0xF000 - 0x4000];
> + struct dummy_page impdef;
> +} __packed;
> +
> +/* Macro for reading a bitfield within a physically mapped packed struct */
> +#define readl_relaxed_bitfield(_regptr, _field) \
> + ({ \
> + u32 _rval; \
> + typeof(_regptr) _rptr = _regptr; \
> + _rval = readl_relaxed(_rptr); \
> + ((typeof(*_rptr) __force *)(&_rval))->_field; \
> + })
> +
> +/* Macro for writing a bitfield within a physically mapped packed struct */
> +#define writel_relaxed_bitfield(_value, _regptr, _field) \
> + ({ \
> + u32 _rval; \
> + typeof(_regptr) _rptr = _regptr; \
> + _rval = readl_relaxed(_rptr); \
> + ((typeof(*_rptr) __force *)(&_rval))->_field = _value; \
> + writel_relaxed(_rval, _rptr); \
> + })
> +
> +/* ====== MHUv3 data structures ====== */
> +
> +enum mhuv3_frame {
> + PBX_FRAME,
> + MBX_FRAME
> +};
> +
> +static char *mhuv3_str[] = {
> + "PBX",
> + "MBX"
> +};
> +
> +enum mhuv3_extension_type {
> + FIRST_EXT = 0,
> + DBE_EXT = FIRST_EXT,
> + FCE_EXT,
> + FE_EXT,
> + MAX_EXT
> +};
> +
> +struct mhuv3;
> +
> +/**
> + * struct mhuv3_protocol_ops - MHUv3 operations
> + *
> + * @rx_startup: Receiver startup callback.
> + * @rx_shutdown: Receiver shutdown callback.
> + * @read_data: Read available Sender in-band LE data (if any).
> + * @rx_complete: Acknowledge data reception to the Sender. Any out-of-band data
> + * has to have been already retrieved before calling this.
> + * @tx_startup: Sender startup callback.
> + * @tx_shutdown: Sender shutdown callback.
> + * @last_tx_done: Report back to the Sender if the last transfer has completed.
> + * @send_data: Send data to the receiver.
> + *
> + * Each supported transport protocol provides its own implementation of
> + * these operations.
> + */
> +struct mhuv3_protocol_ops {
> + int (*rx_startup)(struct mhuv3 *mhu, struct mbox_chan *chan);
> + void (*rx_shutdown)(struct mhuv3 *mhu, struct mbox_chan *chan);
> + void *(*read_data)(struct mhuv3 *mhu, struct mbox_chan *chan);
> + void (*rx_complete)(struct mhuv3 *mhu, struct mbox_chan *chan);
> + void (*tx_startup)(struct mhuv3 *mhu, struct mbox_chan *chan);
> + void (*tx_shutdown)(struct mhuv3 *mhu, struct mbox_chan *chan);
> + int (*last_tx_done)(struct mhuv3 *mhu, struct mbox_chan *chan);
> + int (*send_data)(struct mhuv3 *mhu, struct mbox_chan *chan, void *arg);
> +};
> +
> +/**
> + * struct mhuv3_mbox_chan_priv - MHUv3 channel private information
> + *
> + * @ch_idx: Channel window index associated to this mailbox channel.
> + * @doorbell: Doorbell bit number within the @ch_idx window.
> + * Only relevant to Doorbell transport.
> + * @ops: Transport protocol specific operations for this channel.
> + *
> + * Transport specific data attached to mmailbox channel priv data.
> + */
> +struct mhuv3_mbox_chan_priv {
> + u32 ch_idx;
> + u32 doorbell;
> + const struct mhuv3_protocol_ops *ops;
> +};
> +
> +/**
> + * struct mhuv3_extension - MHUv3 extension descriptor
> + *
> + * @type: Type of extension
> + * @max_chans: Max number of channels found for this extension.
> + * @base_ch_idx: First channel number assigned to this extension, picked from
> + * the set of all mailbox channels descriptors created.
> + * @mbox_of_xlate: Extension specific helper to parse DT and lookup associated
> + * channel from the related 'mboxes' property.
> + * @combined_irq_setup: Extension specific helper to setup the combined irq.
> + * @channels_init: Extension specific helper to initialize channels.
> + * @chan_from_comb_irq_get: Extension specific helper to lookup which channel
> + * triggered the combined irq.
> + * @pending_db: Array of per-channel pending doorbells.
> + * @pending_lock: Protect access to pending_db.
> + */
> +struct mhuv3_extension {
> + enum mhuv3_extension_type type;
> + unsigned int max_chans;
> + unsigned int base_ch_idx;
> + struct mbox_chan *(*mbox_of_xlate)(struct mhuv3 *mhu,
> + unsigned int channel,
> + unsigned int param);
> + void (*combined_irq_setup)(struct mhuv3 *mhu);
> + int (*channels_init)(struct mhuv3 *mhu);
> + struct mbox_chan *(*chan_from_comb_irq_get)(struct mhuv3 *mhu);
> + u32 pending_db[MHUV3_DBCW_MAX];
> + /* Protect access to pending_db */
> + spinlock_t pending_lock;
> +};
> +
> +/**
> + * struct mhuv3 - MHUv3 mailbox controller data
> + *
> + * @frame: Frame type: MBX_FRAME or PBX_FRAME.
> + * @auto_op_full: Flag to indicate if the MHU supports AutoOp full mode.
> + * @major: MHUv3 controller architectural major version.
> + * @minor: MHUv3 controller architectural minor version.
> + * @tot_chans: The total number of channnels discovered across all extensions.
> + * @cmb_irq: Combined IRQ number if any found defined.
> + * @ctrl: A reference to the MHUv3 control page for this block.
> + * @pbx: Base address of the PBX register mapping region.
> + * @mbx: Base address of the MBX register mapping region.
> + * @ext: Array holding descriptors for any found implemented extension.
> + * @mbox: Mailbox controller belonging to the MHU frame.
> + */
> +struct mhuv3 {
> + enum mhuv3_frame frame;
> + bool auto_op_full;
> + unsigned int major;
> + unsigned int minor;
> + unsigned int tot_chans;
>
may be num_chans or chan_count ?
> + int cmb_irq;
> + struct ctrl_page __iomem *ctrl;
> + union {
> + struct mhu3_pbx_frame_reg __iomem *pbx;
> + struct mhu3_mbx_frame_reg __iomem *mbx;
> + };
> + struct mhuv3_extension *ext[MAX_EXT];
> + struct mbox_controller mbox;
> +};
> +
> +#define mhu_from_mbox(_mbox) container_of(_mbox, struct mhuv3, mbox)
> +
> +typedef int (*mhuv3_extension_initializer)(struct mhuv3 *mhu);
> +
> +/* =================== Doorbell transport protocol operations =============== */
> +
> +static void mhuv3_doorbell_tx_startup(struct mhuv3 *mhu, struct mbox_chan *chan)
> +{
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + /* Enable Transfer Acknowledgment events */
> + writel_relaxed_bitfield(0x1, &mhu->pbx->dbcw[priv->ch_idx].int_en, tfr_ack);
> +}
> +
> +static void mhuv3_doorbell_tx_shutdown(struct mhuv3 *mhu, struct mbox_chan *chan)
> +{
> + unsigned long flags;
> + struct mhuv3_extension *e = mhu->ext[DBE_EXT];
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
In order of decreasing line-lengths please everywhere.
> + /* Disable Channel Transfer Ack events */
> + writel_relaxed_bitfield(0x0, &mhu->pbx->dbcw[priv->ch_idx].int_en, tfr_ack);
> +
> + /* Clear Channel Transfer Ack and pending doorbells */
> + writel_relaxed_bitfield(0x1, &mhu->pbx->dbcw[priv->ch_idx].int_clr, tfr_ack);
> + spin_lock_irqsave(&e->pending_lock, flags);
> + e->pending_db[priv->ch_idx] = 0;
> + spin_unlock_irqrestore(&e->pending_lock, flags);
> +}
> +
> +static int mhuv3_doorbell_rx_startup(struct mhuv3 *mhu, struct mbox_chan *chan)
> +{
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + /* Unmask Channel Transfer events */
> + writel_relaxed(BIT(priv->doorbell), &mhu->mbx->dbcw[priv->ch_idx].msk_clr);
> +
> + return 0;
> +}
> +
> +static void mhuv3_doorbell_rx_shutdown(struct mhuv3 *mhu,
> + struct mbox_chan *chan)
> +{
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + /* Mask Channel Transfer events */
> + writel_relaxed(BIT(priv->doorbell), &mhu->mbx->dbcw[priv->ch_idx].msk_set);
> +}
> +
> +static void mhuv3_doorbell_rx_complete(struct mhuv3 *mhu, struct mbox_chan *chan)
> +{
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + /* Clearing the pending transfer generates the Channel Transfer Ack */
> + writel_relaxed(BIT(priv->doorbell), &mhu->mbx->dbcw[priv->ch_idx].clr);
> +}
> +
> +static int mhuv3_doorbell_last_tx_done(struct mhuv3 *mhu,
> + struct mbox_chan *chan)
> +{
> + int done;
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + done = !(readl_relaxed(&mhu->pbx->dbcw[priv->ch_idx].st) &
> + BIT(priv->doorbell));
> + if (done) {
> + unsigned long flags;
> + struct mhuv3_extension *e = mhu->ext[DBE_EXT];
> +
> + /* Take care to clear the pending doorbell also when polling */
> + spin_lock_irqsave(&e->pending_lock, flags);
> + e->pending_db[priv->ch_idx] &= ~BIT(priv->doorbell);
> + spin_unlock_irqrestore(&e->pending_lock, flags);
> + }
> +
> + return done;
> +}
> +
> +static int mhuv3_doorbell_send_data(struct mhuv3 *mhu, struct mbox_chan *chan,
> + void *arg)
> +{
> + int ret = 0;
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> + struct mhuv3_extension *e = mhu->ext[DBE_EXT];
> + unsigned long flags;
> +
> + spin_lock_irqsave(&e->pending_lock, flags);
> + /* Only one in-flight Transfer is allowed per-doorbell */
> + if (!(e->pending_db[priv->ch_idx] & BIT(priv->doorbell))) {
> + e->pending_db[priv->ch_idx] |= BIT(priv->doorbell);
> + writel_relaxed(BIT(priv->doorbell),
> + &mhu->pbx->dbcw[priv->ch_idx].set);
> + } else {
> + ret = -EBUSY;
> + }
> + spin_unlock_irqrestore(&e->pending_lock, flags);
> +
> + return ret;
> +}
> +
> +static const struct mhuv3_protocol_ops mhuv3_doorbell_ops = {
> + .tx_startup = mhuv3_doorbell_tx_startup,
> + .tx_shutdown = mhuv3_doorbell_tx_shutdown,
> + .rx_startup = mhuv3_doorbell_rx_startup,
> + .rx_shutdown = mhuv3_doorbell_rx_shutdown,
> + .rx_complete = mhuv3_doorbell_rx_complete,
> + .last_tx_done = mhuv3_doorbell_last_tx_done,
> + .send_data = mhuv3_doorbell_send_data,
> +};
> +
> +/* Sender and receiver mailbox ops */
> +static bool mhuv3_sender_last_tx_done(struct mbox_chan *chan)
> +{
> + struct mhuv3 *mhu = mhu_from_mbox(chan->mbox);
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + return priv->ops->last_tx_done(mhu, chan);
> +}
> +
> +static int mhuv3_sender_send_data(struct mbox_chan *chan, void *data)
> +{
> + struct mhuv3 *mhu = mhu_from_mbox(chan->mbox);
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + if (!priv->ops->last_tx_done(mhu, chan))
> + return -EBUSY;
> +
> + return priv->ops->send_data(mhu, chan, data);
> +}
> +
> +static int mhuv3_sender_startup(struct mbox_chan *chan)
> +{
> + struct mhuv3 *mhu = mhu_from_mbox(chan->mbox);
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + if (priv->ops->tx_startup)
> + priv->ops->tx_startup(mhu, chan);
> +
> + return 0;
> +}
> +
> +static void mhuv3_sender_shutdown(struct mbox_chan *chan)
> +{
> + struct mhuv3 *mhu = mhu_from_mbox(chan->mbox);
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + if (priv->ops->tx_shutdown)
> + priv->ops->tx_shutdown(mhu, chan);
> +}
> +
> +static const struct mbox_chan_ops mhuv3_sender_ops = {
> + .send_data = mhuv3_sender_send_data,
> + .startup = mhuv3_sender_startup,
> + .shutdown = mhuv3_sender_shutdown,
> + .last_tx_done = mhuv3_sender_last_tx_done,
> +};
> +
> +static int mhuv3_receiver_startup(struct mbox_chan *chan)
> +{
> + struct mhuv3 *mhu = mhu_from_mbox(chan->mbox);
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + return priv->ops->rx_startup(mhu, chan);
> +}
> +
> +static void mhuv3_receiver_shutdown(struct mbox_chan *chan)
> +{
> + struct mhuv3 *mhu = mhu_from_mbox(chan->mbox);
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + priv->ops->rx_shutdown(mhu, chan);
> +}
> +
> +static int mhuv3_receiver_send_data(struct mbox_chan *chan, void *data)
> +{
> + dev_err(chan->mbox->dev,
> + "Trying to transmit on a MBX MHUv3 frame\n");
> + return -EIO;
> +}
> +
> +static bool mhuv3_receiver_last_tx_done(struct mbox_chan *chan)
> +{
> + dev_err(chan->mbox->dev, "Trying to Tx poll on a MBX MHUv3 frame\n");
> + return true;
> +}
> +
> +static const struct mbox_chan_ops mhuv3_receiver_ops = {
> + .send_data = mhuv3_receiver_send_data,
> + .startup = mhuv3_receiver_startup,
> + .shutdown = mhuv3_receiver_shutdown,
> + .last_tx_done = mhuv3_receiver_last_tx_done,
> +};
> +
> +static struct mbox_chan *mhuv3_dbe_mbox_of_xlate(struct mhuv3 *mhu,
> + unsigned int channel,
> + unsigned int doorbell)
> +{
> + struct mbox_controller *mbox = &mhu->mbox;
> + struct mbox_chan *chans = mbox->chans;
> + struct mhuv3_extension *e = mhu->ext[DBE_EXT];
> +
> + if (channel >= e->max_chans || doorbell >= MHUV3_STAT_BITS) {
> + dev_err(mbox->dev, "Couldn't xlate to a valid channel (%d: %d)\n",
> + channel, doorbell);
> + return ERR_PTR(-ENODEV);
> + }
> +
> + return &chans[e->base_ch_idx + channel * MHUV3_STAT_BITS + doorbell];
> +}
> +
> +static void mhuv3_dbe_combined_irq_setup(struct mhuv3 *mhu)
> +{
> + int i;
> + struct mhuv3_extension *e = mhu->ext[DBE_EXT];
> +
> + if (mhu->frame == PBX_FRAME) {
> + struct pdbcw_page __iomem *dbcw = mhu->pbx->dbcw;
> +
> + for (i = 0; i < e->max_chans; i++) {
> + writel_relaxed_bitfield(0x1, &dbcw[i].int_clr, tfr_ack);
> + writel_relaxed_bitfield(0x0, &dbcw[i].int_en, tfr_ack);
> + writel_relaxed_bitfield(0x1, &dbcw[i].ctrl, comb_en);
> + }
> + } else {
> + struct mdbcw_page __iomem *dbcw = mhu->mbx->dbcw;
> +
> + for (i = 0; i < e->max_chans; i++) {
> + writel_relaxed(0xFFFFFFFF, &dbcw[i].clr);
> + writel_relaxed(0xFFFFFFFF, &dbcw[i].msk_set);
> + writel_relaxed_bitfield(0x1, &dbcw[i].ctrl, comb_en);
> + }
> + }
> +}
> +
> +static int mhuv3_dbe_channels_init(struct mhuv3 *mhu)
> +{
> + int i;
> + struct mhuv3_extension *e = mhu->ext[DBE_EXT];
> + struct mbox_controller *mbox = &mhu->mbox;
> + struct mbox_chan *chans;
> +
> + chans = mbox->chans + mbox->num_chans;
> + e->base_ch_idx = mbox->num_chans;
> + for (i = 0; i < e->max_chans; i++) {
> + int k;
> + struct mhuv3_mbox_chan_priv *priv;
> +
> + for (k = 0; k < MHUV3_STAT_BITS; k++) {
> + priv = devm_kmalloc(mbox->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->ch_idx = i;
> + priv->ops = &mhuv3_doorbell_ops;
> + priv->doorbell = k;
> + chans++->con_priv = priv;
> + mbox->num_chans++;
> + }
> + }
> +
> + spin_lock_init(&e->pending_lock);
> +
> + return 0;
> +}
> +
> +static struct mbox_chan *mhuv3_dbe_chan_from_comb_irq_get(struct mhuv3 *mhu)
> +{
> + int i;
> + struct mhuv3_extension *e = mhu->ext[DBE_EXT];
> + struct device *dev = mhu->mbox.dev;
> +
> + for (i = 0; i < MHUV3_DBCH_CMB_INT_ST_REG_CNT; i++) {
> + unsigned int channel, db = MHUV3_INVALID_DOORBELL;
> + u32 cmb_st, st;
> +
> + cmb_st = readl_relaxed(&mhu->ctrl->dbch_int_st[i]);
> + if (!cmb_st)
> + continue;
> +
> + channel = i * MHUV3_STAT_BITS + __builtin_ctz(cmb_st);
__ffs instead of __builtin_ctz please.
> + if (channel >= e->max_chans) {
> + dev_err(dev, "Invalid %s channel:%d\n",
> + mhuv3_str[mhu->frame], channel);
> + break;
> + }
> +
> + if (mhu->frame == PBX_FRAME) {
> + unsigned long flags;
> + u32 active_dbs, fired_dbs;
> +
> + st = readl_relaxed_bitfield(&mhu->pbx->dbcw[channel].int_st,
> + tfr_ack);
> + if (!st) {
> + dev_warn(dev, "Spurios IRQ on %s channel:%d\n",
> + mhuv3_str[mhu->frame], channel);
> + continue;
> + }
> +
> + active_dbs = readl_relaxed(&mhu->pbx->dbcw[channel].st);
> + spin_lock_irqsave(&e->pending_lock, flags);
> + fired_dbs = e->pending_db[channel] & ~active_dbs;
> + if (fired_dbs) {
> + db = __builtin_ctz(fired_dbs);
> + e->pending_db[channel] &= ~BIT(db);
> + fired_dbs &= ~BIT(db);
> + }
> + spin_unlock_irqrestore(&e->pending_lock, flags);
> +
> + /* Clear TFR Ack if no more doorbells pending */
> + if (!fired_dbs)
> + writel_relaxed_bitfield(0x1,
> + &mhu->pbx->dbcw[channel].int_clr,
> + tfr_ack);
> + } else {
> + st = readl_relaxed(&mhu->mbx->dbcw[channel].st_msk);
> + if (!st) {
> + dev_warn(dev, "Spurios IRQ on %s channel:%d\n",
> + mhuv3_str[mhu->frame], channel);
> + continue;
> + }
> + db = __builtin_ctz(st);
> + }
> +
> + if (db != MHUV3_INVALID_DOORBELL) {
> + dev_dbg(dev, "Found %s ch[%d]/db[%d]\n",
> + mhuv3_str[mhu->frame], channel, db);
> +
> + return &mhu->mbox.chans[channel * MHUV3_STAT_BITS + db];
> + }
> + }
> +
> + return ERR_PTR(-EIO);
> +}
> +
> +static int mhuv3_dbe_init(struct mhuv3 *mhu)
> +{
> + struct mhuv3_extension *e;
> + struct device *dev = mhu->mbox.dev;
> +
> + if (!readl_relaxed_bitfield(&mhu->ctrl->feat_spt0, dbe_spt))
> + return 0;
> +
> + dev_dbg(dev, "%s: Initializing DBE Extension.\n", mhuv3_str[mhu->frame]);
> +
> + e = devm_kzalloc(dev, sizeof(*e), GFP_KERNEL);
> + if (!e)
> + return -ENOMEM;
> +
> + e->type = DBE_EXT;
> + /* Note that, by the spec, the number of channels is (num_dbch + 1) */
> + e->max_chans =
> + readl_relaxed_bitfield(&mhu->ctrl->dbch_cfg0, num_dbch) + 1;
> + e->mbox_of_xlate = mhuv3_dbe_mbox_of_xlate;
> + e->combined_irq_setup = mhuv3_dbe_combined_irq_setup;
> + e->channels_init = mhuv3_dbe_channels_init;
> + e->chan_from_comb_irq_get = mhuv3_dbe_chan_from_comb_irq_get;
> +
> + mhu->tot_chans += e->max_chans * MHUV3_STAT_BITS;
> + mhu->ext[DBE_EXT] = e;
> +
> + dev_info(dev, "%s: found %d DBE channels.\n",
> + mhuv3_str[mhu->frame], e->max_chans);
> +
> + return 0;
> +}
> +
> +static int mhuv3_fce_init(struct mhuv3 *mhu)
> +{
> + struct device *dev = mhu->mbox.dev;
> +
> + if (!readl_relaxed_bitfield(&mhu->ctrl->feat_spt0, fce_spt))
> + return 0;
> +
> + dev_dbg(dev, "%s: FCE Extension not supported by driver.\n",
> + mhuv3_str[mhu->frame]);
> +
> + return 0;
> +}
> +
> +static int mhuv3_fe_init(struct mhuv3 *mhu)
> +{
> + struct device *dev = mhu->mbox.dev;
> +
> + if (!readl_relaxed_bitfield(&mhu->ctrl->feat_spt0, fe_spt))
> + return 0;
> +
> + dev_dbg(dev, "%s: FE Extension not supported by driver.\n",
> + mhuv3_str[mhu->frame]);
> +
> + return 0;
> +}
> +
> +static mhuv3_extension_initializer mhuv3_extension_init[MAX_EXT] = {
> + mhuv3_dbe_init,
> + mhuv3_fce_init,
> + mhuv3_fe_init,
> +};
> +
> +static int mhuv3_initialize_channels(struct device *dev, struct mhuv3 *mhu)
> +{
> + int i, ret = 0;
> + struct mbox_controller *mbox = &mhu->mbox;
> +
> + mbox->chans = devm_kcalloc(dev, mhu->tot_chans,
> + sizeof(*mbox->chans), GFP_KERNEL);
> + if (!mbox->chans)
> + return -ENOMEM;
> +
> + for (i = FIRST_EXT; i < MAX_EXT && !ret; i++)
> + if (mhu->ext[i])
> + ret = mhu->ext[i]->channels_init(mhu);
> +
> + return ret;
> +}
> +
> +static struct mbox_chan *mhuv3_mbox_of_xlate(struct mbox_controller *mbox,
> + const struct of_phandle_args *pa)
> +{
> + unsigned int type, channel, param;
> + struct mhuv3 *mhu = mhu_from_mbox(mbox);
> +
> + if (pa->args_count != MHUV3_MBOX_CELLS)
> + return ERR_PTR(-EINVAL);
> +
> + type = pa->args[MHUV3_MBOX_CELL_TYPE];
> + if (type >= MAX_EXT)
> + return ERR_PTR(-EINVAL);
> +
> + channel = pa->args[MHUV3_MBOX_CELL_CHWN];
> + param = pa->args[MHUV3_MBOX_CELL_PARAM];
> +
> + return mhu->ext[type]->mbox_of_xlate(mhu, channel, param);
> +}
> +
> +static int mhuv3_frame_init(struct mhuv3 *mhu, void __iomem *regs)
> +{
> + int i, ret = 0;
> + struct device *dev = mhu->mbox.dev;
> +
> + mhu->ctrl = regs;
> + mhu->frame = readl_relaxed_bitfield(&mhu->ctrl->blk_id, blk_id);
> + if (mhu->frame > MBX_FRAME) {
> + dev_err(dev, "Invalid Frame type- %d\n", mhu->frame);
> + return -EINVAL;
> + }
> +
> + mhu->major = readl_relaxed_bitfield(&mhu->ctrl->aidr, arch_major_rev);
> + mhu->minor = readl_relaxed_bitfield(&mhu->ctrl->aidr, arch_minor_rev);
> + if (mhu->major != MHUV3_MAJOR_VERSION) {
> + dev_warn(dev, "Unsupported MHU %s block - major:%d minor:%d\n",
> + mhuv3_str[mhu->frame], mhu->major, mhu->minor);
> + return -EINVAL;
> + }
> + mhu->auto_op_full = !!readl_relaxed_bitfield(&mhu->ctrl->feat_spt1,
> + auto_op_spt);
> + /* Request the PBX/MBX to remain operational */
> + if (mhu->auto_op_full)
> + writel_relaxed_bitfield(0x1, &mhu->ctrl->ctrl, op_req);
> +
> + dev_dbg(dev, "Found MHU %s block - major:%d minor:%d\n",
> + mhuv3_str[mhu->frame], mhu->major, mhu->minor);
> +
> + if (mhu->frame == PBX_FRAME)
> + mhu->pbx = regs;
> + else
> + mhu->mbx = regs;
> +
> + for (i = FIRST_EXT; i < MAX_EXT && !ret; i++)
> + ret = mhuv3_extension_init[i](mhu);
> +
> + return ret;
> +}
> +
> +static irqreturn_t mhuv3_pbx_comb_interrupt(int irq, void *arg)
> +{
> + int ret = IRQ_NONE;
> + unsigned int i, found = 0;
> + struct mhuv3 *mhu = arg;
> + struct device *dev = mhu->mbox.dev;
> + struct mbox_chan *chan;
> +
> + for (i = FIRST_EXT; i < MAX_EXT; i++) {
> + /* FCE does not participate to the PBX combined */
> + if (i == FCE_EXT || !mhu->ext[i])
> + continue;
> +
> + chan = mhu->ext[i]->chan_from_comb_irq_get(mhu);
> + if (!IS_ERR(chan)) {
>
'continue' for error instead, to have fewer indented lines.
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + found++;
> + if (chan->cl) {
> + mbox_chan_txdone(chan, 0);
> + ret = IRQ_HANDLED;
> + } else {
> + dev_warn(dev,
> + "TX Ack on UNBOUND channel (%u)\n",
> + priv->ch_idx);
> + }
> + }
> + }
> +
> + if (!found)
> + dev_warn_once(dev, "Failed to find channel for the TX interrupt\n");
> +
> + return ret;
> +}
> +
> +static irqreturn_t mhuv3_mbx_comb_interrupt(int irq, void *arg)
> +{
> + int ret = IRQ_NONE;
> + unsigned int i, found = 0;
> + struct mhuv3 *mhu = arg;
> + struct device *dev = mhu->mbox.dev;
> + struct mbox_chan *chan;
> +
> + for (i = FIRST_EXT; i < MAX_EXT; i++) {
> + if (!mhu->ext[i])
> + continue;
> +
> + /* Process any extension which could be source of the IRQ */
> + chan = mhu->ext[i]->chan_from_comb_irq_get(mhu);
> + if (!IS_ERR(chan)) {
'continue' for error instead, to have fewer indented lines.
> + void *data = NULL;
> + struct mhuv3_mbox_chan_priv *priv = chan->con_priv;
> +
> + found++;
> + /* Read and acknowledge optional in-band LE data first. */
> + if (priv->ops->read_data)
> + data = priv->ops->read_data(mhu, chan);
> +
> + if (chan->cl && !IS_ERR(data)) {
> + mbox_chan_received_data(chan, data);
> + ret = IRQ_HANDLED;
> + } else if (!chan->cl) {
> + dev_warn(dev,
> + "RX Data on UNBOUND channel (%u)\n",
> + priv->ch_idx);
> + } else {
> + dev_err(dev, "Failed to read data: %lu\n",
> + PTR_ERR(data));
> + }
> +
> + if (!IS_ERR(data))
> + kfree(data);
> +
> + /*
> + * Acknowledge transfer after any possible optional
> + * out-of-band data has also been retrieved via
> + * mbox_chan_received_data().
> + */
> + if (priv->ops->rx_complete)
> + priv->ops->rx_complete(mhu, chan);
> + }
> + }
> +
> + if (!found)
> + dev_warn_once(dev, "Failed to find channel for the RX interrupt\n");
> +
> + return ret;
> +}
> +
> +static int mhuv3_setup_pbx(struct mhuv3 *mhu)
> +{
> + struct device *dev = mhu->mbox.dev;
> +
> + mhu->mbox.ops = &mhuv3_sender_ops;
> +
> + if (mhu->cmb_irq > 0) {
> + int ret;
> +
> + ret = devm_request_threaded_irq(dev, mhu->cmb_irq, NULL,
> + mhuv3_pbx_comb_interrupt,
> + IRQF_ONESHOT, "mhuv3-pbx", mhu);
> + if (!ret) {
> + int i;
> +
> + mhu->mbox.txdone_irq = true;
> + mhu->mbox.txdone_poll = false;
> +
> + for (i = FIRST_EXT; i < MAX_EXT; i++)
> + if (mhu->ext[i])
> + mhu->ext[i]->combined_irq_setup(mhu);
> +
> + dev_dbg(dev, "MHUv3 PBX IRQs initialized.\n");
> +
> + return 0;
> + }
> +
> + dev_err(dev, "Failed to request PBX IRQ - ret:%d", ret);
> + }
> +
> + dev_info(dev, "Using PBX in Tx polling mode.\n");
> + mhu->mbox.txdone_irq = false;
> + mhu->mbox.txdone_poll = true;
> + mhu->mbox.txpoll_period = 1;
> +
> + return 0;
> +}
> +
> +static int mhuv3_setup_mbx(struct mhuv3 *mhu)
> +{
> + int ret, i;
> + struct device *dev = mhu->mbox.dev;
> +
> + mhu->mbox.ops = &mhuv3_receiver_ops;
> +
> + if (mhu->cmb_irq <= 0) {
> + dev_err(dev, "Missing MBX combined IRQ !\n");
> + return -EINVAL;
> + }
> +
> + ret = devm_request_threaded_irq(dev, mhu->cmb_irq, NULL,
> + mhuv3_mbx_comb_interrupt, IRQF_ONESHOT,
> + "mhuv3-mbx", mhu);
> + if (ret) {
> + dev_err(dev, "Failed to request MBX IRQ - ret:%d\n", ret);
> + return ret;
> + }
> +
> + for (i = FIRST_EXT; i < MAX_EXT; i++)
> + if (mhu->ext[i])
> + mhu->ext[i]->combined_irq_setup(mhu);
> +
> + dev_dbg(dev, "MHUv3 MBX IRQs initialized.\n");
> +
> + return ret;
> +}
> +
> +static int mhuv3_irqs_init(struct mhuv3 *mhu, struct platform_device *pdev)
> +{
> + int ret;
> +
> + dev_dbg(mhu->mbox.dev, "Initializing %s block.\n", mhuv3_str[mhu->frame]);
> +
> + if (mhu->frame == PBX_FRAME) {
> + mhu->cmb_irq = platform_get_irq_byname_optional(pdev, "combined");
> + ret = mhuv3_setup_pbx(mhu);
> + } else {
> + mhu->cmb_irq = platform_get_irq_byname(pdev, "combined");
> + ret = mhuv3_setup_mbx(mhu);
> + }
> +
> + return ret;
> +}
> +
> +static int mhuv3_probe(struct platform_device *pdev)
> +{
> + int ret;
> + struct mhuv3 *mhu;
> + void __iomem *regs;
> + struct device *dev = &pdev->dev;
> +
> + mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
> + if (!mhu)
> + return -ENOMEM;
> +
> + regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(regs))
> + return PTR_ERR(regs);
> +
> + mhu->mbox.dev = dev;
> + ret = mhuv3_frame_init(mhu, regs);
> + if (ret)
> + return ret;
> +
> + ret = mhuv3_irqs_init(mhu, pdev);
> + if (ret)
> + return ret;
> +
> + mhu->mbox.of_xlate = mhuv3_mbox_of_xlate;
> + ret = mhuv3_initialize_channels(dev, mhu);
> + if (ret)
> + return ret;
> +
> + ret = devm_mbox_controller_register(dev, &mhu->mbox);
> + if (ret)
> + dev_err(dev, "failed to register ARM MHUv3 driver %d\n", ret);
> +
> + platform_set_drvdata(pdev, mhu);
> +
> + return ret;
> +}
> +
> +static int mhuv3_remove(struct platform_device *pdev)
> +{
> + struct mhuv3 *mhu = platform_get_drvdata(pdev);
> +
> + if (mhu->auto_op_full)
> + writel_relaxed_bitfield(0x0, &mhu->ctrl->ctrl, op_req);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mhuv3_of_match[] = {
> + { .compatible = "arm,mhuv3", .data = NULL },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, mhuv3_of_match);
> +
> +static struct platform_driver mhuv3_driver = {
> + .driver = {
> + .name = "arm-mhuv3-mailbox",
> + .of_match_table = mhuv3_of_match,
> + },
> + .probe = mhuv3_probe,
> + .remove = mhuv3_remove,
> +};
> +module_platform_driver(mhuv3_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("ARM MHUv3 Driver");
> +MODULE_AUTHOR("Cristian Marussi <cristian.marussi@arm.com>");
> --
> 2.34.1
>
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^ permalink raw reply
* [PATCH v2 0/2] Add missing mmc statistics in DW GMAC
From: Minda Chen @ 2024-04-08 1:29 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, netdev
Cc: linux-stm32, linux-arm-kernel, linux-kernel
Add miss MMC statistic in DW GMAC
base on 6.9-rc1
changed
v2:
patch2 : remove mmc_rx_control_g due to it is gotten in
ethtool_ops::get_eth_ctrl_stats.
Minda Chen (2):
net: stmmac: mmc_core: Add GMAC LPI statistics
net: stmmac: mmc_core: Add GMAC mmc tx/rx missing statistics
drivers/net/ethernet/stmicro/stmmac/mmc.h | 2 ++
drivers/net/ethernet/stmicro/stmmac/mmc_core.c | 15 +++++++++++++++
.../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 2 ++
3 files changed, 19 insertions(+)
base-commit: 4cece764965020c22cff7665b18a012006359095
--
2.17.1
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^ permalink raw reply
* [PATCH v2 1/2] net: stmmac: mmc_core: Add GMAC LPI statistics
From: Minda Chen @ 2024-04-08 1:29 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, netdev
Cc: linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20240408012943.66508-1-minda.chen@starfivetech.com>
XGMAC MMC has already added LPI statistics. GMAC MMC lack of these
statistics. Add register definition and reading the LPI statistics
from registers.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Simon Horman <horms@kernel.org>
---
drivers/net/ethernet/stmicro/stmmac/mmc_core.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
index 7eb477faa75a..b0db5f4e8fe8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
@@ -79,6 +79,12 @@
#define MMC_RX_FIFO_OVERFLOW 0xd4
#define MMC_RX_VLAN_FRAMES_GB 0xd8
#define MMC_RX_WATCHDOG_ERROR 0xdc
+
+#define MMC_TX_LPI_USEC 0xec
+#define MMC_TX_LPI_TRAN 0xf0
+#define MMC_RX_LPI_USEC 0xf4
+#define MMC_RX_LPI_TRAN 0xf8
+
/* IPC*/
#define MMC_RX_IPC_INTR_MASK 0x100
#define MMC_RX_IPC_INTR 0x108
@@ -283,6 +289,8 @@ static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);
mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);
mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);
+ mmc->mmc_tx_lpi_usec += readl(mmcaddr + MMC_TX_LPI_USEC);
+ mmc->mmc_tx_lpi_tran += readl(mmcaddr + MMC_TX_LPI_TRAN);
/* MMC RX counter registers */
mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB);
@@ -316,6 +324,9 @@ static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);
mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);
mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);
+ mmc->mmc_rx_lpi_usec += readl(mmcaddr + MMC_RX_LPI_USEC);
+ mmc->mmc_rx_lpi_tran += readl(mmcaddr + MMC_RX_LPI_TRAN);
+
/* IPv4 */
mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD);
mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR);
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 2/2] net: stmmac: mmc_core: Add GMAC mmc tx/rx missing statistics
From: Minda Chen @ 2024-04-08 1:29 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, netdev
Cc: linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20240408012943.66508-1-minda.chen@starfivetech.com>
The missing statistics including Rx_Receive_Error_Packets and
Tx_OSize_Packets_Good.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Simon Horman <horms@kernel.org>
---
drivers/net/ethernet/stmicro/stmmac/mmc.h | 2 ++
drivers/net/ethernet/stmicro/stmmac/mmc_core.c | 4 ++++
drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 2 ++
3 files changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc.h b/drivers/net/ethernet/stmicro/stmmac/mmc.h
index dff02d75d519..5d1ea3e07459 100644
--- a/drivers/net/ethernet/stmicro/stmmac/mmc.h
+++ b/drivers/net/ethernet/stmicro/stmmac/mmc.h
@@ -52,6 +52,7 @@ struct stmmac_counters {
unsigned int mmc_tx_excessdef;
unsigned int mmc_tx_pause_frame;
unsigned int mmc_tx_vlan_frame_g;
+ unsigned int mmc_tx_oversize_g;
unsigned int mmc_tx_lpi_usec;
unsigned int mmc_tx_lpi_tran;
@@ -80,6 +81,7 @@ struct stmmac_counters {
unsigned int mmc_rx_fifo_overflow;
unsigned int mmc_rx_vlan_frames_gb;
unsigned int mmc_rx_watchdog_error;
+ unsigned int mmc_rx_error;
unsigned int mmc_rx_lpi_usec;
unsigned int mmc_rx_lpi_tran;
unsigned int mmc_rx_discard_frames_gb;
diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
index b0db5f4e8fe8..0fab842902a8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
@@ -53,6 +53,7 @@
#define MMC_TX_EXCESSDEF 0x6c
#define MMC_TX_PAUSE_FRAME 0x70
#define MMC_TX_VLAN_FRAME_G 0x74
+#define MMC_TX_OVERSIZE_G 0x78
/* MMC RX counter registers */
#define MMC_RX_FRAMECOUNT_GB 0x80
@@ -79,6 +80,7 @@
#define MMC_RX_FIFO_OVERFLOW 0xd4
#define MMC_RX_VLAN_FRAMES_GB 0xd8
#define MMC_RX_WATCHDOG_ERROR 0xdc
+#define MMC_RX_ERROR 0xe0
#define MMC_TX_LPI_USEC 0xec
#define MMC_TX_LPI_TRAN 0xf0
@@ -289,6 +291,7 @@ static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);
mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);
mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);
+ mmc->mmc_tx_oversize_g += readl(mmcaddr + MMC_TX_OVERSIZE_G);
mmc->mmc_tx_lpi_usec += readl(mmcaddr + MMC_TX_LPI_USEC);
mmc->mmc_tx_lpi_tran += readl(mmcaddr + MMC_TX_LPI_TRAN);
@@ -324,6 +327,7 @@ static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);
mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);
mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);
+ mmc->mmc_rx_error += readl(mmcaddr + MMC_RX_ERROR);
mmc->mmc_rx_lpi_usec += readl(mmcaddr + MMC_RX_LPI_USEC);
mmc->mmc_rx_lpi_tran += readl(mmcaddr + MMC_RX_LPI_TRAN);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index e1537a57815f..542e2633a6f5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -212,6 +212,7 @@ static const struct stmmac_stats stmmac_mmc[] = {
STMMAC_MMC_STAT(mmc_tx_excessdef),
STMMAC_MMC_STAT(mmc_tx_pause_frame),
STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
+ STMMAC_MMC_STAT(mmc_tx_oversize_g),
STMMAC_MMC_STAT(mmc_tx_lpi_usec),
STMMAC_MMC_STAT(mmc_tx_lpi_tran),
STMMAC_MMC_STAT(mmc_rx_framecount_gb),
@@ -238,6 +239,7 @@ static const struct stmmac_stats stmmac_mmc[] = {
STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
STMMAC_MMC_STAT(mmc_rx_watchdog_error),
+ STMMAC_MMC_STAT(mmc_rx_error),
STMMAC_MMC_STAT(mmc_rx_lpi_usec),
STMMAC_MMC_STAT(mmc_rx_lpi_tran),
STMMAC_MMC_STAT(mmc_rx_discard_frames_gb),
--
2.17.1
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^ permalink raw reply related
* Re: (subset) [PATCH v3 1/2] dt-bindings: arm: qcom: Add Motorola Moto G (2013)
From: Bjorn Andersson @ 2024-04-08 1:37 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stanislav Jakubek
Cc: linux-arm-msm, devicetree, linux-arm-kernel, phone-devel,
linux-kernel
In-Reply-To: <32c507337ab80c550fb1df08f7014d1e31eb4c32.1712480582.git.stano.jakubek@gmail.com>
On Sun, 07 Apr 2024 11:05:10 +0200, Stanislav Jakubek wrote:
> Document the Motorola Moto G (2013), which is a smartphone based
> on the Qualcomm MSM8226 SoC.
>
>
Applied, thanks!
[1/2] dt-bindings: arm: qcom: Add Motorola Moto G (2013)
commit: 4785ec47ec890fe66f31ee886a767dbdf2ea6bae
[2/2] ARM: dts: qcom: Add support for Motorola Moto G (2013)
commit: 49481b6a8f35017af23e9fdfb644095f50a474e3
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
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^ permalink raw reply
* Re: [RFC][PATCH 0/2] Amlogic T7 (A113D2) Clock Driver
From: Xianwei Zhao @ 2024-04-08 1:39 UTC (permalink / raw)
To: tanure
Cc: Yu Tu, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Michael Turquette, linux-arm-kernel,
linux-amlogic, devicetree, linux-kernel, linux-clk
In-Reply-To: <CAJX_Q+2wA+hNDhYtOsMi-DyuvH0KfkVgbsVFBFDj=Ph4fOEJaw@mail.gmail.com>
Hi Lucas,
Thanks for your reply.
On 2024/4/3 16:12, Lucas Tanure wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, Apr 3, 2024 at 7:44 AM Xianwei Zhao <xianwei.zhao@amlogic.com> wrote:
>>
>> Hi Lucas,
>> As we are preparing the T7 clock patchset, we would like to your
>> purpose and plan of this RFC patches. Are you going to submit these
>> patches at last?
>
> Hi Xianwei,
>
> I made some progress, and now the SD card controller probes but fails
> to read blocks from the SD card. I do think my port of the clock
> driver is okay, but I will not send my clock driver until the SD card
> fully works, so I am sure the clocking driver is tested.
> But if you have something already done, please send it, and I will
> test and review it from my side.
>
> Any help with the sdcard controller is also much appreciated.
>
The SDCard part works well on our clock patchset. Then we will send the
formal clock submission later. What do you think?
> Thanks
> Lucas
>
>> On 2024/3/18 19:43, Lucas Tanure wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> I am trying to port the T7 clock driver from Khadas 5.4 kernel for Vim4
>>> to mainline, but I am encountering some issues in the path.
>>>
>>> The kernel panics at clk_mux_val_to_index, but I believe that all the
>>> needed clocks are registered.
>>>
>>> If anyone from Amlogic or the community could help me understand what
>>> my driver is missing, that would be great.
>>> I will continue to try to figure out, but it has been some weeks
>>> without progress =/.
>>>
>>> Lucas Tanure (2):
>>> clk: meson: T7: add support for Amlogic T7 SoC PLL clock driver
>>> arm64: dts: amlogic: t7: SDCard, Ethernet and Clocking
>>>
>>> .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 66 +
>>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 189 +
>>> drivers/clk/meson/Kconfig | 25 +
>>> drivers/clk/meson/Makefile | 2 +
>>> drivers/clk/meson/t7-peripherals.c | 6368 +++++++++++++++++
>>> drivers/clk/meson/t7-peripherals.h | 131 +
>>> drivers/clk/meson/t7-pll.c | 1543 ++++
>>> drivers/clk/meson/t7-pll.h | 83 +
>>> .../clock/amlogic,t7-peripherals-clkc.h | 410 ++
>>> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 69 +
>>> 10 files changed, 8886 insertions(+)
>>> create mode 100644 drivers/clk/meson/t7-peripherals.c
>>> create mode 100644 drivers/clk/meson/t7-peripherals.h
>>> create mode 100644 drivers/clk/meson/t7-pll.c
>>> create mode 100644 drivers/clk/meson/t7-pll.h
>>> create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
>>> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>>>
>>> Starting kernel ...
>>>
>>> uboot time: 14277917 us
>>> boot 64bit kernel
>>> [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd092]
>>> [ 0.000000] Linux version 6.8.0-09793-gda876e5b54b3-dirty (tanureal@ryzen) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621, GNU ld (GNU Toolchain for the A-pr4
>>> [ 0.000000] KASLR disabled due to lack of seed
>>> [ 0.000000] Machine model: Khadas vim4
>>> [ 0.000000] efi: UEFI not found.
>>> [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
>>> [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
>>> [ 0.000000] NUMA: No NUMA configuration found
>>> [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000df7fffff]
>>> [ 0.000000] NUMA: NODE_DATA [mem 0xdf10c9c0-0xdf10efff]
>>> [ 0.000000] Zone ranges:
>>> [ 0.000000] DMA [mem 0x0000000000000000-0x00000000df7fffff]
>>> [ 0.000000] DMA32 empty
>>> [ 0.000000] Normal empty
>>> [ 0.000000] Movable zone start for each node
>>> [ 0.000000] Early memory node ranges
>>> [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
>>> [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
>>> [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000df7fffff]
>>> [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000df7fffff]
>>> [ 0.000000] On node 0, zone DMA: 2048 pages in unavailable ranges
>>> [ 0.000000] cma: Reserved 32 MiB at 0x00000000d9800000 on node -1
>>> [ 0.000000] psci: probing for conduit method from DT.
>>> [ 0.000000] psci: PSCIv1.0 detected in firmware.
>>> [ 0.000000] psci: Using standard PSCI v0.2 function IDs
>>> [ 0.000000] psci: Trusted OS migration not required
>>> [ 0.000000] psci: SMC Calling Convention v1.1
>>> [ 0.000000] percpu: Embedded 24 pages/cpu s58152 r8192 d31960 u98304
>>> [ 0.000000] Detected VIPT I-cache on CPU0
>>> [ 0.000000] CPU features: detected: Spectre-v2
>>> [ 0.000000] CPU features: detected: Spectre-v4
>>> [ 0.000000] CPU features: detected: Spectre-BHB
>>> [ 0.000000] CPU features: detected: ARM erratum 858921
>>> [ 0.000000] alternatives: applying boot alternatives
>>> [ 0.000000] Kernel command line: root=UUID=a91e7bfe-4263-4e53-867d-7824e7c6a992 rw rootfstype=ext4 console=ttyS0,921600 no_console_suspend earlycon=ttyS0,0xfe078000 khadas_board=VIM4 androidboot.selinux=permissive androidboot.0
>>> [ 0.000000] Unknown kernel command line parameters "khadas_board=VIM4", will be passed to user space.
>>> [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
>>> [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
>>> [ 0.000000] Fallback order for Node 0: 0
>>> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 901152
>>> [ 0.000000] Policy zone: DMA
>>> [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
>>> [ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
>>> [ 0.000000] software IO TLB: area num 8.
>>> [ 0.000000] software IO TLB: SWIOTLB bounce buffer size roundup to 4MB
>>> [ 0.000000] software IO TLB: mapped [mem 0x00000000d8e00000-0x00000000d9200000] (4MB)
>>> [ 0.000000] Memory: 3445944K/3661824K available (16896K kernel code, 4426K rwdata, 9184K rodata, 9728K init, 611K bss, 183112K reserved, 32768K cma-reserved)
>>> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
>>> [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
>>> [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
>>> [ 0.000000] Trampoline variant of Tasks RCU enabled.
>>> [ 0.000000] Tracing variant of Tasks RCU enabled.
>>> [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
>>> [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
>>> [ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
>>> [ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
>>> [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
>>> [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
>>> [ 0.000000] Root IRQ handler: gic_handle_irq
>>> [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
>>> [ 0.000000] arch_timer: Enabling local workaround for ARM erratum 858921
>>> [ 0.000000] arch_timer: CPU0: Trapping CNTVCT access
>>> [ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
>>> [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
>>> [ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
>>> [ 0.000210] Console: colour dummy device 80x25
>>> [ 0.000253] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
>>> [ 0.000261] pid_max: default: 32768 minimum: 301
>>> [ 0.000300] LSM: initializing lsm=capability
>>> [ 0.000358] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
>>> [ 0.000371] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
>>> [ 0.000920] cacheinfo: Unable to detect cache hierarchy for CPU 0
>>> [ 0.001389] rcu: Hierarchical SRCU implementation.
>>> [ 0.001391] rcu: Max phase no-delay instances is 1000.
>>> [ 0.001834] EFI services will not be available.
>>> [ 0.001999] smp: Bringing up secondary CPUs ...
>>> [ 0.002408] CPU features: detected: ARM erratum 845719
>>> [ 0.002426] Detected VIPT I-cache on CPU1
>>> [ 0.002516] CPU1: Booted secondary processor 0x0000000100 [0x410fd034]
>>> [ 0.003007] Detected VIPT I-cache on CPU2
>>> [ 0.003054] CPU2: Booted secondary processor 0x0000000101 [0x410fd034]
>>> [ 0.003497] Detected VIPT I-cache on CPU3
>>> [ 0.003546] CPU3: Booted secondary processor 0x0000000102 [0x410fd034]
>>> [ 0.003988] Detected VIPT I-cache on CPU4
>>> [ 0.004038] CPU4: Booted secondary processor 0x0000000103 [0x410fd034]
>>> [ 0.004472] Detected VIPT I-cache on CPU5
>>> [ 0.004509] arch_timer: Enabling local workaround for ARM erratum 858921
>>> [ 0.004519] arch_timer: CPU5: Trapping CNTVCT access
>>> [ 0.004527] CPU5: Booted secondary processor 0x0000000001 [0x410fd092]
>>> [ 0.004915] Detected VIPT I-cache on CPU6
>>> [ 0.004940] arch_timer: Enabling local workaround for ARM erratum 858921
>>> [ 0.004946] arch_timer: CPU6: Trapping CNTVCT access
>>> [ 0.004951] CPU6: Booted secondary processor 0x0000000002 [0x410fd092]
>>> [ 0.005333] Detected VIPT I-cache on CPU7
>>> [ 0.005358] arch_timer: Enabling local workaround for ARM erratum 858921
>>> [ 0.005364] arch_timer: CPU7: Trapping CNTVCT access
>>> [ 0.005369] CPU7: Booted secondary processor 0x0000000003 [0x410fd092]
>>> [ 0.005414] smp: Brought up 1 node, 8 CPUs
>>> [ 0.005419] SMP: Total of 8 processors activated.
>>> [ 0.005421] CPU: All CPU(s) started at EL2
>>> [ 0.005434] CPU features: detected: 32-bit EL0 Support
>>> [ 0.005437] CPU features: detected: 32-bit EL1 Support
>>> [ 0.005440] CPU features: detected: CRC32 instructions
>>> [ 0.005485] alternatives: applying system-wide alternatives
>>> [ 0.006730] devtmpfs: initialized
>>> [ 0.008534] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
>>> [ 0.008545] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
>>> [ 0.008989] pinctrl core: initialized pinctrl subsystem
>>> [ 0.009581] DMI not present or invalid.
>>> [ 0.011290] NET: Registered PF_NETLINK/PF_ROUTE protocol family
>>> [ 0.011944] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
>>> [ 0.012293] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
>>> [ 0.012711] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
>>> [ 0.012832] audit: initializing netlink subsys (disabled)
>>> [ 0.013075] audit: type=2000 audit(0.012:1): state=initialized audit_enabled=0 res=1
>>> [ 0.013508] thermal_sys: Registered thermal governor 'step_wise'
>>> [ 0.013512] thermal_sys: Registered thermal governor 'power_allocator'
>>> [ 0.013557] cpuidle: using governor menu
>>> [ 0.013675] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
>>> [ 0.013784] ASID allocator initialised with 65536 entries
>>> [ 0.014630] Serial: AMBA PL011 UART driver
>>> [ 0.017553] Modules: 22496 pages in range for non-PLT usage
>>> [ 0.017556] Modules: 514016 pages in range for PLT usage
>>> [ 0.017980] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
>>> [ 0.017984] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
>>> [ 0.017988] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
>>> [ 0.017990] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
>>> [ 0.017993] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
>>> [ 0.017995] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
>>> [ 0.017997] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
>>> [ 0.018000] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
>>> [ 0.018247] Demotion targets for Node 0: null
>>> [ 0.018884] ACPI: Interpreter disabled.
>>> [ 0.019584] iommu: Default domain type: Translated
>>> [ 0.019587] iommu: DMA domain TLB invalidation policy: strict mode
>>> [ 0.019979] SCSI subsystem initialized
>>> [ 0.020174] usbcore: registered new interface driver usbfs
>>> [ 0.020187] usbcore: registered new interface driver hub
>>> [ 0.020200] usbcore: registered new device driver usb
>>> [ 0.020434] pps_core: LinuxPPS API ver. 1 registered
>>> [ 0.020437] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>>> [ 0.020443] PTP clock support registered
>>> [ 0.020487] EDAC MC: Ver: 3.0.0
>>> [ 0.020717] scmi_core: SCMI protocol bus registered
>>> [ 0.021039] FPGA manager framework
>>> [ 0.021076] Advanced Linux Sound Architecture Driver Initialized.
>>> [ 0.021612] vgaarb: loaded
>>> [ 0.021857] clocksource: Switched to clocksource arch_sys_counter
>>> [ 0.021967] VFS: Disk quotas dquot_6.6.0
>>> [ 0.021984] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>>> [ 0.022062] pnp: PnP ACPI: disabled
>>> [ 0.026651] NET: Registered PF_INET protocol family
>>> [ 0.026781] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
>>> [ 0.028598] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
>>> [ 0.028615] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
>>> [ 0.028622] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
>>> [ 0.028750] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
>>> [ 0.029019] TCP: Hash tables configured (established 32768 bind 32768)
>>> [ 0.029096] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
>>> [ 0.029124] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
>>> [ 0.029225] NET: Registered PF_UNIX/PF_LOCAL protocol family
>>> [ 0.029506] RPC: Registered named UNIX socket transport module.
>>> [ 0.029510] RPC: Registered udp transport module.
>>> [ 0.029512] RPC: Registered tcp transport module.
>>> [ 0.029513] RPC: Registered tcp-with-tls transport module.
>>> [ 0.029515] RPC: Registered tcp NFSv4.1 backchannel transport module.
>>> [ 0.029524] PCI: CLS 0 bytes, default 64
>>> [ 0.029649] Unpacking initramfs...
>>> [ 0.033933] kvm [1]: IPA Size Limit: 40 bits
>>> [ 0.034713] kvm [1]: Hyp mode initialized successfully
>>> [ 0.035476] Initialise system trusted keyrings
>>> [ 0.035582] workingset: timestamp_bits=42 max_order=20 bucket_order=0
>>> [ 0.035747] squashfs: version 4.0 (2009/01/31) Phillip Lougher
>>> [ 0.035906] NFS: Registering the id_resolver key type
>>> [ 0.035919] Key type id_resolver registered
>>> [ 0.035922] Key type id_legacy registered
>>> [ 0.035933] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
>>> [ 0.035935] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
>>> [ 0.036031] 9p: Installing v9fs 9p2000 file system support
>>> [ 0.062587] Key type asymmetric registered
>>> [ 0.062596] Asymmetric key parser 'x509' registered
>>> [ 0.062657] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
>>> [ 0.062661] io scheduler mq-deadline registered
>>> [ 0.062664] io scheduler kyber registered
>>> [ 0.062688] io scheduler bfq registered
>>> [ 0.063318] irq_meson_gpio: 157 to 12 gpio interrupt mux initialized
>>> [ 0.068061] EINJ: ACPI disabled.
>>> [ 0.072570] amlogic_t7_pll_probe
>>> [ 0.072855] amlogic_t7_pll_probe ret 0
>>> [ 0.072943] amlogic_a1_periphs_probe
>>> [ 0.078155] amlogic_a1_periphs_probe ret 0
>>> [ 0.084876] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
>>> [ 0.086691] fe078000.serial: ttyS0 at MMIO 0xfe078000 (irq = 14, base_baud = 1500000) is a meson_uart
>>> [ 0.086710] printk: legacy console [ttyS0] enabled
>>> [ 0.229167] sysfs: cannot create duplicate filename '/class/tty/ttyS0'
>>> [ 0.229669] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 6.8.0-09793-gda876e5b54b3-dirty #15
>>> [ 0.230684] Hardware name: Khadas vim4 (DT)
>>> [ 0.231205] Call trace:
>>> [ 0.231509] dump_backtrace+0x94/0xec
>>> [ 0.231963] show_stack+0x18/0x24
>>> [ 0.232374] dump_stack_lvl+0x78/0x90
>>> [ 0.232829] dump_stack+0x18/0x24
>>> [ 0.233241] sysfs_warn_dup+0x64/0x80
>>> [ 0.233696] sysfs_do_create_link_sd+0xf0/0xf8
>>> [ 0.234248] sysfs_create_link+0x20/0x40
>>> [ 0.234736] device_add+0x27c/0x77c
>>> [ 0.235169] device_register+0x20/0x30
>>> [ 0.235635] tty_register_device_attr+0xfc/0x240
>>> [ 0.236209] tty_port_register_device_attr_serdev+0x8c/0xac
>>> [ 0.236902] serial_core_register_port+0x318/0x658
>>> [ 0.237498] serial_ctrl_register_port+0x10/0x1c
>>> [ 0.238072] uart_add_one_port+0x10/0x1c
>>> [ 0.238560] meson_uart_probe+0x2c0/0x3b4
>>> [ 0.239058] platform_probe+0x68/0xd8
>>> [ 0.239513] really_probe+0x148/0x2b4
>>> [ 0.239968] __driver_probe_device+0x78/0x12c
>>> [ 0.240510] driver_probe_device+0xdc/0x160
>>> [ 0.241030] __driver_attach+0x94/0x19c
>>> [ 0.241507] bus_for_each_dev+0x74/0xd4
>>> [ 0.241983] driver_attach+0x24/0x30
>>> [ 0.242428] bus_add_driver+0xe4/0x1e8
>>> [ 0.242893] driver_register+0x60/0x128
>>> [ 0.243370] __platform_driver_register+0x28/0x34
>>> [ 0.243955] meson_uart_platform_driver_init+0x1c/0x28
>>> [ 0.244594] do_one_initcall+0x6c/0x1b0
>>> [ 0.245071] kernel_init_freeable+0x1cc/0x294
>>> [ 0.245613] kernel_init+0x20/0x1dc
>>> [ 0.246046] ret_from_fork+0x10/0x20
>>> [ 0.246555] meson_uart fe078000.serial: Cannot register tty device on line 0
>>> [ 0.247729] msm_serial: driver initialized
>>> [ 0.248150] SuperH (H)SCI(F) driver initialized
>>> [ 0.248544] STM32 USART driver initialized
>>> [ 0.263927] loop: module loaded
>>> [ 0.264952] megasas: 07.727.03.00-rc1
>>> [ 0.271065] tun: Universal TUN/TAP device driver, 1.6
>>> [ 0.271824] thunder_xcv, ver 1.0
>>> [ 0.271878] thunder_bgx, ver 1.0
>>> [ 0.271956] nicpf, ver 1.0
>>> [ 0.273230] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
>>> [ 0.273437] hns3: Copyright (c) 2017 Huawei Corporation.
>>> [ 0.274148] hclge is initializing
>>> [ 0.274541] e1000: Intel(R) PRO/1000 Network Driver
>>> [ 0.275116] e1000: Copyright (c) 1999-2006 Intel Corporation.
>>> [ 0.275860] e1000e: Intel(R) PRO/1000 Network Driver
>>> [ 0.276449] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
>>> [ 0.277209] igb: Intel(R) Gigabit Ethernet Network Driver
>>> [ 0.277867] igb: Copyright (c) 2007-2014 Intel Corporation.
>>> [ 0.278576] igbvf: Intel(R) Gigabit Virtual Function Network Driver
>>> [ 0.279330] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
>>> [ 0.280319] sky2: driver version 1.30
>>> [ 0.281597] VFIO - User Level meta-driver version: 0.3
>>> [ 0.283859] usbcore: registered new interface driver usb-storage
>>> [ 0.286328] i2c_dev: i2c /dev entries driver
>>> [ 0.292404] sdhci: Secure Digital Host Controller Interface driver
>>> [ 0.292481] sdhci: Copyright(c) Pierre Ossman
>>> [ 0.293577] Synopsys Designware Multimedia Card Interface Driver
>>> [ 0.294572] sdhci-pltfm: SDHCI platform and OF driver helper
>>> [ 0.296259] ledtrig-cpu: registered to indicate activity on CPUs
>>> [ 0.298966] meson-sm: secure-monitor enabled
>>> [ 0.299963] usbcore: registered new interface driver usbhid
>>> [ 0.299997] usbhid: USB HID core driver
>>> [ 0.306803] NET: Registered PF_PACKET protocol family
>>> [ 0.306919] 9pnet: Installing 9P2000 support
>>> [ 0.307331] Key type dns_resolver registered
>>> [ 0.318926] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
>>> [ 0.319462] registered taskstats version 1
>>> [ 0.319968] Loading compiled-in X.509 certificates
>>> [ 0.362771] clk: Disabling unused clocks
>>> [ 0.363100] PM: genpd: Disabling unused power domains
>>> [ 0.363383] ALSA device list:
>>> [ 0.363580] No soundcards found.
>>> [ 0.368194] meson-gx-mmc fe08a000.sd: Got CD GPIO
>>> [ 0.368524] SError Interrupt on CPU6, code 0x00000000bf000002 -- SError
>>> [ 0.368531] CPU: 6 PID: 87 Comm: kworker/u32:3 Not tainted 6.8.0-09793-gda876e5b54b3-dirty #15
>>> [ 0.368537] Hardware name: Khadas vim4 (DT)
>>> [ 0.368540] Workqueue: async async_run_entry_fn
>>> [ 0.368552] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
>>> [ 0.368556] pc : clk_mux_val_to_index+0x0/0xc0
>>> [ 0.368565] lr : clk_mux_get_parent+0x4c/0x84
>>> [ 0.368571] sp : ffff800082efba10
>>> [ 0.368572] x29: ffff800082efba10 x28: ffff8000823279c0 x27: ffff800082327000
>>> [ 0.368578] x26: ffff000004c361c0 x25: 0000000000000000 x24: 0000000000000002
>>> [ 0.368584] x23: ffff000003f1d300 x22: ffff000003f1d2a0 x21: ffff000004c37280
>>> [ 0.368589] x20: ffff000004c36ec0 x19: ffff000004bba800 x18: 0000000000000020
>>> [ 0.368594] x17: ffff000000022000 x16: 0000000000000003 x15: ffffffffffffffff
>>> [ 0.368599] x14: ffffffffffffffff x13: 0078756d2364732e x12: 3030306138306566
>>> [ 0.368604] x11: 7f7f7f7f7f7f7f7f x10: ffff7fff83438910 x9 : 0000000000000005
>>> [ 0.368609] x8 : 0101010101010101 x7 : 0000000000000000 x6 : 05114367045e5359
>>> [ 0.368613] x5 : 0000000000000006 x4 : 0000000000000000 x3 : 0000000000000000
>>> [ 0.368618] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000004c36ec0
>>> [ 0.368624] Kernel panic - not syncing: Asynchronous SError Interrupt
>>> [ 0.368626] CPU: 6 PID: 87 Comm: kworker/u32:3 Not tainted 6.8.0-09793-gda876e5b54b3-dirty #15
>>> [ 0.368630] Hardware name: Khadas vim4 (DT)
>>> [ 0.368631] Workqueue: async async_run_entry_fn
>>> [ 0.368635] Call trace:
>>> [ 0.368637] dump_backtrace+0x94/0xec
>>> [ 0.368644] show_stack+0x18/0x24
>>> [ 0.368649] dump_stack_lvl+0x38/0x90
>>> [ 0.368656] dump_stack+0x18/0x24
>>> [ 0.368661] panic+0x388/0x3c8
>>> [ 0.368666] nmi_panic+0x48/0x94
>>> [ 0.368670] arm64_serror_panic+0x6c/0x78
>>> [ 0.368674] do_serror+0x3c/0x78
>>> [ 0.368677] el1h_64_error_handler+0x30/0x48
>>> [ 0.368681] el1h_64_error+0x64/0x68
>>> [ 0.368684] clk_mux_val_to_index+0x0/0xc0
>>> [ 0.368689] __clk_register+0x440/0x82c
>>> [ 0.368693] devm_clk_register+0x5c/0xbc
>>> [ 0.368697] meson_mmc_clk_init+0x11c/0x2a8
>>> [ 0.368702] meson_mmc_probe+0x18c/0x3c0
>>> [ 0.368705] platform_probe+0x68/0xd8
>>> [ 0.368711] really_probe+0x148/0x2b4
>>> [ 0.368714] __driver_probe_device+0x78/0x12c
>>> [ 0.368718] driver_probe_device+0xdc/0x160
>>> [ 0.368721] __device_attach_driver+0xb8/0x134
>>> [ 0.368724] bus_for_each_drv+0x84/0xe0
>>> [ 0.368727] __device_attach_async_helper+0xac/0xd0
>>> [ 0.368730] async_run_entry_fn+0x34/0xe0
>>> [ 0.368734] process_one_work+0x150/0x294
>>> [ 0.368740] worker_thread+0x304/0x408
>>> [ 0.368744] kthread+0x118/0x11c
>>> [ 0.368748] ret_from_fork+0x10/0x20
>>> [ 0.368753] SMP: stopping secondary CPUs
>>> [ 0.368760] Kernel Offset: disabled
>>> [ 0.368761] CPU features: 0x0,00000060,d0080000,0200421b
>>> [ 0.368765] Memory Limit: none
>>> [ 0.400328] ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---
>>>
>>>
>>> --
>>> 2.44.0
>>>
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^ permalink raw reply
* RE: [PATCH v2] arm64: Fix double TCR_T0SZ_OFFSET shift
From: Seongsu Park @ 2024-04-08 2:19 UTC (permalink / raw)
To: 'Mark Rutland'
Cc: will, catalin.marinas, ardb, linux-arm-kernel, linux-kernel,
'Leem ChaeHoon', 'Gyeonggeon Choi',
'Soomin Cho', 'DaeRo Lee', 'kmasta'
In-Reply-To: <Zg0pDYADt1YnlQaj@FVFF77S0Q05N>
> On Wed, Apr 03, 2024 at 11:42:36AM +0900, Seongsu Park wrote:
> > We have already shifted the value of t0sz in TCR_T0SZ by
TCR_T0SZ_OFFSET.
> > So, the TCR_T0SZ_OFFSET shift here should be removed.
>
> Can we please write a better commit message?
>
> This doesn't explain:
>
> * Where we have already shifted the value of t0sz, nor why it makes sense
> to do
> that there.
>
> * That the value of TCR_T0SZ_OFFSET is 0, and hence shifting this
> repeatedly is
> beningn, and this patch is a cleanup rather than a fix.
>
> Mark.
Thank you for feedback. I'll send v3 patch.
In v3, We will upgrade the commit message, and add the cpu_set_tcr_t0sz
macro.
Please check v3!
>
> > Co-developed-by: Leem ChaeHoon <infinite.run@gmail.com>
> > Signed-off-by: Leem ChaeHoon <infinite.run@gmail.com>
> > Co-developed-by: Gyeonggeon Choi <gychoi@student.42seoul.kr>
> > Signed-off-by: Gyeonggeon Choi <gychoi@student.42seoul.kr>
> > Co-developed-by: Soomin Cho <to.soomin@gmail.com>
> > Signed-off-by: Soomin Cho <to.soomin@gmail.com>
> > Co-developed-by: DaeRo Lee <skseofh@gmail.com>
> > Signed-off-by: DaeRo Lee <skseofh@gmail.com>
> > Co-developed-by: kmasta <kmasta.study@gmail.com>
> > Signed-off-by: kmasta <kmasta.study@gmail.com>
> > Signed-off-by: Seongsu Park <sgsu.park@samsung.com>
> > ---
> >
> > Changes in v2:
> > - Condition is updated
> >
> > ---
> > arch/arm64/include/asm/mmu_context.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/include/asm/mmu_context.h
> > b/arch/arm64/include/asm/mmu_context.h
> > index c768d16b81a4..bd19f4c758b7 100644
> > --- a/arch/arm64/include/asm/mmu_context.h
> > +++ b/arch/arm64/include/asm/mmu_context.h
> > @@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned
> > long t0sz) {
> > unsigned long tcr = read_sysreg(tcr_el1);
> >
> > - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
> > + if ((tcr & TCR_T0SZ_MASK) == t0sz)
> > return;
> >
> > tcr &= ~TCR_T0SZ_MASK;
> > - tcr |= t0sz << TCR_T0SZ_OFFSET;
> > + tcr |= t0sz;
> > write_sysreg(tcr, tcr_el1);
> > isb();
> > }
> > --
> > 2.34.1
> >
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^ permalink raw reply
* Re: [PATCH V17 0/9] arm64/perf: Enable branch stack sampling
From: Anshuman Khandual @ 2024-04-08 2:26 UTC (permalink / raw)
To: Adam Young, linux-arm-kernel
In-Reply-To: <64c01f0d-7206-4240-8dd6-5690fe310a76@younglogic.com>
>
> Will this apply on 6.8? We have been chasing getting this tested, and are a revision behind you.
It might require some rebasing though - especially in the KVM code.
>
> We are just testing on 6.8, and the fact that we don't have one that works on stable revision has been one
>
> of the reasons we have not provided feedback.
Because there are some other changes that went in during last merge window,
hence will suggest to test this series on the latest v6.9 release instead.
>
> I did get to test an early version of the patch several months ago and strictly speaking it works:
>
> I used a quicksort built unoptimized and compared it with an AutoFDO version consuming the output from BRBE. The AutoFDO version was significantly faster, so we do get some optimization.
Just wondering if AutoFDO version (with BRBE branches) was also better than
previous AutoFDO version (without BRBE branches) ? That would ascertain the
observed improvement to the BRBE branch records.
>
> What is that actual Test framework you are using to test? I would like to do an apples-to-apples comparison with this version of the patch set or the most recent one I can get to apply.
The following standard perf tools based test should be a good start unless
you would like to hand craft some workloads with specific branch types etc
#perf test -vv branch
>
>
>
> On 4/4/24 22:46, Anshuman Khandual wrote:
>> This series enables perf branch stack sampling support on arm64 platform
>> via a new arch feature called Branch Record Buffer Extension (BRBE). All
>> the relevant register definitions could be accessed here.
>>
>> https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers
>>
>> This series applies on 6.9-rc2.
>>
>> Also this series is being hosted below for quick access, review and test.
>>
>> https://git.gitlab.arm.com/linux-arm/linux-anshuman.git (brbe_v17)
>>
>> There are still some open questions regarding handling multiple perf events
>> with different privilege branch filters getting on the same PMU, supporting
>> guest branch stack tracing from the host etc. Finally also looking for some
>> suggestions regarding supporting BRBE inside the guest. The series has been
>> re-organized completely as suggested earlier.
>>
>> - Anshuman
>>
>> ========== Perf Branch Stack Sampling Support (arm64 platforms) ===========
>>
>> Currently arm64 platform does not support perf branch stack sampling. Hence
>> any event requesting for branch stack records i.e PERF_SAMPLE_BRANCH_STACK
>> marked in event->attr.sample_type, will be rejected in armpmu_event_init().
>>
>> static int armpmu_event_init(struct perf_event *event)
>> {
>> ........
>> /* does not support taken branch sampling */
>> if (has_branch_stack(event))
>> return -EOPNOTSUPP;
>> ........
>> }
>>
>> $perf record -j any,u,k ls
>> Error:
>> cycles:P: PMU Hardware or event type doesn't support branch stack sampling.
>>
>> -------------------- CONFIG_ARM64_BRBE and FEAT_BRBE ----------------------
>>
>> After this series, perf branch stack sampling feature gets enabled on arm64
>> platforms where FEAT_BRBE HW feature is supported, and CONFIG_ARM64_BRBE is
>> also selected during build. Let's observe all all possible scenarios here.
>>
>> 1. Feature not built (!CONFIG_ARM64_BRBE):
>>
>> Falls back to the current behaviour i.e event gets rejected.
>>
>> 2. Feature built but HW not supported (CONFIG_ARM64_BRBE && !FEAT_BRBE):
>>
>> Falls back to the current behaviour i.e event gets rejected.
>>
>> 3. Feature built and HW supported (CONFIG_ARM64_BRBE && FEAT_BRBE):
>>
>> Platform supports branch stack sampling requests. Let's observe through a
>> simple example here.
>>
>> $perf record -j any_call,u,k,save_type ls
>>
>> [Please refer perf-record man pages for all possible branch filter options]
>>
>> $perf report
>> -------------------------- Snip ----------------------
>> # Overhead Command Source Shared Object Source Symbol Target Symbol Basic Block Cycles
>> # ........ ....... .................... ............................................ ............................................ ..................
>> #
>> 3.52% ls [kernel.kallsyms] [k] sched_clock_noinstr [k] arch_counter_get_cntpct 16
>> 3.52% ls [kernel.kallsyms] [k] sched_clock [k] sched_clock_noinstr 9
>> 1.85% ls [kernel.kallsyms] [k] sched_clock_cpu [k] sched_clock 5
>> 1.80% ls [kernel.kallsyms] [k] irqtime_account_irq [k] sched_clock_cpu 20
>> 1.58% ls [kernel.kallsyms] [k] gic_handle_irq [k] generic_handle_domain_irq 19
>> 1.58% ls [kernel.kallsyms] [k] call_on_irq_stack [k] gic_handle_irq 9
>> 1.58% ls [kernel.kallsyms] [k] do_interrupt_handler [k] call_on_irq_stack 23
>> 1.58% ls [kernel.kallsyms] [k] generic_handle_domain_irq [k] __irq_resolve_mapping 6
>> 1.58% ls [kernel.kallsyms] [k] __irq_resolve_mapping [k] __rcu_read_lock 10
>> -------------------------- Snip ----------------------
>>
>> $perf report -D | grep cycles
>> -------------------------- Snip ----------------------
>> ..... 1: ffff800080dd3334 -> ffff800080dd759c 39 cycles P 0 IND_CALL
>> ..... 2: ffff800080ffaea0 -> ffff800080ffb688 16 cycles P 0 IND_CALL
>> ..... 3: ffff800080139918 -> ffff800080ffae64 9 cycles P 0 CALL
>> ..... 4: ffff800080dd3324 -> ffff8000801398f8 7 cycles P 0 CALL
>> ..... 5: ffff8000800f8548 -> ffff800080dd330c 21 cycles P 0 IND_CALL
>> ..... 6: ffff8000800f864c -> ffff8000800f84ec 6 cycles P 0 CALL
>> ..... 7: ffff8000800f86dc -> ffff8000800f8638 11 cycles P 0 CALL
>> ..... 8: ffff8000800f86d4 -> ffff800081008630 16 cycles P 0 CALL
>> -------------------------- Snip ----------------------
>>
>> perf script and other tooling can also be applied on the captured perf.data
>> Similarly branch stack sampling records can be collected via direct system
>> call i.e perf_event_open() method after setting 'struct perf_event_attr' as
>> required.
>>
>> event->attr.sample_type |= PERF_SAMPLE_BRANCH_STACK
>> event->attr.branch_sample_type |= PERF_SAMPLE_BRANCH_<FILTER_1> |
>> PERF_SAMPLE_BRANCH_<FILTER_2> |
>> PERF_SAMPLE_BRANCH_<FILTER_3> |
>> ...............................
>>
>> But all branch filters might not be supported on the platform.
>>
>> ----------------------- BRBE Branch Filters Support -----------------------
>>
>> - Following branch filters are supported on arm64.
>>
>> PERF_SAMPLE_BRANCH_USER /* Branch privilege filters */
>> PERF_SAMPLE_BRANCH_KERNEL
>> PERF_SAMPLE_BRANCH_HV
>>
>> PERF_SAMPLE_BRANCH_ANY /* Branch type filters */
>> PERF_SAMPLE_BRANCH_ANY_CALL
>> PERF_SAMPLE_BRANCH_ANY_RETURN
>> PERF_SAMPLE_BRANCH_IND_CALL
>> PERF_SAMPLE_BRANCH_COND
>> PERF_SAMPLE_BRANCH_IND_JUMP
>> PERF_SAMPLE_BRANCH_CALL
>>
>> PERF_SAMPLE_BRANCH_NO_FLAGS /* Branch record flags */
>> PERF_SAMPLE_BRANCH_NO_CYCLES
>> PERF_SAMPLE_BRANCH_TYPE_SAVE
>> PERF_SAMPLE_BRANCH_HW_INDEX
>> PERF_SAMPLE_BRANCH_PRIV_SAVE
>>
>> - Following branch filters are not supported on arm64.
>>
>> PERF_SAMPLE_BRANCH_ABORT_TX
>> PERF_SAMPLE_BRANCH_IN_TX
>> PERF_SAMPLE_BRANCH_NO_TX
>> PERF_SAMPLE_BRANCH_CALL_STACK
>>
>> Events requesting above non-supported branch filters get rejected.
>>
>> ------------------ Possible 'branch_sample_type' Mismatch -----------------
>>
>> Branch stack sampling attributes 'event->attr.branch_sample_type' generally
>> remain the same for all the events during a perf record session.
>>
>> $perf record -e <event_1> -e <event_2> -j <branch_filters> [workload]
>>
>> event_1->attr.branch_sample_type == event_2->attr.branch_sample_type
>>
>> This 'branch_sample_type' is used to configure the BRBE hardware, when both
>> events i.e <event_1> and <event_2> get scheduled on a given PMU. But during
>> PMU HW event's privilege filter inheritance, 'branch_sample_type' does not
>> remain the same for all events. Let's consider the following example
>>
>> $perf record -e cycles:u -e instructions:k -j any,save_type ls
>>
>> cycles->attr.branch_sample_type != instructions->attr.branch_sample_type
>>
>> Because cycles event inherits PERF_SAMPLE_BRANCH_USER and instruction event
>> inherits PERF_SAMPLE_BRANCH_KERNEL. The proposed solution here configures
>> BRBE hardware with 'branch_sample_type' from last event to be added in the
>> PMU and hence captured branch records only get passed on to matching events
>> during a PMU interrupt.
>>
>> static int
>> armpmu_add(struct perf_event *event, int flags)
>> {
>> ........
>> if (has_branch_stack(event)) {
>> /*
>> * Reset branch records buffer if a new task event gets
>> * scheduled on a PMU which might have existing records.
>> * Otherwise older branch records present in the buffer
>> * might leak into the new task event.
>> */
>> if (event->ctx->task && hw_events->brbe_context != event->ctx) {
>> hw_events->brbe_context = event->ctx;
>> if (armpmu->branch_reset)
>> armpmu->branch_reset();
>> }
>> hw_events->brbe_users++;
>> Here -------> hw_events->brbe_sample_type = event->attr.branch_sample_type;
>> }
>> ........
>> }
>>
>> Instead of overriding existing 'branch_sample_type', both could be merged.
>>
>> --------------------------- Virtualisation support ------------------------
>>
>> - Branch stack sampling is not currently supported inside the guest (TODO)
>>
>> - FEAT_BRBE advertised as absent via clearing ID_AA64DFR0_EL1.BRBE
>> - Future support in guest requires emulating FEAT_BRBE
>>
>> - Branch stack sampling the guest is not supported in the host (TODO)
>>
>> - Tracing the guest with event->attr.exclude_guest = 0
>> - There are multiple challenges involved regarding mixing events
>> with mismatched branch_sample_type and exclude_guest and passing
>> on captured BRBE records to intended events during PMU interrupt
>>
>> - Guest access for BRBE registers and instructions has been blocked
>>
>> - BRBE state save is not required for VHE host (EL2) guest (EL1) transition
>>
>> - BRBE state is saved for NVHE host (EL1) guest (EL1) transition
>>
>> -------------------------------- Testing ---------------------------------
>>
>> - Cross compiled for both arm64 and arm32 platforms
>> - Passes all branch tests with 'perf test branch' on arm64
>>
>> -------------------------------- Questions -------------------------------
>>
>> - Instead of configuring the BRBE HW with branch_sample_type from the last
>> event to be added on the PMU as proposed, could those be merged together
>> e.g all privilege requests ORed, to form a common BRBE configuration and
>> all events get branch records after a PMU interrupt ?
>>
>> Changes in V17:
>>
>> - Added back Reviewed-by tags from Mark Brown
>> - Updated the commit message regarding the field BRBINFx_EL1_TYPE_IMPDEF_TRAP_EL3
>> - Added leading 0s for all values as BRBIDR0_EL1.NUMREC is a 8 bit field
>> - Added leading 0s for all values as BRBFCR_EL1.BANK is a 2 bit field
>> - Reordered BRBCR_EL1/BRBCR_EL12/BRBCR_EL2 registers as per sysreg encodings
>> - Renamed s/FIRST/BANK_0 and s/SECOND/BANK_1 in BRBFCR_EL1.BANK
>> - Renamed s/UNCOND_DIRECT/DIRECT_UNCOND in BRBINFx_EL1.TYPE
>> - Renamed s/COND_DIRECT/DIRECT_COND in BRBINFx_EL1.TYPE
>> - Dropped __SYS_BRBINF/__SYS_BRBSRC/__SYS_BRBTGT and their expansions
>> - Moved all existing BRBE registers from sysreg.h header to tools/sysreg format
>> - Updated the commit message including about sys_insn_descs[]
>> - Changed KVM to use existing SYS_BRBSRC/TGT/INF_EL1(n) format
>> - Moved the BRBE instructions into sys_insn_descs[] array
>> - ARM PMUV3 changes have been moved into the BRBE driver patch instead
>> - Moved down branch_stack_add() in armpmu_add() after event's basic checks
>> - Added new callbacks in struct arm_pmu e.g branch_stack_[init|add|del]()
>> - Renamed struct arm_pmu callback branch_reset() as branch_stack_reset()
>> - Dropped the comment in armpmu_event_init()
>> - Renamed 'pmu_hw_events' elements from 'brbe_' to more generic 'branch_'
>> - Separated out from the BRBE driver implementation patch
>> - Dropped the comment in __init_el2_brbe()
>> - Updated __init_el2_brbe() with BRBCR_EL2.MPRED requirements
>> - Updated __init_el2_brbe() with __check_hvhe() constructs
>> - Updated booting.rst regarding MPRED, MDCR_EL3 and fine grained control
>> - Dropped Documentation/arch/arm64/brbe.rst
>> - Renamed armv8pmu_branch_reset() as armv8pmu_branch_stack_reset()
>> - Separated out booting.rst and EL2 boot requirements into a new patch
>> - Dropped process_branch_aborts() completely
>> - Added an warning if transaction states get detected unexpectedly
>> - Dropped enum brbe_bank_idx from the driver
>> - Defined armv8pmu_branch_stack_init/add/del() callbacks in the driver
>> - Changed BRBE driver to use existing SYS_BRBSRC/TGT/INF_EL1(n) format
>> - Dropped isb() call sites in __debug_[save|restore]_brbe()
>> - Changed to [read|write]_sysreg_el1() accessors in __debug_[save|restore]_brbe()
>>
>> Changes in V16
>>
>> https://lore.kernel.org/all/20240125094119.2542332-1-anshuman.khandual@arm.com/
>>
>> - Updated BRBINFx_EL1.TYPE = 0b110000 as field IMPDEF_TRAP_EL3
>> - Updated BRBCR_ELx[9] as field FZPSS
>> - Updated BRBINFINJ_EL1 to use sysreg field BRBINFx_EL1
>> - Added BRB_INF_SRC_TGT_EL1 macro for corresponding BRB_[INF|SRC|TGT] expansion
>> - Renamed arm_brbe.h as arm_pmuv3_branch.h
>> - Updated perf_sample_save_brstack()'s new argument requirements with NULL
>> - Fixed typo (s/informations/information) in Documentation/arch/arm64/brbe.rst
>> - Added SPDX-License-Identifier in Documentation/arch/arm64/brbe.rst
>> - Added new PERF_SAMPLE_BRANCH_COUNTERS into BRBE_EXCLUDE_BRANCH_FILTERS
>> - Dropped BRBFCR_EL1 and BRBCR_EL1 from enum vcpu_sysreg
>> - Reverted back the KVM NVHE patch - use host_debug_state based 'brbcr_el1'
>> element and dropped the previous dependency on Jame's coresight series
>>
>> Changes in V15:
>>
>> https://lore.kernel.org/all/20231201053906.1261704-1-anshuman.khandual@arm.com/
>>
>> - Added a comment for armv8pmu_branch_probe() regarding single cpu probe
>> - Added a text in brbe.rst regarding single cpu probe
>> - Dropped runtime BRBE enable for setting DEBUG_STATE_SAVE_BRBE
>> - Dropped zero_branch_stack based zero branch records mechanism
>> - Replaced BRBFCR_EL1_DEFAULT_CONFIG with BRBFCR_EL1_CONFIG_MASK
>> - Added BRBFCR_EL1_CONFIG_MASK masking in branch_type_to_brbfcr()
>> - Moved BRBE helpers from arm_brbe.h into arm_brbe.c
>> - Moved armv8_pmu_xxx() declaration inside arm_brbe.h for arm64 (CONFIG_ARM64_BRBE)
>> - Moved armv8_pmu_xxx() stub definitions inside arm_brbe.h for arm32 (!CONFIG_ARM64_BRBE)
>> - Included arm_brbe.h header both in arm_pmuv3.c and arm_brbe.c
>> - Dropped BRBE custom pr_fmt()
>> - Dropped CONFIG_PERF_EVENTS wrapping from header entries
>> - Flush branch records when a cpu bound event follows a task bound event
>> - Dropped BRBFCR_EL1 from __debug_save_brbe()/__debug_restore_brbe()
>> - Always save the live SYS_BRBCR_EL1 in host context and then check if
>> BRBE was enabled before resetting SYS_BRBCR_EL1 for the host
>>
>> Changes in V14:
>>
>> https://lore.kernel.org/all/20231114051329.327572-1-anshuman.khandual@arm.com/
>>
>> - This series has been reorganised as suggested during V13
>> - There are just eight patches now i.e 5 enablement and 3 perf branch tests
>>
>> - Fixed brackets problem in __SYS_BRBINFO/BRBSRC/BRBTGT() macros
>> - Renamed the macro i.e s/__SYS_BRBINFO/__SYS_BRBINF/
>> - Renamed s/BRB_IALL/BRB_IALL_INSN and s/BRBE_INJ/BRB_INJ_INSN
>> - Moved BRB_IALL_INSN and SYS_BRB_INSN instructions to sysreg patch
>> - Changed E1BRE as ExBRE in sysreg fields inside BRBCR_ELx
>> - Used BRBCR_ELx for defining all BRBCR_EL1, BRBCR_EL2, and BRBCR_EL12 (new)
>>
>> - Folded the following three patches into a single patch i.e [PATCH 3/8]
>>
>> drivers: perf: arm_pmu: Add new sched_task() callback
>> arm64/perf: Add branch stack support in struct arm_pmu
>> arm64/perf: Add branch stack support in struct pmu_hw_events
>> arm64/perf: Add branch stack support in ARMV8 PMU
>> arm64/perf: Add PERF_ATTACH_TASK_DATA to events with has_branch_stack()
>>
>> - All armv8pmu_branch_xxxx() stub definitions have been moved inside
>> include/linux/perf/arm_pmuv3.h for easy access from both arm32 and arm64
>> - Added brbe_users, brbe_context and brbe_sample_type in struct pmu_hw_events
>> - Added comments for all the above new elements in struct pmu_hw_events
>> - Added branch_reset() and sched_task() callbacks
>> - Changed and optimized branch records processing during a PMU IRQ
>> - NO branch records get captured for event with mismatched brbe_sample_type
>> - Branch record context is tracked from armpmu_del() & armpmu_add()
>> - Branch record hardware is driven from armv8pmu_start() & armv8pmu_stop()
>> - Dropped NULL check for 'pmu_ctx' inside armv8pmu_sched_task()
>> - Moved down PERF_ATTACH_TASK_DATA assignment with a preceding comment
>> - In conflicting branch sample type requests, first event takes precedence
>>
>> - Folded the following five patches from V13 into a single patch i.e
>> [PATCH 4/8]
>>
>> arm64/perf: Enable branch stack events via FEAT_BRBE
>> arm64/perf: Add struct brbe_regset helper functions
>> arm64/perf: Implement branch records save on task sched out
>> arm64/perf: Implement branch records save on PMU IRQ
>>
>> - Fixed the year in copyright statement
>> - Added Documentation/arch/arm64/brbe.rst
>> - Updated Documentation/arch/arm64/booting.rst (BRBCR_EL2.CC for EL1 entry)
>> - Added __init_el2_brbe() which enables branch record cycle count support
>> - Disabled EL2 traps in __init_el2_fgt() while accessing BRBE registers and
>> executing instructions
>> - Changed CONFIG_ARM64_BRBE user visible description
>> - Fixed a typo in CONFIG_ARM64_BRBE config option description text
>> - Added BUILD_BUG_ON() co-relating BRBE_BANK_MAX_ENTRIES and MAX_BRANCH_RECORDS
>> - Dropped arm64_create_brbe_task_ctx_kmem_cache()
>> - Moved down comment for PERF_SAMPLE_BRANCH_KERNEL in branch_type_to_brbcr()
>> - Renamed BRBCR_ELx_DEFAULT_CONFIG as BRBCR_ELx_CONFIG_MASK
>> - Replaced BRBCR_ELx_DEFAULT_TS with BRBCR_ELx_TS_MASK in BRBCR_ELx_CONFIG_MASK
>> - Replaced BRBCR_ELx_E1BRE instances with BRBCR_ELx_ExBRE
>>
>> - Added BRBE specific branch stack sampling perf test patches into the series
>> - Added a patch to prevent guest accesses into BRBE registers and instructions
>> - Added a patch to save the BRBE host context in NVHE environment
>> - Updated most commit messages
>>
>> Changes in V13:
>>
>> https://lore.kernel.org/all/20230711082455.215983-1-anshuman.khandual@arm.com/
>> https://lore.kernel.org/all/20230622065351.1092893-1-anshuman.khandual@arm.com/
>>
>> - Added branch callback stubs for aarch32 pmuv3 based platforms
>> - Updated the comments for capture_brbe_regset()
>> - Deleted the comments in __read_brbe_regset()
>> - Reversed the arguments order in capture_brbe_regset() and brbe_branch_save()
>> - Fixed BRBE_BANK[0|1]_IDX_MAX indices comparison in armv8pmu_branch_read()
>> - Fixed BRBE_BANK[0|1]_IDX_MAX indices comparison in capture_brbe_regset()
>>
>> Changes in V12:
>>
>> https://lore.kernel.org/all/20230615133239.442736-1-anshuman.khandual@arm.com/
>>
>> - Replaced branch types with complete DIRECT/INDIRECT prefixes/suffixes
>> - Replaced branch types with complete INSN/ALIGN prefixes/suffixes
>> - Replaced return branch types as simple RET/ERET
>> - Replaced time field GST_PHYSICAL as GUEST_PHYSICAL
>> - Added 0 padding for BRBIDR0_EL1.NUMREC enum values
>> - Dropped helper arm_pmu_branch_stack_supported()
>> - Renamed armv8pmu_branch_valid() as armv8pmu_branch_attr_valid()
>> - Separated perf_task_ctx_cache setup from arm_pmu private allocation
>> - Collected changes to branch_records_alloc() in a single patch [5/10]
>> - Reworked and cleaned up branch_records_alloc()
>> - Reworked armv8pmu_branch_read() with new loop iterations in patch [6/10]
>> - Reworked capture_brbe_regset() with new loop iterations in patch [8/10]
>> - Updated the comment in branch_type_to_brbcr()
>> - Fixed the comment before stitch_stored_live_entries()
>> - Fixed BRBINFINJ_EL1 definition for VALID_FULL enum field
>> - Factored out helper __read_brbe_regset() from capture_brbe_regset()
>> - Dropped the helper copy_brbe_regset()
>> - Simplified stitch_stored_live_entries() with memcpy(), memmove()
>> - Reworked armv8pmu_probe_pmu() to bail out early with !probe.present
>> - Rework brbe_attributes_probe() without 'struct brbe_hw_attr'
>> - Dropped 'struct brbe_hw_attr' argument from capture_brbe_regset()
>> - Dropped 'struct brbe_hw_attr' argument from brbe_branch_save()
>> - Dropped arm_pmu->private and added arm_pmu->reg_trbidr instead
>>
>> Changes in V11:
>>
>> https://lore.kernel.org/all/20230531040428.501523-1-anshuman.khandual@arm.com/
>>
>> - Fixed the crash for per-cpu events without event->pmu_ctx->task_ctx_data
>>
>> Changes in V10:
>>
>> https://lore.kernel.org/all/20230517022410.722287-1-anshuman.khandual@arm.com/
>>
>> - Rebased the series on v6.4-rc2
>> - Moved ARMV8 PMUV3 changes inside drivers/perf/arm_pmuv3.c
>> - Moved BRBE driver changes inside drivers/perf/arm_brbe.[c|h]
>> - Moved the WARN_ON() inside the if condition in armv8pmu_handle_irq()
>>
>> Changes in V9:
>>
>> https://lore.kernel.org/all/20230315051444.1683170-1-anshuman.khandual@arm.com/
>>
>> - Fixed build problem with has_branch_stack() in arm64 header
>> - BRBINF_EL1 definition has been changed from 'Sysreg' to 'SysregFields'
>> - Renamed all BRBINF_EL1 call sites as BRBINFx_EL1
>> - Dropped static const char branch_filter_error_msg[]
>> - Implemented a positive list check for BRBE supported perf branch filters
>> - Added a comment in armv8pmu_handle_irq()
>> - Implemented per-cpu allocation for struct branch_record records
>> - Skipped looping through bank 1 if an invalid record is detected in bank 0
>> - Added comment in armv8pmu_branch_read() explaining prohibited region etc
>> - Added comment warning about erroneously marking transactions as aborted
>> - Replaced the first argument (perf_branch_entry) in capture_brbe_flags()
>> - Dropped the last argument (idx) in capture_brbe_flags()
>> - Dropped the brbcr argument from capture_brbe_flags()
>> - Used perf_sample_save_brstack() to capture branch records for perf_sample_data
>> - Added comment explaining rationale for setting BRBCR_EL1_FZP for user only traces
>> - Dropped BRBE prohibited state mechanism while in armv8pmu_branch_read()
>> - Implemented event task context based branch records save mechanism
>>
>> Changes in V8:
>>
>> https://lore.kernel.org/all/20230123125956.1350336-1-anshuman.khandual@arm.com/
>>
>> - Replaced arm_pmu->features as arm_pmu->has_branch_stack, updated its helper
>> - Added a comment and line break before arm_pmu->private element
>> - Added WARN_ON_ONCE() in helpers i.e armv8pmu_branch_[read|valid|enable|disable]()
>> - Dropped comments in armv8pmu_enable_event() and armv8pmu_disable_event()
>> - Replaced open bank encoding in BRBFCR_EL1 with SYS_FIELD_PREP()
>> - Changed brbe_hw_attr->brbe_version from 'bool' to 'int'
>> - Updated pr_warn() as pr_warn_once() with values in brbe_get_perf_[type|priv]()
>> - Replaced all pr_warn_once() as pr_debug_once() in armv8pmu_branch_valid()
>> - Added a comment in branch_type_to_brbcr() for the BRBCR_EL1 privilege settings
>> - Modified the comment related to BRBINFx_EL1.LASTFAILED in capture_brbe_flags()
>> - Modified brbe_get_perf_entry_type() as brbe_set_perf_entry_type()
>> - Renamed brbe_valid() as brbe_record_is_complete()
>> - Renamed brbe_source() as brbe_record_is_source_only()
>> - Renamed brbe_target() as brbe_record_is_target_only()
>> - Inverted checks for !brbe_record_is_[target|source]_only() for info capture
>> - Replaced 'fetch' with 'get' in all helpers that extract field value
>> - Dropped 'static int brbe_current_bank' optimization in select_brbe_bank()
>> - Dropped select_brbe_bank_index() completely, added capture_branch_entry()
>> - Process captured branch entries in two separate loops one for each BRBE bank
>> - Moved branch_records_alloc() inside armv8pmu_probe_pmu()
>> - Added a forward declaration for the helper has_branch_stack()
>> - Added new callbacks armv8pmu_private_alloc() and armv8pmu_private_free()
>> - Updated armv8pmu_probe_pmu() to allocate the private structure before SMP call
>>
>> Changes in V7:
>>
>> https://lore.kernel.org/all/20230105031039.207972-1-anshuman.khandual@arm.com/
>>
>> - Folded [PATCH 7/7] into [PATCH 3/7] which enables branch stack sampling event
>> - Defined BRBFCR_EL1_BRANCH_FILTERS, BRBCR_EL1_DEFAULT_CONFIG in the header
>> - Defined BRBFCR_EL1_DEFAULT_CONFIG in the header
>> - Updated BRBCR_EL1_DEFAULT_CONFIG with BRBCR_EL1_FZP
>> - Defined BRBCR_EL1_DEFAULT_TS in the header
>> - Updated BRBCR_EL1_DEFAULT_CONFIG with BRBCR_EL1_DEFAULT_TS
>> - Moved BRBCR_EL1_DEFAULT_CONFIG check inside branch_type_to_brbcr()
>> - Moved down BRBCR_EL1_CC, BRBCR_EL1_MPRED later in branch_type_to_brbcr()
>> - Also set BRBE in paused state in armv8pmu_branch_disable()
>> - Dropped brbe_paused(), set_brbe_paused() helpers
>> - Extracted error string via branch_filter_error_msg[] for armv8pmu_branch_valid()
>> - Replaced brbe_v1p1 with brbe_version in struct brbe_hw_attr
>> - Added valid_brbe_[cc, format, version]() helpers
>> - Split a separate brbe_attributes_probe() from armv8pmu_branch_probe()
>> - Capture event->attr.branch_sample_type earlier in armv8pmu_branch_valid()
>> - Defined enum brbe_bank_idx with possible values for BRBE bank indices
>> - Changed armpmu->hw_attr into armpmu->private
>> - Added missing space in stub definition for armv8pmu_branch_valid()
>> - Replaced both kmalloc() with kzalloc()
>> - Added BRBE_BANK_MAX_ENTRIES
>> - Updated comment for capture_brbe_flags()
>> - Updated comment for struct brbe_hw_attr
>> - Dropped space after type cast in couple of places
>> - Replaced inverse with negation for testing BRBCR_EL1_FZP in armv8pmu_branch_read()
>> - Captured cpuc->branches->branch_entries[idx] in a local variable
>> - Dropped saved_priv from armv8pmu_branch_read()
>> - Reorganize PERF_SAMPLE_BRANCH_NO_[CYCLES|NO_FLAGS] related configuration
>> - Replaced with FIELD_GET() and FIELD_PREP() wherever applicable
>> - Replaced BRBCR_EL1_TS_PHYSICAL with BRBCR_EL1_TS_VIRTUAL
>> - Moved valid_brbe_nr(), valid_brbe_cc(), valid_brbe_format(), valid_brbe_version()
>> select_brbe_bank(), select_brbe_bank_index() helpers inside the C implementation
>> - Reorganized brbe_valid_nr() and dropped the pr_warn() message
>> - Changed probe sequence in brbe_attributes_probe()
>> - Added 'brbcr' argument into capture_brbe_flags() to ascertain correct state
>> - Disable BRBE before disabling the PMU event counter
>> - Enable PERF_SAMPLE_BRANCH_HV filters when is_kernel_in_hyp_mode()
>> - Guard armv8pmu_reset() & armv8pmu_sched_task() with arm_pmu_branch_stack_supported()
>>
>> Changes in V6:
>>
>> https://lore.kernel.org/linux-arm-kernel/20221208084402.863310-1-anshuman.khandual@arm.com/
>>
>> - Restore the exception level privilege after reading the branch records
>> - Unpause the buffer after reading the branch records
>> - Decouple BRBCR_EL1_EXCEPTION/ERTN from perf event privilege level
>> - Reworked BRBE implementation and branch stack sampling support on arm pmu
>> - BRBE implementation is now part of overall ARMV8 PMU implementation
>> - BRBE implementation moved from drivers/perf/ to inside arch/arm64/kernel/
>> - CONFIG_ARM_BRBE_PMU renamed as CONFIG_ARM64_BRBE in arch/arm64/Kconfig
>> - File moved - drivers/perf/arm_pmu_brbe.c -> arch/arm64/kernel/brbe.c
>> - File moved - drivers/perf/arm_pmu_brbe.h -> arch/arm64/kernel/brbe.h
>> - BRBE name has been dropped from struct arm_pmu and struct hw_pmu_events
>> - BRBE name has been abstracted out as 'branches' in arm_pmu and hw_pmu_events
>> - BRBE name has been abstracted out as 'branches' in ARMV8 PMU implementation
>> - Added sched_task() callback into struct arm_pmu
>> - Added 'hw_attr' into struct arm_pmu encapsulating possible PMU HW attributes
>> - Dropped explicit attributes brbe_(v1p1, nr, cc, format) from struct arm_pmu
>> - Dropped brbfcr, brbcr, registers scratch area from struct hw_pmu_events
>> - Dropped brbe_users, brbe_context tracking in struct hw_pmu_events
>> - Added 'features' tracking into struct arm_pmu with ARM_PMU_BRANCH_STACK flag
>> - armpmu->hw_attr maps into 'struct brbe_hw_attr' inside BRBE implementation
>> - Set ARM_PMU_BRANCH_STACK in 'arm_pmu->features' after successful BRBE probe
>> - Added armv8pmu_branch_reset() inside armv8pmu_branch_enable()
>> - Dropped brbe_supported() as events will be rejected via ARM_PMU_BRANCH_STACK
>> - Dropped set_brbe_disabled() as well
>> - Reformated armv8pmu_branch_valid() warnings while rejecting unsupported events
>>
>> Changes in V5:
>>
>> https://lore.kernel.org/linux-arm-kernel/20221107062514.2851047-1-anshuman.khandual@arm.com/
>>
>> - Changed BRBCR_EL1.VIRTUAL from 0b1 to 0b01
>> - Changed BRBFCR_EL1.EnL into BRBFCR_EL1.EnI
>> - Changed config ARM_BRBE_PMU from 'tristate' to 'bool'
>>
>> Changes in V4:
>>
>> https://lore.kernel.org/all/20221017055713.451092-1-anshuman.khandual@arm.com/
>>
>> - Changed ../tools/sysreg declarations as suggested
>> - Set PERF_SAMPLE_BRANCH_STACK in data.sample_flags
>> - Dropped perfmon_capable() check in armpmu_event_init()
>> - s/pr_warn_once/pr_info in armpmu_event_init()
>> - Added brbe_format element into struct pmu_hw_events
>> - Changed v1p1 as brbe_v1p1 in struct pmu_hw_events
>> - Dropped pr_info() from arm64_pmu_brbe_probe(), solved LOCKDEP warning
>>
>> Changes in V3:
>>
>> https://lore.kernel.org/all/20220929075857.158358-1-anshuman.khandual@arm.com/
>>
>> - Moved brbe_stack from the stack and now dynamically allocated
>> - Return PERF_BR_PRIV_UNKNOWN instead of -1 in brbe_fetch_perf_priv()
>> - Moved BRBIDR0, BRBCR, BRBFCR registers and fields into tools/sysreg
>> - Created dummy BRBINF_EL1 field definitions in tools/sysreg
>> - Dropped ARMPMU_EVT_PRIV framework which cached perfmon_capable()
>> - Both exception and exception return branche records are now captured
>> only if the event has PERF_SAMPLE_BRANCH_KERNEL which would already
>> been checked in generic perf via perf_allow_kernel()
>>
>> Changes in V2:
>>
>> https://lore.kernel.org/all/20220908051046.465307-1-anshuman.khandual@arm.com/
>>
>> - Dropped branch sample filter helpers consolidation patch from this series
>> - Added new hw_perf_event.flags element ARMPMU_EVT_PRIV to cache perfmon_capable()
>> - Use cached perfmon_capable() while configuring BRBE branch record filters
>>
>> Changes in V1:
>>
>> https://lore.kernel.org/linux-arm-kernel/20220613100119.684673-1-anshuman.khandual@arm.com/
>>
>> - Added CONFIG_PERF_EVENTS wrapper for all branch sample filter helpers
>> - Process new perf branch types via PERF_BR_EXTEND_ABI
>>
>> Changes in RFC V2:
>>
>> https://lore.kernel.org/linux-arm-kernel/20220412115455.293119-1-anshuman.khandual@arm.com/
>>
>> - Added branch_sample_priv() while consolidating other branch sample filter helpers
>> - Changed all SYS_BRBXXXN_EL1 register definition encodings per Marc
>> - Changed the BRBE driver as per proposed BRBE related perf ABI changes (V5)
>> - Added documentation for struct arm_pmu changes, updated commit message
>> - Updated commit message for BRBE detection infrastructure patch
>> - PERF_SAMPLE_BRANCH_KERNEL gets checked during arm event init (outside the driver)
>> - Branch privilege state capture mechanism has now moved inside the driver
>>
>> Changes in RFC V1:
>>
>> https://lore.kernel.org/all/1642998653-21377-1-git-send-email-anshuman.khandual@arm.com/
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Mark Brown <broonie@kernel.org>
>> Cc: James Clark <james.clark@arm.com>
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
>> Cc: Peter Zijlstra <peterz@infradead.org>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-perf-users@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>>
>> Anshuman Khandual (6):
>> arm64/sysreg: Add BRBE registers and fields
>> KVM: arm64: Explicitly handle BRBE traps as UNDEFINED
>> drivers: perf: arm_pmu: Add infrastructure for branch stack sampling
>> arm64/boot: Enable EL2 requirements for BRBE
>> drivers: perf: arm_pmuv3: Enable branch stack sampling via FEAT_BRBE
>> KVM: arm64: nvhe: Disable branch generation in nVHE guests
>>
>> James Clark (3):
>> perf: test: Speed up running brstack test on an Arm model
>> perf: test: Remove empty lines from branch filter test output
>> perf: test: Extend branch stack sampling test for Arm64 BRBE
>>
>> Documentation/arch/arm64/booting.rst | 26 +
>> arch/arm64/include/asm/el2_setup.h | 90 ++-
>> arch/arm64/include/asm/kvm_host.h | 5 +-
>> arch/arm64/include/asm/sysreg.h | 17 +-
>> arch/arm64/kvm/debug.c | 5 +
>> arch/arm64/kvm/hyp/nvhe/debug-sr.c | 31 +
>> arch/arm64/kvm/sys_regs.c | 56 ++
>> arch/arm64/tools/sysreg | 131 ++++
>> drivers/perf/Kconfig | 11 +
>> drivers/perf/Makefile | 1 +
>> drivers/perf/arm_brbe.c | 968 +++++++++++++++++++++++++
>> drivers/perf/arm_pmu.c | 25 +-
>> drivers/perf/arm_pmuv3.c | 146 +++-
>> drivers/perf/arm_pmuv3_branch.h | 73 ++
>> include/linux/perf/arm_pmu.h | 37 +-
>> tools/perf/tests/builtin-test.c | 1 +
>> tools/perf/tests/shell/test_brstack.sh | 57 +-
>> tools/perf/tests/tests.h | 1 +
>> tools/perf/tests/workloads/Build | 2 +
>> tools/perf/tests/workloads/traploop.c | 39 +
>> 20 files changed, 1696 insertions(+), 26 deletions(-)
>> create mode 100644 drivers/perf/arm_brbe.c
>> create mode 100644 drivers/perf/arm_pmuv3_branch.h
>> create mode 100644 tools/perf/tests/workloads/traploop.c
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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* Re: [RFC PATCH v2 1/5] clk: meson: axg: move reset controller's code to separate module
From: Stephen Boyd @ 2024-04-08 2:39 UTC (permalink / raw)
To: Jan Dakinevich, Jerome Brunet, Philipp Zabel
Cc: Neil Armstrong, Jerome Brunet, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Martin Blumenstingl, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <1j7chfiz8e.fsf@starbuckisacylon.baylibre.com>
Quoting Jerome Brunet (2024-04-02 07:52:38)
>
> On Thu 28 Mar 2024 at 04:08, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>
> > This code will by reused by A1 SoC.
>
> Could expand a bit please ?
>
> >
> > Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>
> In general, I like the idea.
>
> We do have a couple a reset registers lost in middle of clocks and this
> change makes it possible to re-use the code instead duplicating it.
>
> The exported function would be used by audio clock controllers, but the
> module created would be purely about reset.
>
> One may wonder how it ended up in the clock tree, especially since the
> kernel as a reset tree too.
>
> I'm not sure if this should move to the reset framework or if it would
> be an unnecessary churn. Stephen, Philipp, do you have an opinion on
> this ?
>
I'd prefer it be made into an auxiliary device and the driver put in
drivers/reset/ so we can keep reset code in the reset directory. The
auxiliary device creation function can also be in the drivers/reset/
directory so that the clk driver calls some function to create and
register the device.
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* [PATCH v3] arm64: Cleanup __cpu_set_tcr_t0sz()
From: Seongsu Park @ 2024-04-08 2:40 UTC (permalink / raw)
To: will, catalin.marinas, mark.rutland
Cc: linux-arm-kernel, linux-kernel, sgsu.park, Leem ChaeHoon,
Gyeonggeon Choi, Soomin Cho, DaeRo Lee, kmasta
In-Reply-To: <CGME20240408024022epcas1p176f9509f6f85fd8dbfa2dd17067a8aee@epcas1p1.samsung.com>
In cpu_set_default_tcr_t0sz(), it is an error to shift TCR_T0SZ_OFFSET
twice form TCR_T0SZ() and __cpu_set_tcr_t0sz().
Since TCR_T0SZ_OFFSET is 0, no error occurred.
We need to clarify whether the parameter of __cpu_set_tcr_t0sz is a
shifted value or an unshifted value.
We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET.
This is necessary for consistency with TCR_T1SZ.
Therefore, the parameter of __cpu_set_tcr_t0sz is clarified as a shifted
value.
Co-developed-by: Leem ChaeHoon <infinite.run@gmail.com>
Signed-off-by: Leem ChaeHoon <infinite.run@gmail.com>
Co-developed-by: Gyeonggeon Choi <gychoi@student.42seoul.kr>
Signed-off-by: Gyeonggeon Choi <gychoi@student.42seoul.kr>
Co-developed-by: Soomin Cho <to.soomin@gmail.com>
Signed-off-by: Soomin Cho <to.soomin@gmail.com>
Co-developed-by: DaeRo Lee <skseofh@gmail.com>
Signed-off-by: DaeRo Lee <skseofh@gmail.com>
Co-developed-by: kmasta <kmasta.study@gmail.com>
Signed-off-by: kmasta <kmasta.study@gmail.com>
Signed-off-by: Seongsu Park <sgsu.park@samsung.com>
---
v2:
- Condition is updated
v3:
- Commit message is updated
- cpu_set_tcr_t0sz macro is added
---
arch/arm64/include/asm/mmu_context.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index c768d16b81a4..fb603ec7f61f 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -72,15 +72,16 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
{
unsigned long tcr = read_sysreg(tcr_el1);
- if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
+ if ((tcr & TCR_T0SZ_MASK) == t0sz)
return;
tcr &= ~TCR_T0SZ_MASK;
- tcr |= t0sz << TCR_T0SZ_OFFSET;
+ tcr |= t0sz;
write_sysreg(tcr, tcr_el1);
isb();
}
+#define cpu_set_tcr_t0sz(t0sz) __cpu_set_tcr_t0sz(TCR_T0SZ(t0sz))
#define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual))
#define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz)
@@ -134,7 +135,7 @@ static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz)
{
cpu_set_reserved_ttbr0();
local_flush_tlb_all();
- __cpu_set_tcr_t0sz(t0sz);
+ cpu_set_tcr_t0sz(t0sz);
/* avoid cpu_switch_mm() and its SW-PAN and CNP interactions */
write_sysreg(ttbr0, ttbr0_el1);
--
2.34.1
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* [PATCH v4 1/2] dt-bindings: media: imx8-jpeg: Add clocks entries
From: Mirela Rabulea @ 2024-04-08 3:07 UTC (permalink / raw)
To: shawnguo, robh+dt, krzysztof.kozlowski+dt, festevam, festevam,
alexander.stein, Frank.li, ming.qian
Cc: conor+dt, devicetree, linux-arm-kernel, s.hauer, kernel, mchehab,
hverkuil, linux-media, imx, linux-kernel
From: Fabio Estevam <festevam@gmail.com>
The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs need
the PER and IPG clocks to be functional, so add the clock entries.
This also fixes the following schema warning:
imx8qm-apalis-eval.dtb: jpegdec@58400000: 'assigned-clock-rates', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
---
Changes since v3:
- Add items for clocks (per Krzysztof's feddback)
- Add description for clocks (per Conor's feddback to the other similar patch from Alexander)
- Add "media:" to the subject
- Add Mirela's signed-off
- For the similar patches that were sent for this issue, should Co-developed-by/Signed-off-by be added? Alexander Stein? Frank Li?
Changes since v2:
- Remove clock-names. (Mirela)
.../devicetree/bindings/media/nxp,imx8-jpeg.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
index 3d9d1db37040..cc040feb77d7 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
@@ -31,6 +31,14 @@ properties:
reg:
maxItems: 1
+ clocks:
+ description:
+ The JPEG decoder/encoder requires two clocks for it's wrapper (AXI and APB),
+ and one clock for it's core engine (AXI, same source as for the wrapper)
+ items:
+ - description: AXI DMA engine clock for fetching JPEG bitstream from memory (per)
+ - description: IP bus clock for register access (ipg)
+
interrupts:
description: |
There are 4 slots available in the IP, which the driver may use
@@ -49,6 +57,7 @@ properties:
required:
- compatible
- reg
+ - clocks
- interrupts
- power-domains
@@ -56,12 +65,15 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/firmware/imx/rsrc.h>
jpegdec: jpegdec@58400000 {
compatible = "nxp,imx8qxp-jpgdec";
reg = <0x58400000 0x00050000 >;
+ clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
+ <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
@@ -76,6 +88,8 @@ examples:
jpegenc: jpegenc@58450000 {
compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
reg = <0x58450000 0x00050000 >;
+ clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
+ <&img_jpeg__lpcg IMX_LPCG_CLK_4>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
--
2.25.1
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* [PATCH v4 2/2] arm64: dts: imx8-ss-img: Remove JPEG clock-names
From: Mirela Rabulea @ 2024-04-08 3:07 UTC (permalink / raw)
To: shawnguo, robh+dt, krzysztof.kozlowski+dt, festevam, festevam,
alexander.stein, Frank.li, ming.qian
Cc: conor+dt, devicetree, linux-arm-kernel, s.hauer, kernel, mchehab,
hverkuil, linux-media, imx, linux-kernel
In-Reply-To: <20240408030734.1191069-1-mirela.rabulea@nxp.com>
From: Fabio Estevam <festevam@gmail.com>
Per nxp,imx8-jpeg.yaml, the clock-names entry is not valid.
Remove them.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v3:
- Just added "imx8-ss-img:" in the subject
Changes since v2:
- Newly introduced.
arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
index e7783cc2d830..77d2928997b4 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
@@ -21,7 +21,6 @@ jpegdec: jpegdec@58400000 {
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
- clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
@@ -35,7 +34,6 @@ jpegenc: jpegenc@58450000 {
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
- clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
--
2.25.1
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* Re: [EXT] Re: [PATCH 1/1] dt-bindings: media: imx-jpeg: add clocks,clock-names,slot to fix warning
From: Mirela Rabulea @ 2024-04-08 3:15 UTC (permalink / raw)
To: Krzysztof Kozlowski, Frank Li, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER,
open list:NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <af602862-5120-4717-adb6-694ada09e8d8@linaro.org>
Hi Krzysztof,
On 04.04.2024 09:26, Krzysztof Kozlowski wrote:
> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
>
>
> On 04/04/2024 05:52, Frank Li wrote:
>> Fix below DTB_CHECK warning.
>>
>> make CHECK_DTBS=y freescale/imx8qxp-mek.dtb
>> DTC_CHK arch/arm64/boot/dts/freescale/imx8qxp-mek.dtb
>> arch/arm64/boot/dts/freescale/imx8qxp-mek.dtb: jpegdec@58400000: 'assigned-clock-rates', 'assigned-clocks', 'clock-names', 'clocks', 'slot' do not match any of the regexes: 'pinctrl-[0-9]+'
>> from schema $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
> No, that's not the reason to add properties. Add them if they are valid.
>
>
>
>> + slot:
>> + description: Certain slot number is used.
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + minimum: 0
>> + maximum: 3
> NAK. Every time.
>
> Fix your DTS instead.
>
> Please read the feedback instead of pushing this stuff for the third time!
>
> https://lore.kernel.org/all/bbb1875b-7980-46aa-80b4-dbaf2a2d5755@linaro.org/
>
> Can NXP take responsibility for this piece of code?
Thanks for feedback.
For the clocks issue, I looked at the patches sent previously by
Alexander Stein and Fabio Estevam, and the current one:
https://lore.kernel.org/linux-devicetree/?q=dfblob%3A3d9d1db3704+dfblob%3A7899e17aff3
As I also said in the past, I think Fabio's patch was more complete, so
I took his _v3, I tried to incorporate all the feedback given, and I
sent a subsequent _v4, here (bindings & dtb):
https://lore.kernel.org/linux-devicetree/20240408030734.1191069-1-mirela.rabulea@nxp.com/
For the slots issue, I will consult with Ming and get back.
Thanks for your patience, and sorry for the inconvenience.
Regards,
Mirela
>
> Best regards,
> Krzysztof
>
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* Re: [PATCH v1 2/3] dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path
From: Chen-Yu Tsai @ 2024-04-08 3:20 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, robh, krzysztof.kozlowski+dt, conor+dt, p.zabel,
airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
matthias.bgg, shawn.sung, yu-chang.lee, ck.hu, jitao.shi,
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, kernel
In-Reply-To: <20240404081635.91412-3-angelogioacchino.delregno@collabora.com>
On Thu, Apr 4, 2024 at 4:16 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths
> per HW instance (so potentially up to six displays for multi-vdo SoCs).
>
> The MMSYS or VDOSYS is always the first component in the DDP pipeline,
> so it only supports an output port with multiple endpoints - where each
> endpoint defines the starting point for one of the (currently three)
> possible hardware paths.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../bindings/arm/mediatek/mediatek,mmsys.yaml | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index b3c6888c1457..90758bb5bcb1 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -93,6 +93,29 @@ properties:
> '#reset-cells':
> const: 1
>
> + port:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output port node. This port connects the MMSYS/VDOSYS output to
> + the first component of one display pipeline, for example one of
> + the available OVL or RDMA blocks.
> + Some MediaTek SoCs support up to three display outputs per MMSYS.
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: Output to the primary display pipeline
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: Output to the secondary display pipeline
> +
> + endpoint@2:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: Output to the tertiary display pipeline
> +
> + required:
> + - endpoint@0
> +
Technically the mmsys device serves as an glue layer for the display
pipeline, providing things like clock control and signal routing; the
device itself is not part of the pipeline, and probably shouldn't be
part of the graph?
ChenYu
> required:
> - compatible
> - reg
> --
> 2.44.0
>
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^ permalink raw reply
* [PATCH] arm64: dts: meson: fix S4 power-controller node
From: Xianwei Zhao via B4 Relay @ 2024-04-08 3:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel,
Xianwei Zhao
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
The power-controller module works well by adding its parent
node secure-monitor.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ce90b35686a2..24d00dce4969 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -65,10 +65,13 @@ xtal: xtal-clk {
#clock-cells = <0>;
};
- pwrc: power-controller {
- compatible = "amlogic,meson-s4-pwrc";
- #power-domain-cells = <1>;
- status = "okay";
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-s4-pwrc";
+ #power-domain-cells = <1>;
+ };
};
soc {
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240408-fix-secpwr-s4-a99ff960d0ae
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
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^ permalink raw reply related
* Re: [RFC PATCH 1/1] clk: sunxi-ng: h6-r: add GPU power domain
From: Stephen Boyd @ 2024-04-08 3:33 UTC (permalink / raw)
To: Andre Przywara, Chen-Yu Tsai, Jernej Skrabec, Michael Turquette,
Samuel Holland, Ulf Hansson
Cc: linux-clk, linux-pm, linux-arm-kernel, linux-sunxi
In-Reply-To: <20240225160616.15001-2-andre.przywara@arm.com>
Quoting Andre Przywara (2024-02-25 08:06:16)
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> index 02b28cfc5525e..363fb7a71e9f5 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> @@ -217,6 +219,86 @@ static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
[...]
> +static int sun50i_h616_register_ppu(struct platform_device *pdev,
> + void __iomem *base)
> +{
> + struct device *dev = &pdev->dev;
> + struct genpd_onecell_data *ppu;
> + struct sun50i_h616_ppu_pd *pd;
> + int ret;
> +
> + pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
> + if (!pd)
> + return -ENOMEM;
> +
> + ppu = devm_kzalloc(dev, sizeof(*ppu), GFP_KERNEL);
> + if (!ppu)
> + return -ENOMEM;
> +
> + ppu->domains = devm_kzalloc(dev, sizeof(*ppu->domains), GFP_KERNEL);
> + if (!ppu->domains)
> + return -ENOMEM;
> +
> + ppu->num_domains = 1;
> + pd->genpd.name = "GPU";
> + pd->genpd.power_off = sun50i_h616_ppu_pd_power_off;
> + pd->genpd.power_on = sun50i_h616_ppu_pd_power_on;
> + pd->base = base;
> +
> + ret = pm_genpd_init(&pd->genpd, NULL, !sun50i_h616_ppu_power_status(pd));
> + if (ret) {
> + dev_warn(dev, "Failed to add GPU power domain: %d\n", ret);
> + return ret;
> + }
> +
> + ppu->domains[0] = &pd->genpd;
> + ret = of_genpd_add_provider_onecell(dev->of_node, ppu);
Is this provider removed somewhere when probe fails or the driver is
removed? It looks like the rest of the driver uses devm during probe.
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^ permalink raw reply
* Re: [PATCH] clkdev: report over-sized strings when creating clkdev entries
From: Stephen Boyd @ 2024-04-08 3:48 UTC (permalink / raw)
To: Russell King, linux-arm-kernel
Cc: Duanqiang Wen, mturquette, linux-clk, linux-kernel
In-Reply-To: <E1rl62V-004UFh-Te@rmk-PC.armlinux.org.uk>
Quoting Russell King (Oracle) (2024-03-15 04:47:55)
> Report an error when an attempt to register a clkdev entry results in a
> truncated string so the problem can be easily spotted.
>
> Reported by: Duanqiang Wen <duanqiangwen@net-swift.com>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> ---
Russell, are you taking this through your tree? I took the last one
because it was small and you reviewed it instead of applied it. If
you're taking it please add:
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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^ permalink raw reply
* Re: [PATCH v2 1/5] clk: scmi: Allocate CLK operations dynamically
From: Stephen Boyd @ 2024-04-08 4:38 UTC (permalink / raw)
To: Cristian Marussi, linux-arm-kernel, linux-clk, linux-kernel
Cc: sudeep.holla, james.quinlan, f.fainelli, vincent.guittot,
peng.fan, michal.simek, quic_sibis, quic_nkela,
souvik.chakravarty, mturquette, Cristian Marussi
In-Reply-To: <20240325210025.1448717-2-cristian.marussi@arm.com>
Quoting Cristian Marussi (2024-03-25 14:00:21)
> diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
> index 8cbe24789c24..d5d369b052bd 100644
> --- a/drivers/clk/clk-scmi.c
> +++ b/drivers/clk/clk-scmi.c
> @@ -16,6 +16,14 @@
> #define NOT_ATOMIC false
> #define ATOMIC true
>
> +enum scmi_clk_feats {
> + SCMI_CLK_ATOMIC_SUPPORTED,
> + SCMI_CLK_MAX_FEATS
> +};
> +
> +#define SCMI_MAX_CLK_OPS (1 << SCMI_CLK_MAX_FEATS)
> +
> +static const struct clk_ops *clk_ops_db[SCMI_MAX_CLK_OPS];
Can it be 'scmi_clk_ops_db' for some name spacing?
> static const struct scmi_clk_proto_ops *scmi_proto_clk_ops;
>
> struct scmi_clk {
> @@ -230,6 +202,106 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
> return ret;
> }
>
> +/**
> + * scmi_clk_ops_alloc() - Alloc and configure clock operations
> + * @dev: A device reference for devres
> + * @feats_key: A bitmap representing the desired clk_ops capabilities.
Drop the period please because it's not consistent with the previous
argument descriptor.
> + *
> + * Allocate and configure a proper set of clock operations depending on the
> + * specifically required SCMI clock features.
> + *
> + * Return: A pointer to the allocated and configured clk_ops on Success,
Lowercase 'Success'.
> +
> +/**
> + * scmi_clk_ops_select() - Select a proper set of clock operations
> + * @sclk: A reference to an SCMI clock descriptor
> + * @atomic_capable: A flag to indicate if atomic mode is supported by the
> + * transport
> + * @atomic_threshold: Platform atomic threshold value
Is this in nanoseconds, microseconds, or ??? Maybe a better description is
"clk_ops are atomic when clk enable_latency is less than X [time unit]"
> + *
> + * After having built a bitmap descriptor to represent the set of features
> + * needed by this SCMI clock, at first use it to lookup into the set of
> + * previously allocated clk_ops to check if a suitable combination of clock
> + * operations was already created; when no match is found allocate a brand new
> + * set of clk_ops satisfying the required combination of features and save it
> + * for future references.
> + *
> + * In this way only one set of clk_ops is ever created for each different
> + * combination that is effectively needed.
> + *
> + * Return: A pointer to the allocated and configured clk_ops on Success, or
Lowercase 'Success'.
> + * NULL otherwise.
> + */
> +static const struct clk_ops *
> +scmi_clk_ops_select(struct scmi_clk *sclk, bool atomic_capable,
> + unsigned int atomic_threshold)
> +{
> + const struct scmi_clock_info *ci = sclk->info;
> + unsigned int feats_key = 0;
> + const struct clk_ops *ops;
> +
> + /*
> + * Note that when transport is atomic but SCMI protocol did not
> + * specify (or support) an enable_latency associated with a
> + * clock, we default to use atomic operations mode.
> + */
> + if (atomic_capable && ci->enable_latency <= atomic_threshold)
> + feats_key |= BIT(SCMI_CLK_ATOMIC_SUPPORTED);
> +
Can we have a static_assert() here that makes sure 'feats_key' isn't
larger than the size of clk_ops_db?
static_assert(ARRAY_SIZE(clk_ops_db) >= feats_key);
> + /* Lookup previously allocated ops */
> + ops = clk_ops_db[feats_key];
> + if (!ops) {
> + ops = scmi_clk_ops_alloc(sclk->dev, feats_key);
> + if (!ops)
> + return NULL;
This could be less nested if the first lookup is put in
scmi_clk_ops_alloc() and the store below is folded in. Or an early
return if found.
ops = clk_ops_db[feats_key];
if (ops)
return ops;
/* Didn't find one */
ops = scmi_clk_ops_alloc(...)
if (!ops)
return NULL;
clk_ops_db[feats_key] = ops;
return ops;
> +
> + /* Store new ops combinations */
> + clk_ops_db[feats_key] = ops;
> + }
> +
> + return ops;
> +}
> +
> static int scmi_clocks_probe(struct scmi_device *sdev)
> {
> int idx, count, err;
> @@ -285,16 +357,10 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
> sclk->ph = ph;
> sclk->dev = dev;
>
> - /*
> - * Note that when transport is atomic but SCMI protocol did not
> - * specify (or support) an enable_latency associated with a
> - * clock, we default to use atomic operations mode.
> - */
> - if (is_atomic &&
> - sclk->info->enable_latency <= atomic_threshold)
> - scmi_ops = &scmi_atomic_clk_ops;
> - else
> - scmi_ops = &scmi_clk_ops;
> + scmi_ops = scmi_clk_ops_select(sclk, is_atomic,
'is_atomic' should probably be 'transport_is_atomic' so this reads
easier.
> + atomic_threshold);
> + if (!scmi_ops)
> + return -ENOMEM;
>
> /* Initialize clock parent data. */
> if (sclk->info->num_parents > 0) {
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^ permalink raw reply
* Re: [PATCH] MAINTAINERS: Drop Li Yang as their email address stopped working
From: Michael Ellerman @ 2024-04-08 4:48 UTC (permalink / raw)
To: Uwe Kleine-König, Greg Kroah-Hartman
Cc: netdev, linux-usb, linuxppc-dev, Li Yang, Zhang Wei, kernel,
Shawn Guo, linux-arm-kernel, vladimir.oltean
In-Reply-To: <20240405072042.697182-2-u.kleine-koenig@pengutronix.de>
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> writes:
> When sending a patch to (among others) Li Yang the nxp MTA replied that
> the address doesn't exist and so the mail couldn't be delivered. The
> error code was 550, so at least technically that's not a temporal issue.
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
> Hello,
>
> I added the affected maintainers and lists to Cc:, maybe someone there
> knows if this issue is only temporal?
Apparently not. See https://lore.kernel.org/all/20240219153016.ntltc76bphwrv6hn@skbuf/
Leo Li (Li Yang) is no longer with NXP.
cheers
> @Greg: Given that I noticed the non-existing address when sending an usb
> patch, I suggest you care for application of this patch (iff it should
> be applied now). If Li Yang disappeared indeed, I'd prefer to drop the
> contact from MAINTAINERS early to not give wrong expectations to
> contributors.
>
> Best regards
> Uwe
>
> MAINTAINERS | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7c121493f43d..be19aad15045 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2191,7 +2191,6 @@ N: mxs
>
> ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE
> M: Shawn Guo <shawnguo@kernel.org>
> -M: Li Yang <leoyang.li@nxp.com>
> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
> @@ -8523,7 +8522,6 @@ S: Maintained
> F: drivers/video/fbdev/fsl-diu-fb.*
>
> FREESCALE DMA DRIVER
> -M: Li Yang <leoyang.li@nxp.com>
> M: Zhang Wei <zw@zh-kernel.org>
> L: linuxppc-dev@lists.ozlabs.org
> S: Maintained
> @@ -8688,10 +8686,9 @@ F: drivers/soc/fsl/qe/tsa.h
> F: include/dt-bindings/soc/cpm1-fsl,tsa.h
>
> FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
> -M: Li Yang <leoyang.li@nxp.com>
> L: netdev@vger.kernel.org
> L: linuxppc-dev@lists.ozlabs.org
> -S: Maintained
> +S: Orphan
> F: drivers/net/ethernet/freescale/ucc_geth*
>
> FREESCALE QUICC ENGINE UCC HDLC DRIVER
> @@ -8708,10 +8705,9 @@ S: Maintained
> F: drivers/tty/serial/ucc_uart.c
>
> FREESCALE SOC DRIVERS
> -M: Li Yang <leoyang.li@nxp.com>
> L: linuxppc-dev@lists.ozlabs.org
> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> -S: Maintained
> +S: Orphan
> F: Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml
> F: Documentation/devicetree/bindings/soc/fsl/
> F: drivers/soc/fsl/
> @@ -8745,10 +8741,9 @@ F: Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
> F: sound/soc/fsl/fsl_qmc_audio.c
>
> FREESCALE USB PERIPHERAL DRIVERS
> -M: Li Yang <leoyang.li@nxp.com>
> L: linux-usb@vger.kernel.org
> L: linuxppc-dev@lists.ozlabs.org
> -S: Maintained
> +S: Orphan
> F: drivers/usb/gadget/udc/fsl*
>
> FREESCALE USB PHY DRIVER
>
> base-commit: c85af715cac0a951eea97393378e84bb49384734
> --
> 2.43.0
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^ permalink raw reply
* Re: [PATCH v2 2/5] clk: scmi: Add support for state control restricted clocks
From: Stephen Boyd @ 2024-04-08 4:48 UTC (permalink / raw)
To: Cristian Marussi, linux-arm-kernel, linux-clk, linux-kernel
Cc: sudeep.holla, james.quinlan, f.fainelli, vincent.guittot,
peng.fan, michal.simek, quic_sibis, quic_nkela,
souvik.chakravarty, mturquette, Cristian Marussi
In-Reply-To: <20240325210025.1448717-3-cristian.marussi@arm.com>
Quoting Cristian Marussi (2024-03-25 14:00:22)
> Some exposed SCMI Clocks could be marked as non-supporting state changes.
> Configure a clk_ops descriptor which does not provide the state change
> callbacks for such clocks when registering with CLK framework.
>
> CC: Michael Turquette <mturquette@baylibre.com>
> CC: Stephen Boyd <sboyd@kernel.org>
> CC: linux-clk@vger.kernel.org
> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
> ---
> drivers/clk/clk-scmi.c | 22 +++++++++++++++-------
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
> index d5d369b052bd..fc9603988d91 100644
> --- a/drivers/clk/clk-scmi.c
> +++ b/drivers/clk/clk-scmi.c
> @@ -18,6 +18,7 @@
>
> enum scmi_clk_feats {
> SCMI_CLK_ATOMIC_SUPPORTED,
> + SCMI_CLK_STATE_CTRL_FORBIDDEN,
Can it be positive, i.e. SCMI_CLK_STATE_CTRL_SUPPORTED?
> SCMI_CLK_MAX_FEATS
> };
>
> @@ -230,15 +231,19 @@ scmi_clk_ops_alloc(struct device *dev, unsigned long feats_key)
> * only the prepare/unprepare API, as allowed by the clock framework
> * when atomic calls are not available.
> */
> - if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED)) {
> - ops->enable = scmi_clk_atomic_enable;
> - ops->disable = scmi_clk_atomic_disable;
> - ops->is_enabled = scmi_clk_atomic_is_enabled;
> - } else {
> - ops->prepare = scmi_clk_enable;
> - ops->unprepare = scmi_clk_disable;
> + if (!(feats_key & BIT(SCMI_CLK_STATE_CTRL_FORBIDDEN))) {
> + if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED)) {
> + ops->enable = scmi_clk_atomic_enable;
> + ops->disable = scmi_clk_atomic_disable;
> + } else {
> + ops->prepare = scmi_clk_enable;
> + ops->unprepare = scmi_clk_disable;
> + }
> }
>
> + if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED))
> + ops->is_enabled = scmi_clk_atomic_is_enabled;
> +
> /* Rate ops */
> ops->recalc_rate = scmi_clk_recalc_rate;
> ops->round_rate = scmi_clk_round_rate;
> @@ -288,6 +293,9 @@ scmi_clk_ops_select(struct scmi_clk *sclk, bool atomic_capable,
> if (atomic_capable && ci->enable_latency <= atomic_threshold)
> feats_key |= BIT(SCMI_CLK_ATOMIC_SUPPORTED);
>
> + if (ci->state_ctrl_forbidden)
Then this is negated.
> + feats_key |= BIT(SCMI_CLK_STATE_CTRL_FORBIDDEN);
> +
> /* Lookup previously allocated ops */
> ops = clk_ops_db[feats_key];
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^ permalink raw reply
* [PATCH] ASoC: dt-bindings: imx-audio-spdif: convert to YAML
From: Shengjiu Wang @ 2024-04-08 4:55 UTC (permalink / raw)
To: lgirdwood, broonie, robh+dt, krzysztof.kozlowski+dt, conor+dt,
shengjiu.wang, linux-sound, devicetree, linux-kernel, shawnguo,
s.hauer, kernel, festevam, imx, linux-arm-kernel
Convert the imx-audio-spdif binding to YAML.
When testing dtbs_check, found below compatible strings
are not listed in document:
fsl,imx-sabreauto-spdif
fsl,imx6sx-sdb-spdif
So add them in yaml file to pass the test.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
.../bindings/sound/imx-audio-spdif.txt | 36 -----------
.../bindings/sound/imx-audio-spdif.yaml | 62 +++++++++++++++++++
2 files changed, 62 insertions(+), 36 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.yaml
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
deleted file mode 100644
index da84a442ccea..000000000000
--- a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Freescale i.MX audio complex with S/PDIF transceiver
-
-Required properties:
-
- - compatible : "fsl,imx-audio-spdif"
-
- - model : The user-visible name of this sound complex
-
- - spdif-controller : The phandle of the i.MX S/PDIF controller
-
-
-Optional properties:
-
- - spdif-out : This is a boolean property. If present, the
- transmitting function of S/PDIF will be enabled,
- indicating there's a physical S/PDIF out connector
- or jack on the board or it's connecting to some
- other IP block, such as an HDMI encoder or
- display-controller.
-
- - spdif-in : This is a boolean property. If present, the receiving
- function of S/PDIF will be enabled, indicating there
- is a physical S/PDIF in connector/jack on the board.
-
-* Note: At least one of these two properties should be set in the DT binding.
-
-
-Example:
-
-sound-spdif {
- compatible = "fsl,imx-audio-spdif";
- model = "imx-spdif";
- spdif-controller = <&spdif>;
- spdif-out;
- spdif-in;
-};
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-spdif.yaml b/Documentation/devicetree/bindings/sound/imx-audio-spdif.yaml
new file mode 100644
index 000000000000..b29e024f553f
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-spdif.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/imx-audio-spdif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX audio complex with S/PDIF transceiver
+
+maintainers:
+ - Shengjiu Wang <shengjiu.wang@nxp.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,imx-audio-spdif
+ - enum:
+ - fsl,imx-sabreauto-spdif
+ - fsl,imx6sx-sdb-spdif
+ - items:
+ - enum:
+ - fsl,imx-audio-spdif
+
+ model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: User specified audio sound card name
+
+ spdif-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the i.MX S/PDIF controller
+
+ spdif-out:
+ type: boolean
+ description: |
+ If present, the transmitting function of S/PDIF will be enabled,
+ indicating there's a physical S/PDIF out connector or jack on the
+ board or it's connecting to some other IP block, such as an HDMI
+ encoder or display-controller.
+
+ spdif-in:
+ type: boolean
+ description: |
+ If present, the receiving function of S/PDIF will be enabled,
+ indicating there is a physical S/PDIF in connector/jack on the board.
+
+required:
+ - compatible
+ - model
+ - spdif-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-out;
+ spdif-in;
+ };
--
2.34.1
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^ permalink raw reply related
* Re: [PATCH] ASoC: dt-bindings: imx-audio-spdif: convert to YAML
From: Krzysztof Kozlowski @ 2024-04-08 5:48 UTC (permalink / raw)
To: Shengjiu Wang, lgirdwood, broonie, robh+dt,
krzysztof.kozlowski+dt, conor+dt, shengjiu.wang, linux-sound,
devicetree, linux-kernel, shawnguo, s.hauer, kernel, festevam,
imx, linux-arm-kernel
In-Reply-To: <1712552142-27055-1-git-send-email-shengjiu.wang@nxp.com>
On 08/04/2024 06:55, Shengjiu Wang wrote:
> Convert the imx-audio-spdif binding to YAML.
>
> When testing dtbs_check, found below compatible strings
> are not listed in document:
>
> fsl,imx-sabreauto-spdif
> fsl,imx6sx-sdb-spdif
>
> So add them in yaml file to pass the test.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
> .../bindings/sound/imx-audio-spdif.txt | 36 -----------
> .../bindings/sound/imx-audio-spdif.yaml | 62 +++++++++++++++++++
Filename like compatible.
> 2 files changed, 62 insertions(+), 36 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
> create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.yaml
>
...
> +$id: http://devicetree.org/schemas/sound/imx-audio-spdif.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX audio complex with S/PDIF transceiver
> +
> +maintainers:
> + - Shengjiu Wang <shengjiu.wang@nxp.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - fsl,imx-audio-spdif
> + - enum:
> + - fsl,imx-sabreauto-spdif
> + - fsl,imx6sx-sdb-spdif
> + - items:
No need for items here.
> + - enum:
> + - fsl,imx-audio-spdif
> +
> + model:
> + $ref: /schemas/types.yaml#/definitions/string
> + description: User specified audio sound card name
> +
> + spdif-controller:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The phandle of the i.MX S/PDIF controller
> +
> + spdif-out:
> + type: boolean
> + description: |
Do not need '|' unless you need to preserve formatting.
> + If present, the transmitting function of S/PDIF will be enabled,
> + indicating there's a physical S/PDIF out connector or jack on the
> + board or it's connecting to some other IP block, such as an HDMI
> + encoder or display-controller.
> +
> + spdif-in:
> + type: boolean
> + description: |
Do not need '|' unless you need to preserve formatting.
> + If present, the receiving function of S/PDIF will be enabled,
> + indicating there is a physical S/PDIF in connector/jack on the board.
> +
> +required:
> + - compatible
> + - model
> + - spdif-controller
> +
spdif-out and/or spdif-in are required. You either miss oneOf: required:
or anyOf:
https://elixir.bootlin.com/linux/v6.8-rc4/source/Documentation/devicetree/bindings/connector/usb-connector.yaml#L305
https://elixir.bootlin.com/linux/v5.17-rc2/source/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml#L91
Judging by example, the first one.
> +additionalProperties: false
> +
> +examples:
> + - |
> + sound-spdif {
spdif {
> + compatible = "fsl,imx-audio-spdif";
> + model = "imx-spdif";
> + spdif-controller = <&spdif>;
> + spdif-out;
> + spdif-in;
> + };
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set additionalProperties to true
From: Krzysztof Kozlowski @ 2024-04-08 5:57 UTC (permalink / raw)
To: Peng Fan, Peng Fan (OSS), Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Sudeep Holla, Cristian Marussi
Cc: devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <DU0PR04MB9417839C42681F57366003EF88012@DU0PR04MB9417.eurprd04.prod.outlook.com>
On 08/04/2024 01:50, Peng Fan wrote:
>> Subject: Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set
>> additionalProperties to true
>>
>> On 07/04/2024 12:04, Peng Fan wrote:
>>>> Subject: Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set
>>>> additionalProperties to true
>>>>
>>>> On 07/04/2024 02:37, Peng Fan wrote:
>>>>>> Subject: Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set
>>>>>> additionalProperties to true
>>>>>>
>>>>>> On 05/04/2024 14:39, Peng Fan (OSS) wrote:
>>>>>>> From: Peng Fan <peng.fan@nxp.com>
>>>>>>>
>>>>>>> When adding vendor extension protocols, there is dt-schema warning:
>>>>>>> "
>>>>>>> imx,scmi.example.dtb: scmi: 'protocol@81', 'protocol@84' do not
>>>>>>> match any of the regexes: 'pinctrl-[0-9]+'
>>>>>>> "
>>>>>>>
>>>>>>> Set additionalProperties to true to address the issue.
>>>>>>
>>>>>> I do not see anything addressed here, except making the binding
>>>>>> accepting anything anywhere...
>>>>>
>>>>> I not wanna add vendor protocols in arm,scmi.yaml, so will introduce
>>>>> a new yaml imx.scmi.yaml which add i.MX SCMI protocol extension.
>>>>>
>>>>> With additionalProperties set to false, I not know how, please suggest.
>>>>
>>>> First of all, you cannot affect negatively existing devices (their
>>>> bindings) and your patch does exactly that. This should make you
>>>> thing what is the correct approach...
>>>>
>>>> Rob gave you the comment about missing compatible - you still did not
>>>> address that.
>>>
>>> I added the compatible in patch 2/6 in the examples "compatible =
>> "arm,scmi";"
>>
>> So you claim that your vendor extensions are the same or fully compatible
>> with arm,scmi and you add nothing... Are your extensions/protocol valid for
>> arm,scmi?
>
> Yes. They are valid for arm,scmi.
>
> If yes, why is this in separate binding. If no, why you use someone
>> else's compatible?
>
> Per SCMI Spec
> 0x80-0xFF: Reserved for vendor or platform-specific extensions to
> this interface
>
> i.MX use 0x81 for BBM, 0x84 for MISC. But other vendors will use
> the id for their own protocol.
So how are they valid for arm,scmi? I don't understand.
Best regards,
Krzysztof
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