* [PATCH v3 net-next 09/14] net: dsa: add NETC switch tag support
From: Wei Fang @ 2026-03-26 6:29 UTC (permalink / raw)
To: claudiu.manoil, vladimir.oltean, xiaoning.wang, andrew+netdev,
davem, edumazet, kuba, pabeni, robh, krzk+dt, conor+dt,
f.fainelli, frank.li, chleroy, horms, linux, andrew
Cc: netdev, linux-kernel, devicetree, linuxppc-dev, linux-arm-kernel,
imx
In-Reply-To: <20260326062917.3552334-1-wei.fang@nxp.com>
The NXP NETC switch tag is a proprietary header added to frames after the
source MAC address. The switch tag has 3 types, and each type has 1 ~ 4
subtypes, the details are as follows.
Forward NXP switch tag (Type=0): Represents forwarded frames.
- SubType = 0 - Normal frame processing.
To_Port NXP switch tag (Type=1): Represents frames that are to be sent
to a specific switch port.
- SubType = 0. No request to perform timestamping.
- SubType = 1. Request to perform one-step timestamping.
- SubType = 2. Request to perform two-step timestamping.
- SubType = 3. Request to perform both one-step timestamping and
two-step timestamping.
To_Host NXP switch tag (Type=2): Represents frames redirected or copied
to the switch management port.
- SubType = 0. Received frames redirected or copied to the switch
management port.
- SubType = 1. Received frames redirected or copied to the switch
management port with captured timestamp at the switch port where
the frame was received.
- SubType = 2. Transmit timestamp response (two-step timestamping).
In addition, the length of different type switch tag is different, the
minimum length is 6 bytes, the maximum length is 14 bytes. Currently,
Forward tag, SubType 0 of To_Port tag and Subtype 0 of To_Host tag are
supported. More tags will be supported in the future.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
include/linux/dsa/tag_netc.h | 14 +++
include/net/dsa.h | 2 +
include/uapi/linux/if_ether.h | 1 +
net/dsa/Kconfig | 10 ++
net/dsa/Makefile | 1 +
net/dsa/tag_netc.c | 185 ++++++++++++++++++++++++++++++++++
6 files changed, 213 insertions(+)
create mode 100644 include/linux/dsa/tag_netc.h
create mode 100644 net/dsa/tag_netc.c
diff --git a/include/linux/dsa/tag_netc.h b/include/linux/dsa/tag_netc.h
new file mode 100644
index 000000000000..fe964722e5b0
--- /dev/null
+++ b/include/linux/dsa/tag_netc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2025-2026 NXP
+ */
+
+#ifndef __NET_DSA_TAG_NETC_H
+#define __NET_DSA_TAG_NETC_H
+
+#include <linux/skbuff.h>
+#include <net/dsa.h>
+
+#define NETC_TAG_MAX_LEN 14
+
+#endif
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 6c17446f3dcc..6bed824d1f07 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -58,6 +58,7 @@ struct tc_action;
#define DSA_TAG_PROTO_YT921X_VALUE 30
#define DSA_TAG_PROTO_MXL_GSW1XX_VALUE 31
#define DSA_TAG_PROTO_MXL862_VALUE 32
+#define DSA_TAG_PROTO_NETC_VALUE 33
enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -93,6 +94,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_YT921X = DSA_TAG_PROTO_YT921X_VALUE,
DSA_TAG_PROTO_MXL_GSW1XX = DSA_TAG_PROTO_MXL_GSW1XX_VALUE,
DSA_TAG_PROTO_MXL862 = DSA_TAG_PROTO_MXL862_VALUE,
+ DSA_TAG_PROTO_NETC = DSA_TAG_PROTO_NETC_VALUE,
};
struct dsa_switch;
diff --git a/include/uapi/linux/if_ether.h b/include/uapi/linux/if_ether.h
index df9d44a11540..fb5efc8e06cc 100644
--- a/include/uapi/linux/if_ether.h
+++ b/include/uapi/linux/if_ether.h
@@ -123,6 +123,7 @@
#define ETH_P_DSA_A5PSW 0xE001 /* A5PSW Tag Value [ NOT AN OFFICIALLY REGISTERED ID ] */
#define ETH_P_IFE 0xED3E /* ForCES inter-FE LFB type */
#define ETH_P_AF_IUCV 0xFBFB /* IBM af_iucv [ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_NXP_NETC 0xFD3A /* NXP NETC DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
#define ETH_P_802_3_MIN 0x0600 /* If the value in the ethernet type is more than this value
* then the frame is Ethernet II. Else it is 802.3 */
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index 5ed8c704636d..d5e725b90d78 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -125,6 +125,16 @@ config NET_DSA_TAG_KSZ
Say Y if you want to enable support for tagging frames for the
Microchip 8795/937x/9477/9893 families of switches.
+config NET_DSA_TAG_NETC
+ tristate "Tag driver for NXP NETC switches"
+ help
+ Say Y or M if you want to enable support for the NXP Switch Tag (NST),
+ as implemented by NXP NETC switches having version 4.3 or later. The
+ switch tag is a proprietary header added to frames after the source
+ MAC address, it has 3 types and each type has different subtypes, so
+ its length depends on the type and subtype of the tag, the maximum
+ length is 14 bytes.
+
config NET_DSA_TAG_OCELOT
tristate "Tag driver for Ocelot family of switches, using NPI port"
select PACKING
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
index bf7247759a64..b8c2667cd14a 100644
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
obj-$(CONFIG_NET_DSA_TAG_MXL_862XX) += tag_mxl862xx.o
obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o
+obj-$(CONFIG_NET_DSA_TAG_NETC) += tag_netc.o
obj-$(CONFIG_NET_DSA_TAG_NONE) += tag_none.o
obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
obj-$(CONFIG_NET_DSA_TAG_OCELOT_8021Q) += tag_ocelot_8021q.o
diff --git a/net/dsa/tag_netc.c b/net/dsa/tag_netc.c
new file mode 100644
index 000000000000..addd41f7f1b6
--- /dev/null
+++ b/net/dsa/tag_netc.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+#include <linux/dsa/tag_netc.h>
+
+#include "tag.h"
+
+#define NETC_NAME "nxp_netc"
+
+/* Forward NXP switch tag */
+#define NETC_TAG_FORWARD 0
+
+/* To_Port NXP switch tag */
+#define NETC_TAG_TO_PORT 1
+/* SubType0: No request to perform timestamping */
+#define NETC_TAG_TP_SUBTYPE0 0
+
+/* To_Host NXP switch tag */
+#define NETC_TAG_TO_HOST 2
+/* SubType0: frames redirected or copied to CPU port */
+#define NETC_TAG_TH_SUBTYPE0 0
+/* SubType1: frames redirected or copied to CPU port with timestamp */
+#define NETC_TAG_TH_SUBTYPE1 1
+/* SubType2: Transmit timestamp response (two-step timestamping) */
+#define NETC_TAG_TH_SUBTYPE2 2
+
+/* NETC switch tag lengths */
+#define NETC_TAG_FORWARD_LEN 6
+#define NETC_TAG_TP_SUBTYPE0_LEN 6
+#define NETC_TAG_TH_SUBTYPE0_LEN 6
+#define NETC_TAG_TH_SUBTYPE1_LEN 14
+#define NETC_TAG_TH_SUBTYPE2_LEN 14
+#define NETC_TAG_CMN_LEN 5
+
+#define NETC_TAG_SUBTYPE GENMASK(3, 0)
+#define NETC_TAG_TYPE GENMASK(7, 4)
+#define NETC_TAG_QV BIT(0)
+#define NETC_TAG_IPV GENMASK(4, 2)
+#define NETC_TAG_SWITCH GENMASK(2, 0)
+#define NETC_TAG_PORT GENMASK(7, 3)
+
+struct netc_tag_cmn {
+ __be16 tpid;
+ u8 type;
+ u8 qos;
+ u8 switch_port;
+} __packed;
+
+static void netc_fill_common_tag(struct netc_tag_cmn *tag, u8 type,
+ u8 subtype, u8 sw_id, u8 port, u8 ipv)
+{
+ tag->tpid = htons(ETH_P_NXP_NETC);
+ tag->type = FIELD_PREP(NETC_TAG_TYPE, type) |
+ FIELD_PREP(NETC_TAG_SUBTYPE, subtype);
+ tag->qos = NETC_TAG_QV | FIELD_PREP(NETC_TAG_IPV, ipv);
+ tag->switch_port = FIELD_PREP(NETC_TAG_SWITCH, sw_id) |
+ FIELD_PREP(NETC_TAG_PORT, port);
+}
+
+static void *netc_fill_common_tp_tag(struct sk_buff *skb,
+ struct net_device *ndev,
+ u8 subtype, int tag_len)
+{
+ struct dsa_port *dp = dsa_user_to_port(ndev);
+ u16 queue = skb_get_queue_mapping(skb);
+ u8 ipv = netdev_txq_to_tc(ndev, queue);
+ void *tag;
+
+ skb_push(skb, tag_len);
+ dsa_alloc_etype_header(skb, tag_len);
+
+ tag = dsa_etype_header_pos_tx(skb);
+ memset(tag + NETC_TAG_CMN_LEN, 0, tag_len - NETC_TAG_CMN_LEN);
+ netc_fill_common_tag(tag, NETC_TAG_TO_PORT, subtype,
+ dp->ds->index, dp->index, ipv);
+
+ return tag;
+}
+
+static void netc_fill_tp_tag_subtype0(struct sk_buff *skb,
+ struct net_device *ndev)
+{
+ netc_fill_common_tp_tag(skb, ndev, NETC_TAG_TP_SUBTYPE0,
+ NETC_TAG_TP_SUBTYPE0_LEN);
+}
+
+/* Currently only support To_Port tag, subtype 0 */
+static struct sk_buff *netc_xmit(struct sk_buff *skb,
+ struct net_device *ndev)
+{
+ netc_fill_tp_tag_subtype0(skb, ndev);
+
+ return skb;
+}
+
+static int netc_get_rx_tag_len(int rx_type)
+{
+ int type = FIELD_GET(NETC_TAG_TYPE, rx_type);
+
+ if (type == NETC_TAG_TO_HOST) {
+ u8 subtype = rx_type & NETC_TAG_SUBTYPE;
+
+ if (subtype == NETC_TAG_TH_SUBTYPE1)
+ return NETC_TAG_TH_SUBTYPE1_LEN;
+ else if (subtype == NETC_TAG_TH_SUBTYPE2)
+ return NETC_TAG_TH_SUBTYPE2_LEN;
+ else
+ return NETC_TAG_TH_SUBTYPE0_LEN;
+ }
+
+ return NETC_TAG_FORWARD_LEN;
+}
+
+static struct sk_buff *netc_rcv(struct sk_buff *skb,
+ struct net_device *ndev)
+{
+ struct netc_tag_cmn *tag_cmn;
+ int tag_len, sw_id, port;
+
+ if (unlikely(!pskb_may_pull(skb, NETC_TAG_MAX_LEN)))
+ return NULL;
+
+ tag_cmn = dsa_etype_header_pos_rx(skb);
+ tag_len = netc_get_rx_tag_len(tag_cmn->type);
+
+ if (ntohs(tag_cmn->tpid) != ETH_P_NXP_NETC) {
+ dev_warn_ratelimited(&ndev->dev, "Unknown TPID 0x%04x\n",
+ ntohs(tag_cmn->tpid));
+
+ return NULL;
+ }
+
+ if (tag_cmn->qos & NETC_TAG_QV)
+ skb->priority = FIELD_GET(NETC_TAG_IPV, tag_cmn->qos);
+
+ sw_id = NETC_TAG_SWITCH & tag_cmn->switch_port;
+ /* ENETC VEPA switch ID (0) is not supported yet */
+ if (!sw_id) {
+ dev_warn_ratelimited(&ndev->dev,
+ "VEPA switch ID is not supported yet\n");
+
+ return NULL;
+ }
+
+ port = FIELD_GET(NETC_TAG_PORT, tag_cmn->switch_port);
+ skb->dev = dsa_conduit_find_user(ndev, sw_id, port);
+ if (!skb->dev)
+ return NULL;
+
+ if (tag_cmn->type == NETC_TAG_FORWARD)
+ dsa_default_offload_fwd_mark(skb);
+
+ /* Remove Switch tag from the frame */
+ skb_pull_rcsum(skb, tag_len);
+ dsa_strip_etype_header(skb, tag_len);
+
+ return skb;
+}
+
+static void netc_flow_dissect(const struct sk_buff *skb, __be16 *proto,
+ int *offset)
+{
+ struct netc_tag_cmn *tag_cmn = (struct netc_tag_cmn *)(skb->data - 2);
+ int tag_len = netc_get_rx_tag_len(tag_cmn->type);
+
+ *offset = tag_len;
+ *proto = ((__be16 *)skb->data)[(tag_len / 2) - 1];
+}
+
+static const struct dsa_device_ops netc_netdev_ops = {
+ .name = NETC_NAME,
+ .proto = DSA_TAG_PROTO_NETC,
+ .xmit = netc_xmit,
+ .rcv = netc_rcv,
+ .needed_headroom = NETC_TAG_MAX_LEN,
+ .flow_dissect = netc_flow_dissect,
+};
+
+MODULE_DESCRIPTION("DSA tag driver for NXP NETC switch family");
+MODULE_LICENSE("GPL");
+
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_NETC, NETC_NAME);
+module_dsa_tag_driver(netc_netdev_ops);
--
2.34.1
^ permalink raw reply related
* [PATCH v3 net-next 10/14] net: dsa: netc: introduce NXP NETC switch driver for i.MX94
From: Wei Fang @ 2026-03-26 6:29 UTC (permalink / raw)
To: claudiu.manoil, vladimir.oltean, xiaoning.wang, andrew+netdev,
davem, edumazet, kuba, pabeni, robh, krzk+dt, conor+dt,
f.fainelli, frank.li, chleroy, horms, linux, andrew
Cc: netdev, linux-kernel, devicetree, linuxppc-dev, linux-arm-kernel,
imx
In-Reply-To: <20260326062917.3552334-1-wei.fang@nxp.com>
For i.MX94 series, the NETC IP provides full 802.1Q Ethernet switch
functionality, advanced QoS with 8 traffic classes, and a full range of
TSN standards capabilities. The switch has 3 user ports and 1 CPU port,
the CPU port is connected to an internal ENETC. Since the switch and the
internal ENETC are fully integrated within the NETC IP, no back-to-back
MAC connection is required. Instead, a light-weight "pseudo MAC" is used
between the switch and the ENETC. This translates to lower power (less
logic and memory) and lower delay (as there is no serialization delay
across this link).
This patch introduces the initial NETC switch driver. At this stage,
only basic probe and remove functionality is supported. More features
will be supported in the subsequent patches.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
MAINTAINERS | 11 +
drivers/net/dsa/Kconfig | 3 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/netc/Kconfig | 14 +
drivers/net/dsa/netc/Makefile | 3 +
drivers/net/dsa/netc/netc_main.c | 672 ++++++++++++++++++++++++++
drivers/net/dsa/netc/netc_platform.c | 49 ++
drivers/net/dsa/netc/netc_switch.h | 92 ++++
drivers/net/dsa/netc/netc_switch_hw.h | 137 ++++++
9 files changed, 982 insertions(+)
create mode 100644 drivers/net/dsa/netc/Kconfig
create mode 100644 drivers/net/dsa/netc/Makefile
create mode 100644 drivers/net/dsa/netc/netc_main.c
create mode 100644 drivers/net/dsa/netc/netc_platform.c
create mode 100644 drivers/net/dsa/netc/netc_switch.h
create mode 100644 drivers/net/dsa/netc/netc_switch_hw.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a09bf30a057d..fe744320b1e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19083,6 +19083,17 @@ F: Documentation/devicetree/bindings/clock/*imx*
F: drivers/clk/imx/
F: include/dt-bindings/clock/*imx*
+NXP NETC ETHERNET SWITCH DRIVER
+M: Wei Fang <wei.fang@nxp.com>
+R: Clark Wang <xiaoning.wang@nxp.com>
+L: imx@lists.linux.dev
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml
+F: drivers/net/dsa/netc/
+F: include/linux/dsa/tag_netc.h
+F: net/dsa/tag_netc.c
+
NXP NETC TIMER PTP CLOCK DRIVER
M: Wei Fang <wei.fang@nxp.com>
M: Clark Wang <xiaoning.wang@nxp.com>
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 39fb8ead16b5..e9c7a6874791 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -74,8 +74,11 @@ source "drivers/net/dsa/microchip/Kconfig"
source "drivers/net/dsa/mv88e6xxx/Kconfig"
+
source "drivers/net/dsa/mxl862xx/Kconfig"
+source "drivers/net/dsa/netc/Kconfig"
+
source "drivers/net/dsa/ocelot/Kconfig"
source "drivers/net/dsa/qca/Kconfig"
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index f5a463b87ec2..d2975badffc0 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -21,6 +21,7 @@ obj-y += lantiq/
obj-y += microchip/
obj-y += mv88e6xxx/
obj-y += mxl862xx/
+obj-y += netc/
obj-y += ocelot/
obj-y += qca/
obj-y += realtek/
diff --git a/drivers/net/dsa/netc/Kconfig b/drivers/net/dsa/netc/Kconfig
new file mode 100644
index 000000000000..8824d30ed3ea
--- /dev/null
+++ b/drivers/net/dsa/netc/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_NETC_SWITCH
+ tristate "NXP NETC Ethernet switch support"
+ depends on NET_DSA && PCI
+ select NET_DSA_TAG_NETC
+ select FSL_ENETC_MDIO
+ select NXP_NTMP
+ select NXP_NETC_LIB
+ help
+ This driver supports the NXP NETC Ethernet switch, which is embedded
+ as a PCIe function of the NXP NETC IP. But note that this driver does
+ only support switch versions greater than or equal to NETC v4.3.
+
+ If compiled as module (M), the module name is nxp-netc-switch.
diff --git a/drivers/net/dsa/netc/Makefile b/drivers/net/dsa/netc/Makefile
new file mode 100644
index 000000000000..4a5767562574
--- /dev/null
+++ b/drivers/net/dsa/netc/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_NET_DSA_NETC_SWITCH) += nxp-netc-switch.o
+nxp-netc-switch-objs := netc_main.o netc_platform.o
diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c
new file mode 100644
index 000000000000..5828fd3e342e
--- /dev/null
+++ b/drivers/net/dsa/netc/netc_main.c
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * NXP NETC switch driver
+ * Copyright 2025-2026 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/etherdevice.h>
+#include <linux/fsl/enetc_mdio.h>
+#include <linux/if_vlan.h>
+#include <linux/of_mdio.h>
+
+#include "netc_switch.h"
+
+static enum dsa_tag_protocol
+netc_get_tag_protocol(struct dsa_switch *ds, int port,
+ enum dsa_tag_protocol mprot)
+{
+ return DSA_TAG_PROTO_NETC;
+}
+
+static void netc_port_rmw(struct netc_port *np, u32 reg,
+ u32 mask, u32 val)
+{
+ u32 old, new;
+
+ WARN_ON((mask | val) != mask);
+
+ old = netc_port_rd(np, reg);
+ new = (old & ~mask) | val;
+ if (new == old)
+ return;
+
+ netc_port_wr(np, reg, new);
+}
+
+static void netc_mac_port_wr(struct netc_port *np, u32 reg, u32 val)
+{
+ if (is_netc_pseudo_port(np))
+ return;
+
+ netc_port_wr(np, reg, val);
+ if (np->caps.pmac)
+ netc_port_wr(np, reg + NETC_PMAC_OFFSET, val);
+}
+
+static void netc_mac_port_rmw(struct netc_port *np, u32 reg,
+ u32 mask, u32 val)
+{
+ u32 old, new;
+
+ if (is_netc_pseudo_port(np))
+ return;
+
+ WARN_ON((mask | val) != mask);
+
+ old = netc_port_rd(np, reg);
+ new = (old & ~mask) | val;
+ if (new == old)
+ return;
+
+ netc_port_wr(np, reg, new);
+ if (np->caps.pmac)
+ netc_port_wr(np, reg + NETC_PMAC_OFFSET, new);
+}
+
+static void netc_port_get_capability(struct netc_port *np)
+{
+ u32 val;
+
+ val = netc_port_rd(np, NETC_PMCAPR);
+ if (val & PMCAPR_HD)
+ np->caps.half_duplex = true;
+
+ if (FIELD_GET(PMCAPR_FP, val) == FP_SUPPORT)
+ np->caps.pmac = true;
+
+ val = netc_port_rd(np, NETC_PCAPR);
+ if (val & PCAPR_LINK_TYPE)
+ np->caps.pseudo_link = true;
+}
+
+static int netc_port_get_info_from_dt(struct netc_port *np,
+ struct device_node *node,
+ struct device *dev)
+{
+ if (of_find_property(node, "clock-names", NULL)) {
+ np->ref_clk = devm_get_clk_from_child(dev, node, "ref");
+ if (IS_ERR(np->ref_clk)) {
+ dev_err(dev, "Port %d cannot get reference clock\n",
+ np->dp->index);
+ return PTR_ERR(np->ref_clk);
+ }
+ }
+
+ return 0;
+}
+
+static int netc_port_create_emdio_bus(struct netc_port *np,
+ struct device_node *node)
+{
+ struct netc_switch *priv = np->switch_priv;
+ struct enetc_mdio_priv *mdio_priv;
+ struct device *dev = priv->dev;
+ struct enetc_hw *hw;
+ struct mii_bus *bus;
+ int err;
+
+ hw = enetc_hw_alloc(dev, np->iobase);
+ if (IS_ERR(hw))
+ return dev_err_probe(dev, PTR_ERR(hw),
+ "Failed to allocate enetc_hw\n");
+
+ bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
+ if (!bus)
+ return -ENOMEM;
+
+ bus->name = "NXP NETC switch external MDIO Bus";
+ bus->read = enetc_mdio_read_c22;
+ bus->write = enetc_mdio_write_c22;
+ bus->read_c45 = enetc_mdio_read_c45;
+ bus->write_c45 = enetc_mdio_write_c45;
+ bus->parent = dev;
+ mdio_priv = bus->priv;
+ mdio_priv->hw = hw;
+ mdio_priv->mdio_base = NETC_EMDIO_BASE;
+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-p%d-emdio",
+ dev_name(dev), np->dp->index);
+
+ err = devm_of_mdiobus_register(dev, bus, node);
+ if (err)
+ return dev_err_probe(dev, err,
+ "Cannot register EMDIO bus\n");
+
+ np->emdio = bus;
+
+ return 0;
+}
+
+static int netc_port_create_mdio_bus(struct netc_port *np,
+ struct device_node *node)
+{
+ struct device_node *mdio_node;
+ int err;
+
+ mdio_node = of_get_child_by_name(node, "mdio");
+ if (mdio_node) {
+ err = netc_port_create_emdio_bus(np, mdio_node);
+ of_node_put(mdio_node);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int netc_init_switch_id(struct netc_switch *priv)
+{
+ struct netc_switch_regs *regs = &priv->regs;
+ struct dsa_switch *ds = priv->ds;
+
+ /* The value of 0 is reserved for the VEPA switch and cannot
+ * be used.
+ */
+ if (ds->index > SWCR_SWID || !ds->index) {
+ dev_err(priv->dev, "Switch index %d out of range\n",
+ ds->index);
+ return -ERANGE;
+ }
+
+ netc_base_wr(regs, NETC_SWCR, ds->index);
+
+ return 0;
+}
+
+static int netc_init_all_ports(struct netc_switch *priv)
+{
+ struct device *dev = priv->dev;
+ struct netc_port *np;
+ struct dsa_port *dp;
+ int err;
+
+ priv->ports = devm_kcalloc(dev, priv->info->num_ports,
+ sizeof(struct netc_port *),
+ GFP_KERNEL);
+ if (!priv->ports)
+ return -ENOMEM;
+
+ /* Some DSA interfaces may set the port even it is disabled, such
+ * as .port_disable(), .port_stp_state_set() and so on. To avoid
+ * crash caused by accessing NULL port pointer, each port is
+ * allocated its own memory. Otherwise, we need to check whether
+ * the port pointer is NULL in these interfaces. The latter is
+ * difficult for us to cover.
+ */
+ for (int i = 0; i < priv->info->num_ports; i++) {
+ np = devm_kzalloc(dev, sizeof(*np), GFP_KERNEL);
+ if (!np)
+ return -ENOMEM;
+
+ np->switch_priv = priv;
+ np->iobase = priv->regs.port + PORT_IOBASE(i);
+ netc_port_get_capability(np);
+ priv->ports[i] = np;
+ }
+
+ dsa_switch_for_each_available_port(dp, priv->ds) {
+ np = priv->ports[dp->index];
+ np->dp = dp;
+ err = netc_port_get_info_from_dt(np, dp->dn, dev);
+ if (err)
+ return err;
+
+ if (dsa_port_is_user(dp)) {
+ err = netc_port_create_mdio_bus(np, dp->dn);
+ if (err) {
+ dev_err(dev, "Failed to create MDIO bus\n");
+ return err;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static void netc_init_ntmp_tbl_versions(struct netc_switch *priv)
+{
+ struct ntmp_user *ntmp = &priv->ntmp;
+
+ /* All tables default to version 0 */
+ memset(&ntmp->tbl, 0, sizeof(ntmp->tbl));
+}
+
+static int netc_init_all_cbdrs(struct netc_switch *priv)
+{
+ struct netc_switch_regs *regs = &priv->regs;
+ struct ntmp_user *ntmp = &priv->ntmp;
+ int i, err;
+
+ ntmp->cbdr_num = NETC_CBDR_NUM;
+ ntmp->dev = priv->dev;
+ ntmp->ring = devm_kcalloc(ntmp->dev, ntmp->cbdr_num,
+ sizeof(struct netc_cbdr),
+ GFP_KERNEL);
+ if (!ntmp->ring)
+ return -ENOMEM;
+
+ for (i = 0; i < ntmp->cbdr_num; i++) {
+ struct netc_cbdr *cbdr = &ntmp->ring[i];
+ struct netc_cbdr_regs cbdr_regs;
+
+ cbdr_regs.pir = regs->base + NETC_CBDRPIR(i);
+ cbdr_regs.cir = regs->base + NETC_CBDRCIR(i);
+ cbdr_regs.mr = regs->base + NETC_CBDRMR(i);
+ cbdr_regs.bar0 = regs->base + NETC_CBDRBAR0(i);
+ cbdr_regs.bar1 = regs->base + NETC_CBDRBAR1(i);
+ cbdr_regs.lenr = regs->base + NETC_CBDRLENR(i);
+
+ err = ntmp_init_cbdr(cbdr, ntmp->dev, &cbdr_regs);
+ if (err)
+ goto free_cbdrs;
+ }
+
+ return 0;
+
+free_cbdrs:
+ for (i--; i >= 0; i--)
+ ntmp_free_cbdr(&ntmp->ring[i]);
+
+ return err;
+}
+
+static void netc_remove_all_cbdrs(struct netc_switch *priv)
+{
+ struct ntmp_user *ntmp = &priv->ntmp;
+
+ for (int i = 0; i < NETC_CBDR_NUM; i++)
+ ntmp_free_cbdr(&ntmp->ring[i]);
+}
+
+static int netc_init_ntmp_user(struct netc_switch *priv)
+{
+ netc_init_ntmp_tbl_versions(priv);
+
+ return netc_init_all_cbdrs(priv);
+}
+
+static void netc_free_ntmp_user(struct netc_switch *priv)
+{
+ netc_remove_all_cbdrs(priv);
+}
+
+static void netc_switch_dos_default_config(struct netc_switch *priv)
+{
+ struct netc_switch_regs *regs = &priv->regs;
+ u32 val;
+
+ val = DOSL2CR_SAMEADDR | DOSL2CR_MSAMCC;
+ netc_base_wr(regs, NETC_DOSL2CR, val);
+
+ val = DOSL3CR_SAMEADDR | DOSL3CR_IPSAMCC;
+ netc_base_wr(regs, NETC_DOSL3CR, val);
+}
+
+static void netc_switch_vfht_default_config(struct netc_switch *priv)
+{
+ struct netc_switch_regs *regs = &priv->regs;
+ u32 val;
+
+ val = netc_base_rd(regs, NETC_VFHTDECR2);
+
+ /* if no match is found in the VLAN Filter table, then VFHTDECR2[MLO]
+ * will take effect. VFHTDECR2[MLO] is set to "Software MAC learning
+ * secure" by default. Notice BPCR[MLO] will override VFHTDECR2[MLO]
+ * if its value is not zero.
+ */
+ val = u32_replace_bits(val, MLO_SW_SEC, VFHTDECR2_MLO);
+ val = u32_replace_bits(val, MFO_NO_MATCH_DISCARD, VFHTDECR2_MFO);
+ netc_base_wr(regs, NETC_VFHTDECR2, val);
+}
+
+static void netc_port_set_max_frame_size(struct netc_port *np,
+ u32 max_frame_size)
+{
+ netc_mac_port_wr(np, NETC_PM_MAXFRM(0),
+ PM_MAXFRAM & max_frame_size);
+}
+
+static void netc_switch_fixed_config(struct netc_switch *priv)
+{
+ netc_switch_dos_default_config(priv);
+ netc_switch_vfht_default_config(priv);
+}
+
+static void netc_port_set_tc_max_sdu(struct netc_port *np,
+ int tc, u32 max_sdu)
+{
+ u32 val = max_sdu & PTCTMSDUR_MAXSDU;
+
+ val |= FIELD_PREP(PTCTMSDUR_SDU_TYPE, SDU_TYPE_MPDU);
+ netc_port_wr(np, NETC_PTCTMSDUR(tc), val);
+}
+
+static void netc_port_set_all_tc_msdu(struct netc_port *np)
+{
+ for (int tc = 0; tc < NETC_TC_NUM; tc++)
+ netc_port_set_tc_max_sdu(np, tc, NETC_MAX_FRAME_LEN);
+}
+
+static void netc_port_set_mlo(struct netc_port *np, enum netc_mlo mlo)
+{
+ netc_port_rmw(np, NETC_BPCR, BPCR_MLO, FIELD_PREP(BPCR_MLO, mlo));
+}
+
+static void netc_port_fixed_config(struct netc_port *np)
+{
+ /* Default IPV and DR setting */
+ netc_port_rmw(np, NETC_PQOSMR, PQOSMR_VS | PQOSMR_VE,
+ PQOSMR_VS | PQOSMR_VE);
+
+ /* Enable L2 and L3 DOS */
+ netc_port_rmw(np, NETC_PCR, PCR_L2DOSE | PCR_L3DOSE,
+ PCR_L2DOSE | PCR_L3DOSE);
+}
+
+static void netc_port_default_config(struct netc_port *np)
+{
+ netc_port_fixed_config(np);
+
+ /* Default VLAN unaware */
+ netc_port_rmw(np, NETC_BPDVR, BPDVR_RXVAM, BPDVR_RXVAM);
+
+ if (dsa_port_is_cpu(np->dp))
+ /* For CPU port, source port pruning is disabled and
+ * hardware MAC learning is enabled by default.
+ */
+ netc_port_rmw(np, NETC_BPCR, BPCR_SRCPRND | BPCR_MLO,
+ BPCR_SRCPRND | FIELD_PREP(BPCR_MLO, MLO_HW));
+ else
+ netc_port_set_mlo(np, MLO_DISABLE);
+
+ netc_port_set_max_frame_size(np, NETC_MAX_FRAME_LEN);
+ netc_port_set_all_tc_msdu(np);
+ netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_TX_EN,
+ PM_CMD_CFG_TX_EN);
+ netc_port_rmw(np, NETC_POR, PCR_TXDIS, 0);
+}
+
+static int netc_setup(struct dsa_switch *ds)
+{
+ struct netc_switch *priv = ds->priv;
+ struct dsa_port *dp;
+ int err;
+
+ err = netc_init_switch_id(priv);
+ if (err)
+ return err;
+
+ err = netc_init_all_ports(priv);
+ if (err)
+ return err;
+
+ err = netc_init_ntmp_user(priv);
+ if (err)
+ return err;
+
+ netc_switch_fixed_config(priv);
+
+ /* default setting for ports */
+ dsa_switch_for_each_available_port(dp, ds)
+ netc_port_default_config(priv->ports[dp->index]);
+
+ return 0;
+}
+
+static void netc_teardown(struct dsa_switch *ds)
+{
+ struct netc_switch *priv = ds->priv;
+
+ netc_free_ntmp_user(priv);
+}
+
+static struct device_node *netc_get_switch_ports(struct device_node *node)
+{
+ struct device_node *ports;
+
+ ports = of_get_child_by_name(node, "ports");
+ if (!ports)
+ ports = of_get_child_by_name(node, "ethernet-ports");
+
+ return ports;
+}
+
+static bool netc_port_is_emdio_consumer(struct device_node *node)
+{
+ struct device_node *mdio_node;
+
+ /* If the port node has phy-handle property and it does
+ * not contain a mdio child node, then the port is the
+ * EMDIO consumer.
+ */
+ mdio_node = of_get_child_by_name(node, "mdio");
+ if (!mdio_node)
+ return true;
+
+ of_node_put(mdio_node);
+
+ return false;
+}
+
+/* Currently, phylink_of_phy_connect() is called by dsa_user_create(),
+ * so if the switch uses the external MDIO controller (like the EMDIO
+ * function) to manage the external PHYs. The MDIO bus may not be
+ * created when phylink_of_phy_connect() is called, so it will return
+ * an error and cause the switch driver to fail to probe.
+ * This workaround can be removed when DSA phylink_of_phy_connect()
+ * calls are moved from probe() to ndo_open().
+ */
+static int netc_switch_check_emdio_is_ready(struct device *dev)
+{
+ struct device_node *ports, *phy_node;
+ struct phy_device *phydev;
+ int err = 0;
+
+ ports = netc_get_switch_ports(dev->of_node);
+ if (!ports)
+ return 0;
+
+ for_each_available_child_of_node_scoped(ports, child) {
+ /* If the node does not have phy-handle property, then
+ * the port does not connect to a PHY, so the port is
+ * not the EMDIO consumer.
+ */
+ phy_node = of_parse_phandle(child, "phy-handle", 0);
+ if (!phy_node)
+ continue;
+
+ if (!netc_port_is_emdio_consumer(child)) {
+ of_node_put(phy_node);
+ continue;
+ }
+
+ phydev = of_phy_find_device(phy_node);
+ of_node_put(phy_node);
+ if (!phydev) {
+ err = -EPROBE_DEFER;
+ goto out;
+ }
+
+ put_device(&phydev->mdio.dev);
+ }
+
+out:
+ of_node_put(ports);
+
+ return err;
+}
+
+static int netc_switch_pci_init(struct pci_dev *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct netc_switch_regs *regs;
+ struct netc_switch *priv;
+ int err;
+
+ pcie_flr(pdev);
+ err = pci_enable_device_mem(pdev);
+ if (err)
+ return dev_err_probe(dev, err, "Failed to enable device\n");
+
+ /* The command BD rings and NTMP tables need DMA. No need to check
+ * the return value, because it never returns fail when the mask is
+ * DMA_BIT_MASK(64), see dma-api-howto.rst.
+ */
+ dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ err = pci_request_mem_regions(pdev, KBUILD_MODNAME);
+ if (err) {
+ dev_err(dev, "Failed to request memory regions, err: %pe\n",
+ ERR_PTR(err));
+ goto disable_pci_device;
+ }
+
+ pci_set_master(pdev);
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ err = -ENOMEM;
+ goto release_mem_regions;
+ }
+
+ priv->pdev = pdev;
+ priv->dev = dev;
+
+ regs = &priv->regs;
+ regs->base = pci_ioremap_bar(pdev, NETC_REGS_BAR);
+ if (!regs->base) {
+ err = -ENXIO;
+ dev_err(dev, "pci_ioremap_bar() failed\n");
+ goto release_mem_regions;
+ }
+
+ regs->port = regs->base + NETC_REGS_PORT_BASE;
+ regs->global = regs->base + NETC_REGS_GLOBAL_BASE;
+ pci_set_drvdata(pdev, priv);
+
+ return 0;
+
+release_mem_regions:
+ pci_release_mem_regions(pdev);
+disable_pci_device:
+ pci_disable_device(pdev);
+
+ return err;
+}
+
+static void netc_switch_pci_destroy(struct pci_dev *pdev)
+{
+ struct netc_switch *priv = pci_get_drvdata(pdev);
+
+ iounmap(priv->regs.base);
+ pci_release_mem_regions(pdev);
+ pci_disable_device(pdev);
+}
+
+static void netc_switch_get_ip_revision(struct netc_switch *priv)
+{
+ struct netc_switch_regs *regs = &priv->regs;
+ u32 val = netc_glb_rd(regs, NETC_IPBRR0);
+
+ priv->revision = val & IPBRR0_IP_REV;
+}
+
+static const struct dsa_switch_ops netc_switch_ops = {
+ .get_tag_protocol = netc_get_tag_protocol,
+ .setup = netc_setup,
+ .teardown = netc_teardown,
+};
+
+static int netc_switch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct device_node *node = dev_of_node(&pdev->dev);
+ struct device *dev = &pdev->dev;
+ struct netc_switch *priv;
+ struct dsa_switch *ds;
+ int err;
+
+ if (!node)
+ return dev_err_probe(dev, -ENODEV,
+ "No DT bindings, skipping\n");
+
+ err = netc_switch_check_emdio_is_ready(dev);
+ if (err)
+ return err;
+
+ err = netc_switch_pci_init(pdev);
+ if (err)
+ return err;
+
+ priv = pci_get_drvdata(pdev);
+ netc_switch_get_ip_revision(priv);
+
+ err = netc_switch_platform_probe(priv);
+ if (err)
+ goto destroy_netc_switch;
+
+ ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
+ if (!ds) {
+ err = -ENOMEM;
+ goto destroy_netc_switch;
+ }
+
+ ds->dev = dev;
+ ds->num_ports = priv->info->num_ports;
+ ds->num_tx_queues = NETC_TC_NUM;
+ ds->ops = &netc_switch_ops;
+ ds->priv = priv;
+
+ priv->ds = ds;
+
+ err = dsa_register_switch(ds);
+ if (err) {
+ dev_err_probe(dev, err, "Failed to register DSA switch\n");
+ goto destroy_netc_switch;
+ }
+
+ return 0;
+
+destroy_netc_switch:
+ netc_switch_pci_destroy(pdev);
+
+ return err;
+}
+
+static void netc_switch_remove(struct pci_dev *pdev)
+{
+ struct netc_switch *priv = pci_get_drvdata(pdev);
+
+ if (!priv)
+ return;
+
+ dsa_unregister_switch(priv->ds);
+ netc_switch_pci_destroy(pdev);
+}
+
+static void netc_switch_shutdown(struct pci_dev *pdev)
+{
+ struct netc_switch *priv = pci_get_drvdata(pdev);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(priv->ds);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id netc_switch_ids[] = {
+ { PCI_DEVICE(NETC_SWITCH_VENDOR_ID, NETC_SWITCH_DEVICE_ID) },
+ { }
+};
+MODULE_DEVICE_TABLE(pci, netc_switch_ids);
+
+static struct pci_driver netc_switch_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = netc_switch_ids,
+ .probe = netc_switch_probe,
+ .remove = netc_switch_remove,
+ .shutdown = netc_switch_shutdown,
+};
+module_pci_driver(netc_switch_driver);
+
+MODULE_DESCRIPTION("NXP NETC Switch driver");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/dsa/netc/netc_platform.c b/drivers/net/dsa/netc/netc_platform.c
new file mode 100644
index 000000000000..abd599ea9c8d
--- /dev/null
+++ b/drivers/net/dsa/netc/netc_platform.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * NXP NETC switch driver
+ * Copyright 2025-2026 NXP
+ */
+
+#include "netc_switch.h"
+
+struct netc_switch_platform {
+ u16 revision;
+ const struct netc_switch_info *info;
+};
+
+static const struct netc_switch_info imx94_info = {
+ .num_ports = 4,
+};
+
+static const struct netc_switch_platform netc_platforms[] = {
+ { .revision = NETC_SWITCH_REV_4_3, .info = &imx94_info, },
+ { }
+};
+
+static const struct netc_switch_info *
+netc_switch_get_info(struct netc_switch *priv)
+{
+ int i;
+
+ /* Matching based on IP revision */
+ for (i = 0; i < ARRAY_SIZE(netc_platforms); i++) {
+ if (priv->revision == netc_platforms[i].revision)
+ return netc_platforms[i].info;
+ }
+
+ return NULL;
+}
+
+int netc_switch_platform_probe(struct netc_switch *priv)
+{
+ const struct netc_switch_info *info = netc_switch_get_info(priv);
+
+ if (!info) {
+ dev_err(priv->dev, "Cannot find switch platform info\n");
+ return -EINVAL;
+ }
+
+ priv->info = info;
+
+ return 0;
+}
diff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h
new file mode 100644
index 000000000000..dac19bfba02b
--- /dev/null
+++ b/drivers/net/dsa/netc/netc_switch.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+#ifndef _NETC_SWITCH_H
+#define _NETC_SWITCH_H
+
+#include <linux/dsa/tag_netc.h>
+#include <linux/fsl/netc_global.h>
+#include <linux/fsl/ntmp.h>
+#include <linux/of_device.h>
+#include <linux/of_net.h>
+#include <linux/pci.h>
+
+#include "netc_switch_hw.h"
+
+#define NETC_REGS_BAR 0
+#define NETC_MSIX_TBL_BAR 2
+#define NETC_REGS_PORT_BASE 0x4000
+/* register block size per port */
+#define NETC_REGS_PORT_SIZE 0x4000
+#define PORT_IOBASE(p) (NETC_REGS_PORT_SIZE * (p))
+#define NETC_REGS_GLOBAL_BASE 0x70000
+
+#define NETC_SWITCH_REV_4_3 0x0403
+
+#define NETC_TC_NUM 8
+#define NETC_CBDR_NUM 2
+
+#define NETC_MAX_FRAME_LEN 9600
+
+struct netc_switch;
+
+struct netc_switch_info {
+ u32 num_ports;
+};
+
+struct netc_port_caps {
+ u32 half_duplex:1; /* indicates whether the port support half-duplex */
+ u32 pmac:1; /* indicates whether the port has preemption MAC */
+ u32 pseudo_link:1;
+};
+
+struct netc_port {
+ void __iomem *iobase;
+ struct netc_switch *switch_priv;
+ struct netc_port_caps caps;
+ struct dsa_port *dp;
+ struct clk *ref_clk; /* RGMII/RMII reference clock */
+ struct mii_bus *emdio;
+};
+
+struct netc_switch_regs {
+ void __iomem *base;
+ void __iomem *port;
+ void __iomem *global;
+};
+
+struct netc_switch {
+ struct pci_dev *pdev;
+ struct device *dev;
+ struct dsa_switch *ds;
+ u16 revision;
+
+ const struct netc_switch_info *info;
+ struct netc_switch_regs regs;
+ struct netc_port **ports;
+
+ struct ntmp_user ntmp;
+};
+
+/* Write/Read Switch base registers */
+#define netc_base_rd(r, o) netc_read((r)->base + (o))
+#define netc_base_wr(r, o, v) netc_write((r)->base + (o), v)
+
+/* Write/Read registers of Switch Port (including pseudo MAC port) */
+#define netc_port_rd(p, o) netc_read((p)->iobase + (o))
+#define netc_port_wr(p, o, v) netc_write((p)->iobase + (o), v)
+
+/* Write/Read Switch global registers */
+#define netc_glb_rd(r, o) netc_read((r)->global + (o))
+#define netc_glb_wr(r, o, v) netc_write((r)->global + (o), v)
+
+static inline bool is_netc_pseudo_port(struct netc_port *np)
+{
+ return np->caps.pseudo_link;
+}
+
+int netc_switch_platform_probe(struct netc_switch *priv);
+
+#endif
diff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h
new file mode 100644
index 000000000000..11cb124ce4bf
--- /dev/null
+++ b/drivers/net/dsa/netc/netc_switch_hw.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+#ifndef _NETC_SWITCH_HW_H
+#define _NETC_SWITCH_HW_H
+
+#include <linux/bitops.h>
+
+#define NETC_SWITCH_VENDOR_ID 0x1131
+#define NETC_SWITCH_DEVICE_ID 0xeef2
+
+/* Definition of Switch base registers */
+#define NETC_CBDRMR(a) (0x0800 + (a) * 0x30)
+#define NETC_CBDRBAR0(a) (0x0810 + (a) * 0x30)
+#define NETC_CBDRBAR1(a) (0x0814 + (a) * 0x30)
+#define NETC_CBDRPIR(a) (0x0818 + (a) * 0x30)
+#define NETC_CBDRCIR(a) (0x081c + (a) * 0x30)
+#define NETC_CBDRLENR(a) (0x0820 + (a) * 0x30)
+
+#define NETC_SWCR 0x1018
+#define SWCR_SWID GENMASK(2, 0)
+
+#define NETC_DOSL2CR 0x1220
+#define DOSL2CR_SAMEADDR BIT(0)
+#define DOSL2CR_MSAMCC BIT(1)
+
+#define NETC_DOSL3CR 0x1224
+#define DOSL3CR_SAMEADDR BIT(0)
+#define DOSL3CR_IPSAMCC BIT(1)
+
+#define NETC_VFHTDECR1 0x2014
+#define NETC_VFHTDECR2 0x2018
+#define VFHTDECR2_ET_PORT(a) BIT((a))
+#define VFHTDECR2_MLO GENMASK(26, 24)
+#define VFHTDECR2_MFO GENMASK(28, 27)
+
+/* Definition of Switch port registers */
+#define NETC_PCAPR 0x0000
+#define PCAPR_LINK_TYPE BIT(4)
+#define PCAPR_NUM_TC GENMASK(15, 12)
+#define PCAPR_NUM_Q GENMASK(19, 16)
+#define PCAPR_NUM_CG GENMASK(27, 24)
+#define PCAPR_TGS BIT(28)
+#define PCAPR_CBS BIT(29)
+
+#define NETC_PMCAPR 0x0004
+#define PMCAPR_HD BIT(8)
+#define PMCAPR_FP GENMASK(10, 9)
+#define FP_SUPPORT 2
+
+#define NETC_PCR 0x0010
+#define PCR_HDR_FMT BIT(0)
+#define PCR_NS_TAG_PORT BIT(3)
+#define PCR_L2DOSE BIT(4)
+#define PCR_L3DOSE BIT(5)
+#define PCR_TIMER_CS BIT(8)
+#define PCR_PSPEED GENMASK(29, 16)
+#define PSPEED_SET_VAL(s) FIELD_PREP(PCR_PSPEED, ((s) / 10 - 1))
+
+#define NETC_PQOSMR 0x0054
+#define PQOSMR_VS BIT(0)
+#define PQOSMR_VE BIT(1)
+#define PQOSMR_DDR GENMASK(3, 2)
+#define PQOSMR_DIPV GENMASK(6, 4)
+#define PQOSMR_VQMP GENMASK(19, 16)
+#define PQOSMR_QVMP GENMASK(23, 20)
+
+#define NETC_POR 0x100
+#define PCR_TXDIS BIT(0)
+#define PCR_RXDIS BIT(1)
+
+#define NETC_PTCTMSDUR(a) (0x208 + (a) * 0x20)
+#define PTCTMSDUR_MAXSDU GENMASK(15, 0)
+#define PTCTMSDUR_SDU_TYPE GENMASK(17, 16)
+#define SDU_TYPE_PPDU 0
+#define SDU_TYPE_MPDU 1
+#define SDU_TYPE_MSDU 2
+
+#define NETC_BPCR 0x500
+#define BPCR_DYN_LIMIT GENMASK(15, 0)
+#define BPCR_MLO GENMASK(22, 20)
+#define BPCR_UUCASTE BIT(24)
+#define BPCR_UMCASTE BIT(25)
+#define BPCR_MCASTE BIT(26)
+#define BPCR_BCASTE BIT(27)
+#define BPCR_STAMVD BIT(28)
+#define BPCR_SRCPRND BIT(29)
+
+/* MAC learning options, see BPCR[MLO], VFHTDECR2[MLO] and
+ * VLAN Filter Table CFGE_DATA[MLO]
+ */
+enum netc_mlo {
+ MLO_NOT_OVERRIDE = 0,
+ MLO_DISABLE,
+ MLO_HW,
+ MLO_SW_SEC,
+ MLO_SW_UNSEC,
+ MLO_DISABLE_SMAC,
+};
+
+/* MAC forwarding options, see VFHTDECR2[MFO] and VLAN
+ * Filter Table CFGE_DATA[MFO]
+ */
+enum netc_mfo {
+ MFO_NO_FDB_LOOKUP = 1,
+ MFO_NO_MATCH_FLOOD,
+ MFO_NO_MATCH_DISCARD,
+};
+
+#define NETC_BPDVR 0x510
+#define BPDVR_VID GENMASK(11, 0)
+#define BPDVR_DEI BIT(12)
+#define BPDVR_PCP GENMASK(15, 13)
+#define BPDVR_TPID BIT(16)
+#define BPDVR_RXTAGA GENMASK(23, 20)
+#define BPDVR_RXVAM BIT(24)
+#define BPDVR_TXTAGA GENMASK(26, 25)
+
+/* Definition of Switch ethernet MAC port registers */
+#define NETC_PMAC_OFFSET 0x400
+#define NETC_PM_CMD_CFG(a) (0x1008 + (a) * 0x400)
+#define PM_CMD_CFG_TX_EN BIT(0)
+#define PM_CMD_CFG_RX_EN BIT(1)
+
+#define NETC_PM_MAXFRM(a) (0x1014 + (a) * 0x400)
+#define PM_MAXFRAM GENMASK(15, 0)
+
+#define NETC_PEMDIOCR 0x1c00
+#define NETC_EMDIO_BASE NETC_PEMDIOCR
+
+/* Definition of global registers (read only) */
+#define NETC_IPBRR0 0x0bf8
+#define IPBRR0_IP_REV GENMASK(15, 0)
+
+#endif
--
2.34.1
^ permalink raw reply related
* [PATCH v3 net-next 11/14] net: dsa: netc: add phylink MAC operations
From: Wei Fang @ 2026-03-26 6:29 UTC (permalink / raw)
To: claudiu.manoil, vladimir.oltean, xiaoning.wang, andrew+netdev,
davem, edumazet, kuba, pabeni, robh, krzk+dt, conor+dt,
f.fainelli, frank.li, chleroy, horms, linux, andrew
Cc: netdev, linux-kernel, devicetree, linuxppc-dev, linux-arm-kernel,
imx
In-Reply-To: <20260326062917.3552334-1-wei.fang@nxp.com>
Different versions of NETC switches have different numbers of ports and
MAC capabilities, so add .phylink_get_caps() to struct netc_switch_info,
so that each version of the NETC switch can implement its own callback
to obtain MAC capabilities. In addition, related interfaces of struct
phylink_mac_ops are added, such as .mac_config(), .mac_link_up(), and
.mac_link_down().
Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
drivers/net/dsa/netc/netc_main.c | 179 ++++++++++++++++++++++++++
drivers/net/dsa/netc/netc_platform.c | 40 ++++++
drivers/net/dsa/netc/netc_switch.h | 4 +
drivers/net/dsa/netc/netc_switch_hw.h | 21 +++
4 files changed, 244 insertions(+)
diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c
index 5828fd3e342e..f11f5d0f6a6d 100644
--- a/drivers/net/dsa/netc/netc_main.c
+++ b/drivers/net/dsa/netc/netc_main.c
@@ -569,10 +569,188 @@ static void netc_switch_get_ip_revision(struct netc_switch *priv)
priv->revision = val & IPBRR0_IP_REV;
}
+static void netc_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+{
+ struct netc_switch *priv = ds->priv;
+
+ priv->info->phylink_get_caps(port, config);
+}
+
+static void netc_port_set_mac_mode(struct netc_port *np,
+ unsigned int mode,
+ phy_interface_t phy_mode)
+{
+ u32 mask = PM_IF_MODE_IFMODE | PM_IF_MODE_REVMII;
+ u32 val = 0;
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ val |= IFMODE_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ val |= IFMODE_RMII;
+ break;
+ case PHY_INTERFACE_MODE_REVMII:
+ val |= PM_IF_MODE_REVMII;
+ fallthrough;
+ case PHY_INTERFACE_MODE_MII:
+ val |= IFMODE_MII;
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ val |= IFMODE_SGMII;
+ break;
+ default:
+ break;
+ }
+
+ netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);
+}
+
+static void netc_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+
+ netc_port_set_mac_mode(NETC_PORT(dp->ds, dp->index), mode,
+ state->interface);
+}
+
+static void netc_port_set_speed(struct netc_port *np, int speed)
+{
+ netc_port_rmw(np, NETC_PCR, PCR_PSPEED, PSPEED_SET_VAL(speed));
+}
+
+static void netc_port_set_rgmii_mac(struct netc_port *np,
+ int speed, int duplex)
+{
+ u32 mask, val;
+
+ mask = PM_IF_MODE_SSP | PM_IF_MODE_HD | PM_IF_MODE_M10;
+
+ switch (speed) {
+ default:
+ case SPEED_1000:
+ val = FIELD_PREP(PM_IF_MODE_SSP, SSP_1G);
+ break;
+ case SPEED_100:
+ val = FIELD_PREP(PM_IF_MODE_SSP, SSP_100M);
+ break;
+ case SPEED_10:
+ val = FIELD_PREP(PM_IF_MODE_SSP, SSP_10M);
+ break;
+ }
+
+ if (duplex != DUPLEX_FULL)
+ val |= PM_IF_MODE_HD;
+
+ netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);
+}
+
+static void netc_port_set_rmii_mii_mac(struct netc_port *np,
+ int speed, int duplex)
+{
+ u32 mask, val = 0;
+
+ mask = PM_IF_MODE_SSP | PM_IF_MODE_HD | PM_IF_MODE_M10;
+
+ if (speed == SPEED_10)
+ val |= PM_IF_MODE_M10;
+
+ if (duplex != DUPLEX_FULL)
+ val |= PM_IF_MODE_HD;
+
+ netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);
+}
+
+static void netc_port_mac_rx_enable(struct netc_port *np)
+{
+ netc_port_rmw(np, NETC_POR, PCR_RXDIS, 0);
+ netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN,
+ PM_CMD_CFG_RX_EN);
+}
+
+static void netc_port_wait_rx_empty(struct netc_port *np, int mac)
+{
+ u32 val;
+
+ if (read_poll_timeout(netc_port_rd, val, val & PM_IEVENT_RX_EMPTY,
+ 100, 10000, false, np, NETC_PM_IEVENT(mac)))
+ dev_warn(np->switch_priv->dev,
+ "MAC %d of swp%d RX is not empty\n", mac,
+ np->dp->index);
+}
+
+static void netc_port_mac_rx_graceful_stop(struct netc_port *np)
+{
+ u32 val;
+
+ if (is_netc_pseudo_port(np))
+ goto check_rx_busy;
+
+ if (np->caps.pmac) {
+ netc_port_rmw(np, NETC_PM_CMD_CFG(1), PM_CMD_CFG_RX_EN, 0);
+ netc_port_wait_rx_empty(np, 1);
+ }
+
+ netc_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN, 0);
+ netc_port_wait_rx_empty(np, 0);
+
+check_rx_busy:
+ if (read_poll_timeout(netc_port_rd, val, !(val & PSR_RX_BUSY),
+ 100, 10000, false, np, NETC_PSR))
+ dev_warn(np->switch_priv->dev, "swp%d RX is busy\n",
+ np->dp->index);
+
+ netc_port_rmw(np, NETC_POR, PCR_RXDIS, PCR_RXDIS);
+}
+
+static void netc_mac_link_up(struct phylink_config *config,
+ struct phy_device *phy, unsigned int mode,
+ phy_interface_t interface, int speed,
+ int duplex, bool tx_pause, bool rx_pause)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct netc_port *np;
+
+ np = NETC_PORT(dp->ds, dp->index);
+ netc_port_set_speed(np, speed);
+
+ if (phy_interface_mode_is_rgmii(interface))
+ netc_port_set_rgmii_mac(np, speed, duplex);
+
+ if (interface == PHY_INTERFACE_MODE_RMII ||
+ interface == PHY_INTERFACE_MODE_REVMII ||
+ interface == PHY_INTERFACE_MODE_MII)
+ netc_port_set_rmii_mii_mac(np, speed, duplex);
+
+ netc_port_mac_rx_enable(np);
+}
+
+static void netc_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+
+ netc_port_mac_rx_graceful_stop(NETC_PORT(dp->ds, dp->index));
+}
+
+static const struct phylink_mac_ops netc_phylink_mac_ops = {
+ .mac_config = netc_mac_config,
+ .mac_link_up = netc_mac_link_up,
+ .mac_link_down = netc_mac_link_down,
+};
+
static const struct dsa_switch_ops netc_switch_ops = {
.get_tag_protocol = netc_get_tag_protocol,
.setup = netc_setup,
.teardown = netc_teardown,
+ .phylink_get_caps = netc_phylink_get_caps,
};
static int netc_switch_probe(struct pci_dev *pdev,
@@ -613,6 +791,7 @@ static int netc_switch_probe(struct pci_dev *pdev,
ds->num_ports = priv->info->num_ports;
ds->num_tx_queues = NETC_TC_NUM;
ds->ops = &netc_switch_ops;
+ ds->phylink_mac_ops = &netc_phylink_mac_ops;
ds->priv = priv;
priv->ds = ds;
diff --git a/drivers/net/dsa/netc/netc_platform.c b/drivers/net/dsa/netc/netc_platform.c
index abd599ea9c8d..8d3fb5151902 100644
--- a/drivers/net/dsa/netc/netc_platform.c
+++ b/drivers/net/dsa/netc/netc_platform.c
@@ -11,8 +11,48 @@ struct netc_switch_platform {
const struct netc_switch_info *info;
};
+static void imx94_switch_phylink_get_caps(int port,
+ struct phylink_config *config)
+{
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_1000FD;
+
+ switch (port) {
+ case 0 ... 1:
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ config->mac_capabilities |= MAC_2500FD;
+ fallthrough;
+ case 2:
+ config->mac_capabilities |= MAC_10 | MAC_100;
+ __set_bit(PHY_INTERFACE_MODE_MII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_RMII,
+ config->supported_interfaces);
+ if (port == 2)
+ __set_bit(PHY_INTERFACE_MODE_REVMII,
+ config->supported_interfaces);
+
+ phy_interface_set_rgmii(config->supported_interfaces);
+ break;
+ case 3: /* CPU port */
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ config->mac_capabilities |= MAC_10FD | MAC_100FD |
+ MAC_2500FD;
+ break;
+ default:
+ break;
+ }
+}
+
static const struct netc_switch_info imx94_info = {
.num_ports = 4,
+ .phylink_get_caps = imx94_switch_phylink_get_caps,
};
static const struct netc_switch_platform netc_platforms[] = {
diff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h
index dac19bfba02b..eb65c36ecead 100644
--- a/drivers/net/dsa/netc/netc_switch.h
+++ b/drivers/net/dsa/netc/netc_switch.h
@@ -34,6 +34,7 @@ struct netc_switch;
struct netc_switch_info {
u32 num_ports;
+ void (*phylink_get_caps)(int port, struct phylink_config *config);
};
struct netc_port_caps {
@@ -70,6 +71,9 @@ struct netc_switch {
struct ntmp_user ntmp;
};
+#define NETC_PRIV(ds) ((struct netc_switch *)((ds)->priv))
+#define NETC_PORT(ds, port_id) (NETC_PRIV(ds)->ports[(port_id)])
+
/* Write/Read Switch base registers */
#define netc_base_rd(r, o) netc_read((r)->base + (o))
#define netc_base_wr(r, o, v) netc_write((r)->base + (o), v)
diff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h
index 11cb124ce4bf..881122004644 100644
--- a/drivers/net/dsa/netc/netc_switch_hw.h
+++ b/drivers/net/dsa/netc/netc_switch_hw.h
@@ -71,6 +71,10 @@
#define PCR_TXDIS BIT(0)
#define PCR_RXDIS BIT(1)
+#define NETC_PSR 0x104
+#define PSR_TX_BUSY BIT(0)
+#define PSR_RX_BUSY BIT(1)
+
#define NETC_PTCTMSDUR(a) (0x208 + (a) * 0x20)
#define PTCTMSDUR_MAXSDU GENMASK(15, 0)
#define PTCTMSDUR_SDU_TYPE GENMASK(17, 16)
@@ -127,6 +131,23 @@ enum netc_mfo {
#define NETC_PM_MAXFRM(a) (0x1014 + (a) * 0x400)
#define PM_MAXFRAM GENMASK(15, 0)
+#define NETC_PM_IEVENT(a) (0x1040 + (a) * 0x400)
+#define PM_IEVENT_RX_EMPTY BIT(6)
+
+#define NETC_PM_IF_MODE(a) (0x1300 + (a) * 0x400)
+#define PM_IF_MODE_IFMODE GENMASK(2, 0)
+#define IFMODE_MII 1
+#define IFMODE_RMII 3
+#define IFMODE_RGMII 4
+#define IFMODE_SGMII 5
+#define PM_IF_MODE_REVMII BIT(3)
+#define PM_IF_MODE_M10 BIT(4)
+#define PM_IF_MODE_HD BIT(6)
+#define PM_IF_MODE_SSP GENMASK(14, 13)
+#define SSP_100M 0
+#define SSP_10M 1
+#define SSP_1G 2
+
#define NETC_PEMDIOCR 0x1c00
#define NETC_EMDIO_BASE NETC_PEMDIOCR
--
2.34.1
^ permalink raw reply related
* [PATCH v3 net-next 12/14] net: dsa: netc: add more basic functions support
From: Wei Fang @ 2026-03-26 6:29 UTC (permalink / raw)
To: claudiu.manoil, vladimir.oltean, xiaoning.wang, andrew+netdev,
davem, edumazet, kuba, pabeni, robh, krzk+dt, conor+dt,
f.fainelli, frank.li, chleroy, horms, linux, andrew
Cc: netdev, linux-kernel, devicetree, linuxppc-dev, linux-arm-kernel,
imx
In-Reply-To: <20260326062917.3552334-1-wei.fang@nxp.com>
This patch expands the NETC switch driver with several foundational
features, including FDB and MDB management, STP state handling, MTU
configuration, port setup/teardown, and host flooding support.
At this stage, the driver operates only in standalone port mode. Each
port uses VLAN 0 as its PVID, meaning ingress frames are internally
assigned VID 0 regardless of whether they arrive tagged or untagged.
Note that this does not inject a VLAN 0 header into the frame, the VID
is used purely for subsequent VLAN processing within the switch.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
drivers/net/dsa/netc/netc_main.c | 540 ++++++++++++++++++++++++++
drivers/net/dsa/netc/netc_switch.h | 33 ++
drivers/net/dsa/netc/netc_switch_hw.h | 11 +
3 files changed, 584 insertions(+)
diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c
index f11f5d0f6a6d..3609d83ac363 100644
--- a/drivers/net/dsa/netc/netc_main.c
+++ b/drivers/net/dsa/netc/netc_main.c
@@ -7,11 +7,36 @@
#include <linux/clk.h>
#include <linux/etherdevice.h>
#include <linux/fsl/enetc_mdio.h>
+#include <linux/if_bridge.h>
#include <linux/if_vlan.h>
#include <linux/of_mdio.h>
#include "netc_switch.h"
+static struct netc_fdb_entry *
+netc_lookup_fdb_entry(struct netc_switch *priv,
+ const unsigned char *addr,
+ u16 vid)
+{
+ struct netc_fdb_entry *entry;
+
+ hlist_for_each_entry(entry, &priv->fdb_list, node)
+ if (ether_addr_equal(entry->keye.mac_addr, addr) &&
+ le16_to_cpu(entry->keye.fid) == vid)
+ return entry;
+
+ return NULL;
+}
+
+static void netc_destroy_fdb_list(struct netc_switch *priv)
+{
+ struct netc_fdb_entry *entry;
+ struct hlist_node *tmp;
+
+ hlist_for_each_entry_safe(entry, tmp, &priv->fdb_list, node)
+ netc_del_fdb_entry(entry);
+}
+
static enum dsa_tag_protocol
netc_get_tag_protocol(struct dsa_switch *ds, int port,
enum dsa_tag_protocol mprot)
@@ -386,6 +411,212 @@ static void netc_port_default_config(struct netc_port *np)
netc_port_rmw(np, NETC_POR, PCR_TXDIS, 0);
}
+static u32 netc_available_port_bitmap(struct netc_switch *priv)
+{
+ struct dsa_port *dp;
+ u32 bitmap = 0;
+
+ dsa_switch_for_each_available_port(dp, priv->ds)
+ bitmap |= BIT(dp->index);
+
+ return bitmap;
+}
+
+static int netc_add_standalone_vlan_entry(struct netc_switch *priv)
+{
+ u32 bitmap_stg = VFT_STG_ID(0) | netc_available_port_bitmap(priv);
+ struct vft_cfge_data *cfge;
+ u16 cfg;
+ int err;
+
+ cfge = kzalloc_obj(*cfge);
+ if (!cfge)
+ return -ENOMEM;
+
+ cfge->bitmap_stg = cpu_to_le32(bitmap_stg);
+ cfge->et_eid = cpu_to_le32(NTMP_NULL_ENTRY_ID);
+ cfge->fid = cpu_to_le16(NETC_STANDALONE_PVID);
+
+ /* For standalone ports, MAC learning needs to be disabled, so frames
+ * from other user ports will not be forwarded to the standalone ports,
+ * because there are no FDB entries on the standalone ports. Also, the
+ * frames received by the standalone ports cannot be flooded to other
+ * ports, so MAC forwarding option needs to be set to
+ * MFO_NO_MATCH_DISCARD, so the frames will discarded rather than
+ * flooding to other ports.
+ */
+ cfg = FIELD_PREP(VFT_MLO, MLO_DISABLE) |
+ FIELD_PREP(VFT_MFO, MFO_NO_MATCH_DISCARD);
+ cfge->cfg = cpu_to_le16(cfg);
+
+ err = ntmp_vft_add_entry(&priv->ntmp, NETC_STANDALONE_PVID, cfge);
+ if (err)
+ dev_err(priv->dev,
+ "Failed to add standalone VLAN entry\n");
+
+ kfree(cfge);
+
+ return err;
+}
+
+static int netc_port_add_fdb_entry(struct netc_port *np,
+ const unsigned char *addr, u16 vid)
+{
+ struct netc_switch *priv = np->switch_priv;
+ struct netc_fdb_entry *entry;
+ struct fdbt_keye_data *keye;
+ struct fdbt_cfge_data *cfge;
+ int port = np->dp->index;
+ u32 cfg = 0;
+ int err;
+
+ entry = kzalloc_obj(*entry);
+ if (!entry)
+ return -ENOMEM;
+
+ keye = &entry->keye;
+ cfge = &entry->cfge;
+ ether_addr_copy(keye->mac_addr, addr);
+ keye->fid = cpu_to_le16(vid);
+
+ cfge->port_bitmap = cpu_to_le32(BIT(port));
+ cfge->cfg = cpu_to_le32(cfg);
+ cfge->et_eid = cpu_to_le32(NTMP_NULL_ENTRY_ID);
+
+ err = ntmp_fdbt_add_entry(&priv->ntmp, &entry->entry_id, keye, cfge);
+ if (err) {
+ kfree(entry);
+
+ return err;
+ }
+
+ netc_add_fdb_entry(priv, entry);
+
+ return 0;
+}
+
+static int netc_port_set_fdb_entry(struct netc_port *np,
+ const unsigned char *addr, u16 vid)
+{
+ struct netc_switch *priv = np->switch_priv;
+ struct netc_fdb_entry *entry;
+ int port = np->dp->index;
+ u32 port_bitmap;
+ int err = 0;
+
+ mutex_lock(&priv->fdbt_lock);
+
+ entry = netc_lookup_fdb_entry(priv, addr, vid);
+ if (!entry) {
+ err = netc_port_add_fdb_entry(np, addr, vid);
+ if (err)
+ dev_err(priv->dev,
+ "Failed to add FDB entry on port %d\n",
+ port);
+
+ goto unlock_fdbt;
+ }
+
+ port_bitmap = le32_to_cpu(entry->cfge.port_bitmap);
+ /* If the entry already exists on the port, return 0 directly */
+ if (unlikely(port_bitmap & BIT(port)))
+ goto unlock_fdbt;
+
+ /* If the entry already exists, but not on this port, we need to
+ * update the port bitmap. In general, it should only be valid
+ * for multicast or broadcast address.
+ */
+ port_bitmap ^= BIT(port);
+ entry->cfge.port_bitmap = cpu_to_le32(port_bitmap);
+ err = ntmp_fdbt_update_entry(&priv->ntmp, entry->entry_id,
+ &entry->cfge);
+ if (err) {
+ port_bitmap ^= BIT(port);
+ entry->cfge.port_bitmap = cpu_to_le32(port_bitmap);
+ dev_err(priv->dev, "Failed to set FDB entry on port %d\n",
+ port);
+ }
+
+unlock_fdbt:
+ mutex_unlock(&priv->fdbt_lock);
+
+ return err;
+}
+
+static int netc_port_del_fdb_entry(struct netc_port *np,
+ const unsigned char *addr, u16 vid)
+{
+ struct netc_switch *priv = np->switch_priv;
+ struct ntmp_user *ntmp = &priv->ntmp;
+ struct netc_fdb_entry *entry;
+ int port = np->dp->index;
+ u32 port_bitmap;
+ int err = 0;
+
+ mutex_lock(&priv->fdbt_lock);
+
+ entry = netc_lookup_fdb_entry(priv, addr, vid);
+ if (unlikely(!entry))
+ goto unlock_fdbt;
+
+ port_bitmap = le32_to_cpu(entry->cfge.port_bitmap);
+ if (unlikely(!(port_bitmap & BIT(port))))
+ goto unlock_fdbt;
+
+ if (port_bitmap != BIT(port)) {
+ /* If the entry also exists on other ports, we need to
+ * update the entry in the FDB table.
+ */
+ port_bitmap ^= BIT(port);
+ entry->cfge.port_bitmap = cpu_to_le32(port_bitmap);
+ err = ntmp_fdbt_update_entry(ntmp, entry->entry_id,
+ &entry->cfge);
+ if (err) {
+ port_bitmap ^= BIT(port);
+ entry->cfge.port_bitmap = cpu_to_le32(port_bitmap);
+ goto unlock_fdbt;
+ }
+ } else {
+ /* If the entry only exists on this port, just delete
+ * it from the FDB table.
+ */
+ err = ntmp_fdbt_delete_entry(ntmp, entry->entry_id);
+ if (err)
+ goto unlock_fdbt;
+
+ netc_del_fdb_entry(entry);
+ }
+
+unlock_fdbt:
+ mutex_unlock(&priv->fdbt_lock);
+
+ return err;
+}
+
+static int netc_add_standalone_fdb_bcast_entry(struct netc_switch *priv)
+{
+ const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+ struct dsa_port *dp, *cpu_dp = NULL;
+
+ dsa_switch_for_each_cpu_port(dp, priv->ds) {
+ cpu_dp = dp;
+ break;
+ }
+
+ if (!cpu_dp)
+ return -ENODEV;
+
+ /* If the user port acts as a standalone port, then its PVID is 0,
+ * MLO is set to "disable MAC learning" and MFO is set to "discard
+ * frames if no matching entry found in FDB table". Therefore, we
+ * need to add a broadcast FDB entry on the CPU port so that the
+ * broadcast frames received on the user port can be forwarded to
+ * the CPU port.
+ */
+ return netc_port_set_fdb_entry(NETC_PORT(priv->ds, cpu_dp->index),
+ bcast, NETC_STANDALONE_PVID);
+}
+
static int netc_setup(struct dsa_switch *ds)
{
struct netc_switch *priv = ds->priv;
@@ -404,19 +635,61 @@ static int netc_setup(struct dsa_switch *ds)
if (err)
return err;
+ INIT_HLIST_HEAD(&priv->fdb_list);
+ mutex_init(&priv->fdbt_lock);
+
netc_switch_fixed_config(priv);
/* default setting for ports */
dsa_switch_for_each_available_port(dp, ds)
netc_port_default_config(priv->ports[dp->index]);
+ err = netc_add_standalone_vlan_entry(priv);
+ if (err)
+ goto free_lock_and_ntmp_user;
+
+ err = netc_add_standalone_fdb_bcast_entry(priv);
+ if (err)
+ goto free_lock_and_ntmp_user;
+
return 0;
+
+free_lock_and_ntmp_user:
+ mutex_destroy(&priv->fdbt_lock);
+ netc_free_ntmp_user(priv);
+
+ return err;
+}
+
+static void netc_destroy_all_lists(struct netc_switch *priv)
+{
+ netc_destroy_fdb_list(priv);
+ mutex_destroy(&priv->fdbt_lock);
+}
+
+static void netc_free_host_flood_rules(struct netc_switch *priv)
+{
+ struct dsa_port *dp;
+
+ dsa_switch_for_each_user_port(dp, priv->ds) {
+ struct netc_port *np = priv->ports[dp->index];
+
+ /* No need to clear the hardware IPFT entry. Because PCIe
+ * FLR will be performed when the switch is re-registered,
+ * it will reset hardware state. So only need to free the
+ * memory to avoid memory leak.
+ */
+ kfree(np->host_flood);
+ np->host_flood = NULL;
+ }
}
static void netc_teardown(struct dsa_switch *ds)
{
struct netc_switch *priv = ds->priv;
+ netc_destroy_all_lists(priv);
+ netc_free_host_flood_rules(priv);
netc_free_ntmp_user(priv);
}
@@ -569,6 +842,261 @@ static void netc_switch_get_ip_revision(struct netc_switch *priv)
priv->revision = val & IPBRR0_IP_REV;
}
+static int netc_port_enable(struct dsa_switch *ds, int port,
+ struct phy_device *phy)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+ int err;
+
+ if (np->enable)
+ return 0;
+
+ err = clk_prepare_enable(np->ref_clk);
+ if (err) {
+ dev_err(ds->dev,
+ "Failed to enable enet_ref_clk of port %d\n", port);
+ return err;
+ }
+
+ np->enable = true;
+
+ return 0;
+}
+
+static void netc_port_disable(struct dsa_switch *ds, int port)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+
+ /* When .port_disable() is called, .port_enable() may not have been
+ * called. In this case, both the prepare_count and enable_count of
+ * clock are 0. Calling clk_disable_unprepare() at this time will
+ * cause warnings.
+ */
+ if (!np->enable)
+ return;
+
+ clk_disable_unprepare(np->ref_clk);
+ np->enable = false;
+}
+
+static void netc_port_stp_state_set(struct dsa_switch *ds,
+ int port, u8 state)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+ u32 val;
+
+ switch (state) {
+ case BR_STATE_DISABLED:
+ case BR_STATE_LISTENING:
+ case BR_STATE_BLOCKING:
+ val = NETC_STG_STATE_DISABLED;
+ break;
+ case BR_STATE_LEARNING:
+ val = NETC_STG_STATE_LEARNING;
+ break;
+ case BR_STATE_FORWARDING:
+ val = NETC_STG_STATE_FORWARDING;
+ break;
+ default:
+ return;
+ }
+
+ netc_port_wr(np, NETC_BPSTGSR, val);
+}
+
+static int netc_port_change_mtu(struct dsa_switch *ds,
+ int port, int mtu)
+{
+ u32 max_frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
+ struct netc_port *np = NETC_PORT(ds, port);
+
+ if (dsa_is_cpu_port(ds, port))
+ max_frame_size += NETC_TAG_MAX_LEN;
+
+ netc_port_set_max_frame_size(np, max_frame_size);
+
+ return 0;
+}
+
+static int netc_port_max_mtu(struct dsa_switch *ds, int port)
+{
+ return NETC_MAX_FRAME_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN;
+}
+
+static int netc_port_fdb_add(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+
+ /* Currently, we only support standalone port mode, so all VLANs
+ * should be converted to NETC_STANDALONE_PVID.
+ */
+ return netc_port_set_fdb_entry(np, addr, NETC_STANDALONE_PVID);
+}
+
+static int netc_port_fdb_del(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+
+ return netc_port_del_fdb_entry(np, addr, NETC_STANDALONE_PVID);
+}
+
+static int netc_port_fdb_dump(struct dsa_switch *ds, int port,
+ dsa_fdb_dump_cb_t *cb, void *data)
+{
+ struct netc_switch *priv = ds->priv;
+ u32 resume_eid = NTMP_NULL_ENTRY_ID;
+ struct fdbt_entry_data *entry;
+ struct fdbt_keye_data *keye;
+ struct fdbt_cfge_data *cfge;
+ bool is_static;
+ u32 cfg;
+ int err;
+ u16 vid;
+
+ entry = kmalloc_obj(*entry);
+ if (!entry)
+ return -ENOMEM;
+
+ keye = &entry->keye;
+ cfge = &entry->cfge;
+ mutex_lock(&priv->fdbt_lock);
+
+ do {
+ memset(entry, 0, sizeof(*entry));
+ err = ntmp_fdbt_search_port_entry(&priv->ntmp, port,
+ &resume_eid, entry);
+ if (err || entry->entry_id == NTMP_NULL_ENTRY_ID)
+ break;
+
+ cfg = le32_to_cpu(cfge->cfg);
+ is_static = (cfg & FDBT_DYNAMIC) ? false : true;
+ vid = le16_to_cpu(keye->fid);
+
+ err = cb(keye->mac_addr, vid, is_static, data);
+ if (err)
+ break;
+ } while (resume_eid != NTMP_NULL_ENTRY_ID);
+
+ mutex_unlock(&priv->fdbt_lock);
+ kfree(entry);
+
+ return err;
+}
+
+static int netc_port_mdb_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ return netc_port_fdb_add(ds, port, mdb->addr, mdb->vid, db);
+}
+
+static int netc_port_mdb_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ return netc_port_fdb_del(ds, port, mdb->addr, mdb->vid, db);
+}
+
+static int netc_port_add_host_flood_rule(struct netc_port *np,
+ bool uc, bool mc)
+{
+ const u8 dmac_mask[ETH_ALEN] = {0x1, 0, 0, 0, 0, 0};
+ struct netc_switch *priv = np->switch_priv;
+ struct ipft_entry_data *host_flood;
+ struct ipft_keye_data *keye;
+ struct ipft_cfge_data *cfge;
+ u16 src_port;
+ u32 cfg;
+ int err;
+
+ if (!uc && !mc)
+ return 0;
+
+ host_flood = kzalloc_obj(*host_flood);
+ if (!host_flood)
+ return -ENOMEM;
+
+ keye = &host_flood->keye;
+ cfge = &host_flood->cfge;
+
+ src_port = FIELD_PREP(IPFT_SRC_PORT, np->dp->index);
+ src_port |= IPFT_SRC_PORT_MASK;
+ keye->src_port = cpu_to_le16(src_port);
+
+ /* If either only unicast or only multicast need to be flooded
+ * to the host, we always set the mask that tests the first MAC
+ * DA octet. The value should be 0 for the first bit (if unicast
+ * has to be flooded) or 1 (if multicast). If both unicast and
+ * multicast have to be flooded, we leave the key mask empty, so
+ * it matches everything.
+ */
+ if (uc && !mc)
+ ether_addr_copy(keye->dmac_mask, dmac_mask);
+
+ if (!uc && mc) {
+ ether_addr_copy(keye->dmac, dmac_mask);
+ ether_addr_copy(keye->dmac_mask, dmac_mask);
+ }
+
+ cfg = FIELD_PREP(IPFT_FLTFA, IPFT_FLTFA_REDIRECT);
+ cfg |= FIELD_PREP(IPFT_HR, NETC_HR_HOST_FLOOD);
+ cfge->cfg = cpu_to_le32(cfg);
+
+ err = ntmp_ipft_add_entry(&priv->ntmp, host_flood);
+ if (err) {
+ kfree(host_flood);
+ return err;
+ }
+
+ np->uc = uc;
+ np->mc = mc;
+ np->host_flood = host_flood;
+ /* Enable ingress port filter table lookup */
+ netc_port_wr(np, NETC_PIPFCR, PIPFCR_EN);
+
+ return 0;
+}
+
+static void netc_port_remove_host_flood(struct netc_port *np)
+{
+ struct netc_switch *priv = np->switch_priv;
+
+ if (!np->host_flood)
+ return;
+
+ ntmp_ipft_delete_entry(&priv->ntmp, np->host_flood->entry_id);
+ kfree(np->host_flood);
+ np->host_flood = NULL;
+ np->uc = false;
+ np->mc = false;
+ /* Disable ingress port filter table lookup */
+ netc_port_wr(np, NETC_PIPFCR, 0);
+}
+
+static void netc_port_set_host_flood(struct dsa_switch *ds, int port,
+ bool uc, bool mc)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+
+ if (np->uc == uc && np->mc == mc)
+ return;
+
+ /* IPFT does not support in-place updates to the KEYE element,
+ * so we need to delete the old IPFT entry and then add a new
+ * one.
+ */
+ if (np->host_flood)
+ netc_port_remove_host_flood(np);
+
+ if (netc_port_add_host_flood_rule(np, uc, mc))
+ dev_err(ds->dev, "Failed to add host flood rule on port %d\n",
+ port);
+}
+
static void netc_phylink_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
@@ -751,6 +1279,17 @@ static const struct dsa_switch_ops netc_switch_ops = {
.setup = netc_setup,
.teardown = netc_teardown,
.phylink_get_caps = netc_phylink_get_caps,
+ .port_enable = netc_port_enable,
+ .port_disable = netc_port_disable,
+ .port_stp_state_set = netc_port_stp_state_set,
+ .port_change_mtu = netc_port_change_mtu,
+ .port_max_mtu = netc_port_max_mtu,
+ .port_fdb_add = netc_port_fdb_add,
+ .port_fdb_del = netc_port_fdb_del,
+ .port_fdb_dump = netc_port_fdb_dump,
+ .port_mdb_add = netc_port_mdb_add,
+ .port_mdb_del = netc_port_mdb_del,
+ .port_set_host_flood = netc_port_set_host_flood,
};
static int netc_switch_probe(struct pci_dev *pdev,
@@ -792,6 +1331,7 @@ static int netc_switch_probe(struct pci_dev *pdev,
ds->num_tx_queues = NETC_TC_NUM;
ds->ops = &netc_switch_ops;
ds->phylink_mac_ops = &netc_phylink_mac_ops;
+ ds->fdb_isolation = true;
ds->priv = priv;
priv->ds = ds;
diff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h
index eb65c36ecead..4b229a71578e 100644
--- a/drivers/net/dsa/netc/netc_switch.h
+++ b/drivers/net/dsa/netc/netc_switch.h
@@ -30,6 +30,8 @@
#define NETC_MAX_FRAME_LEN 9600
+#define NETC_STANDALONE_PVID 0
+
struct netc_switch;
struct netc_switch_info {
@@ -43,6 +45,11 @@ struct netc_port_caps {
u32 pseudo_link:1;
};
+enum netc_host_reason {
+ /* Software defined host reasons */
+ NETC_HR_HOST_FLOOD = 8,
+};
+
struct netc_port {
void __iomem *iobase;
struct netc_switch *switch_priv;
@@ -50,6 +57,11 @@ struct netc_port {
struct dsa_port *dp;
struct clk *ref_clk; /* RGMII/RMII reference clock */
struct mii_bus *emdio;
+
+ u16 enable:1;
+ u16 uc:1;
+ u16 mc:1;
+ struct ipft_entry_data *host_flood;
};
struct netc_switch_regs {
@@ -58,6 +70,13 @@ struct netc_switch_regs {
void __iomem *global;
};
+struct netc_fdb_entry {
+ u32 entry_id;
+ struct fdbt_cfge_data cfge;
+ struct fdbt_keye_data keye;
+ struct hlist_node node;
+};
+
struct netc_switch {
struct pci_dev *pdev;
struct device *dev;
@@ -69,6 +88,8 @@ struct netc_switch {
struct netc_port **ports;
struct ntmp_user ntmp;
+ struct hlist_head fdb_list;
+ struct mutex fdbt_lock; /* FDB table lock */
};
#define NETC_PRIV(ds) ((struct netc_switch *)((ds)->priv))
@@ -91,6 +112,18 @@ static inline bool is_netc_pseudo_port(struct netc_port *np)
return np->caps.pseudo_link;
}
+static inline void netc_add_fdb_entry(struct netc_switch *priv,
+ struct netc_fdb_entry *entry)
+{
+ hlist_add_head(&entry->node, &priv->fdb_list);
+}
+
+static inline void netc_del_fdb_entry(struct netc_fdb_entry *entry)
+{
+ hlist_del(&entry->node);
+ kfree(entry);
+}
+
int netc_switch_platform_probe(struct netc_switch *priv);
#endif
diff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h
index 881122004644..c6a0c0a8ff8a 100644
--- a/drivers/net/dsa/netc/netc_switch_hw.h
+++ b/drivers/net/dsa/netc/netc_switch_hw.h
@@ -67,6 +67,9 @@
#define PQOSMR_VQMP GENMASK(19, 16)
#define PQOSMR_QVMP GENMASK(23, 20)
+#define NETC_PIPFCR 0x0084
+#define PIPFCR_EN BIT(0)
+
#define NETC_POR 0x100
#define PCR_TXDIS BIT(0)
#define PCR_RXDIS BIT(1)
@@ -122,6 +125,14 @@ enum netc_mfo {
#define BPDVR_RXVAM BIT(24)
#define BPDVR_TXTAGA GENMASK(26, 25)
+#define NETC_BPSTGSR 0x520
+
+enum netc_stg_stage {
+ NETC_STG_STATE_DISABLED = 0,
+ NETC_STG_STATE_LEARNING,
+ NETC_STG_STATE_FORWARDING,
+};
+
/* Definition of Switch ethernet MAC port registers */
#define NETC_PMAC_OFFSET 0x400
#define NETC_PM_CMD_CFG(a) (0x1008 + (a) * 0x400)
--
2.34.1
^ permalink raw reply related
* [PATCH v3 net-next 13/14] net: dsa: netc: initialize buffer bool table and implement flow-control
From: Wei Fang @ 2026-03-26 6:29 UTC (permalink / raw)
To: claudiu.manoil, vladimir.oltean, xiaoning.wang, andrew+netdev,
davem, edumazet, kuba, pabeni, robh, krzk+dt, conor+dt,
f.fainelli, frank.li, chleroy, horms, linux, andrew
Cc: netdev, linux-kernel, devicetree, linuxppc-dev, linux-arm-kernel,
imx
In-Reply-To: <20260326062917.3552334-1-wei.fang@nxp.com>
The buffer pool is a quantity of memory available for buffering a group
of flows (e.g. frames having the same priority, frames received from the
same port), while waiting to be transmitted on a port. The buffer pool
tracks internal memory consumption with upper bound limits and optionally
a non-shared portion when associated with a shared buffer pool. Currently
the shared buffer pool is not supported, it will be added in the future.
For i.MX94, the switch has 4 ports and 8 buffer pools, so each port is
allocated two buffer pools. For frames with priorities of 0 to 3, they
will be mapped to the first buffer pool; For frames with priorities of
4 to 7, they will be mapped to the second buffer pool. Each buffer pool
has a flow control on threshold and a flow control off threshold. By
setting these threshold, add the flow control support to each port.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
drivers/net/dsa/netc/netc_main.c | 163 ++++++++++++++++++++++++++
drivers/net/dsa/netc/netc_switch.h | 9 ++
drivers/net/dsa/netc/netc_switch_hw.h | 13 ++
3 files changed, 185 insertions(+)
diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c
index 3609d83ac363..62611263a93f 100644
--- a/drivers/net/dsa/netc/netc_main.c
+++ b/drivers/net/dsa/netc/netc_main.c
@@ -379,6 +379,8 @@ static void netc_port_set_mlo(struct netc_port *np, enum netc_mlo mlo)
static void netc_port_fixed_config(struct netc_port *np)
{
+ u32 pqnt = 0xffff, qth = 0xff00;
+
/* Default IPV and DR setting */
netc_port_rmw(np, NETC_PQOSMR, PQOSMR_VS | PQOSMR_VE,
PQOSMR_VS | PQOSMR_VE);
@@ -386,6 +388,15 @@ static void netc_port_fixed_config(struct netc_port *np)
/* Enable L2 and L3 DOS */
netc_port_rmw(np, NETC_PCR, PCR_L2DOSE | PCR_L3DOSE,
PCR_L2DOSE | PCR_L3DOSE);
+
+ /* Set the quanta value of TX PAUSE frame */
+ netc_mac_port_wr(np, NETC_PM_PAUSE_QUANTA(0), pqnt);
+
+ /* When a quanta timer counts down and reaches this value,
+ * the MAC sends a refresh PAUSE frame with the programmed
+ * full quanta value if a pause condition still exists.
+ */
+ netc_mac_port_wr(np, NETC_PM_PAUSE_TRHESH(0), qth);
}
static void netc_port_default_config(struct netc_port *np)
@@ -617,6 +628,117 @@ static int netc_add_standalone_fdb_bcast_entry(struct netc_switch *priv)
bcast, NETC_STANDALONE_PVID);
}
+static u32 netc_get_buffer_pool_num(struct netc_switch *priv)
+{
+ return netc_base_rd(&priv->regs, NETC_BPCAPR) & BPCAPR_NUM_BP;
+}
+
+static void netc_port_set_pbpmcr(struct netc_port *np, u64 mapping)
+{
+ u32 pbpmcr0 = lower_32_bits(mapping);
+ u32 pbpmcr1 = upper_32_bits(mapping);
+
+ netc_port_wr(np, NETC_PBPMCR0, pbpmcr0);
+ netc_port_wr(np, NETC_PBPMCR1, pbpmcr1);
+}
+
+static void netc_ipv_to_buffer_pool_mapping(struct netc_switch *priv)
+{
+ int bp_per_port = priv->num_bp / priv->info->num_ports;
+ int q, r, num, i, ipv;
+ u32 bp_id;
+
+ if (!bp_per_port) {
+ q = priv->info->num_ports / priv->num_bp;
+ r = priv->info->num_ports % priv->num_bp;
+ num = (q + 1) * r;
+
+ /* Multiple ports share a buffer pool, the mapping relationship
+ * between ports and buffer pools is as follows:
+ *
+ * - For the first 'r' buffer pools, each buffer pool is shared
+ * by 'q + 1' ports.
+ * - After that, each buffer pool is share by 'q' ports.
+ * - All IPVs of a port are mapped to the same buffer pool.
+ */
+ for (i = 0; i < priv->info->num_ports; i++) {
+ u64 mapping = 0;
+
+ if (i < num)
+ bp_id = i / (q + 1);
+ else
+ bp_id = r + (i - num) / q;
+
+ for (ipv = 0; ipv < NETC_IPV_NUM; ipv++)
+ mapping |= (u64)bp_id << (ipv * 8);
+
+ netc_port_set_pbpmcr(priv->ports[i], mapping);
+ }
+
+ return;
+ }
+
+ q = NETC_IPV_NUM / bp_per_port;
+ r = NETC_IPV_NUM % bp_per_port;
+ num = q + r;
+
+ /* IPV-to–buffer-pool mapping per port:
+ * Each port is allocated 'bp_per_port' buffer pools and supports 8
+ * IPVs, where a higher IPV indicates a higher frame priority. Each
+ * IPV can be mapped to only one buffer pool.
+ *
+ * The mapping rule is as follows:
+ * - The first 'num' IPVs share the port's first buffer pool (index
+ * 'base_id').
+ * - After that, every 'q' IPVs share one buffer pool, with pool
+ * indices increasing sequentially.
+ */
+ for (i = 0; i < priv->info->num_ports; i++) {
+ u32 base_id = i * bp_per_port;
+ u64 mapping = 0;
+
+ bp_id = base_id;
+
+ for (ipv = 0; ipv < NETC_IPV_NUM; ipv++) {
+ /* Update the buffer pool index */
+ if (ipv >= num)
+ bp_id = base_id + ((ipv - num) / q) + 1;
+
+ mapping |= (u64)bp_id << (ipv * 8);
+ }
+
+ netc_port_set_pbpmcr(priv->ports[i], mapping);
+ }
+}
+
+static int netc_switch_bpt_default_config(struct netc_switch *priv)
+{
+ /* priv->num_bp is read from register, its value is hardcoded as
+ * a non-zero value.
+ */
+ priv->num_bp = netc_get_buffer_pool_num(priv);
+ priv->bpt_list = devm_kcalloc(priv->dev, priv->num_bp,
+ sizeof(struct bpt_cfge_data),
+ GFP_KERNEL);
+ if (!priv->bpt_list)
+ return -ENOMEM;
+
+ /* Initialize the maximum threshold of each buffer pool entry */
+ for (int i = 0; i < priv->num_bp; i++) {
+ struct bpt_cfge_data *cfge = &priv->bpt_list[i];
+ int err;
+
+ cfge->max_thresh = cpu_to_le16(NETC_BP_THRESH);
+ err = ntmp_bpt_update_entry(&priv->ntmp, i, cfge);
+ if (err)
+ return err;
+ }
+
+ netc_ipv_to_buffer_pool_mapping(priv);
+
+ return 0;
+}
+
static int netc_setup(struct dsa_switch *ds)
{
struct netc_switch *priv = ds->priv;
@@ -644,6 +766,10 @@ static int netc_setup(struct dsa_switch *ds)
dsa_switch_for_each_available_port(dp, ds)
netc_port_default_config(priv->ports[dp->index]);
+ err = netc_switch_bpt_default_config(priv);
+ if (err)
+ goto free_lock_and_ntmp_user;
+
err = netc_add_standalone_vlan_entry(priv);
if (err)
goto free_lock_and_ntmp_user;
@@ -1195,6 +1321,41 @@ static void netc_port_set_rmii_mii_mac(struct netc_port *np,
netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);
}
+static void netc_port_set_tx_pause(struct netc_port *np, bool tx_pause)
+{
+ struct netc_switch *priv = np->switch_priv;
+ int port = np->dp->index;
+ int i, j, num_bp;
+
+ num_bp = priv->num_bp / priv->info->num_ports;
+ for (i = 0, j = port * num_bp; i < num_bp; i++, j++) {
+ struct bpt_cfge_data *cfge = &priv->bpt_list[j];
+ struct bpt_cfge_data old_cfge = *cfge;
+
+ if (tx_pause) {
+ cfge->fc_on_thresh = cpu_to_le16(NETC_FC_THRESH_ON);
+ cfge->fc_off_thresh = cpu_to_le16(NETC_FC_THRESH_OFF);
+ cfge->fccfg_sbpen = FIELD_PREP(BPT_FC_CFG,
+ BPT_FC_CFG_EN_BPFC);
+ cfge->fc_ports = cpu_to_le32(BIT(port));
+ } else {
+ cfge->fc_on_thresh = cpu_to_le16(0);
+ cfge->fc_off_thresh = cpu_to_le16(0);
+ cfge->fccfg_sbpen = 0;
+ cfge->fc_ports = cpu_to_le32(0);
+ }
+
+ if (ntmp_bpt_update_entry(&priv->ntmp, j, cfge))
+ *cfge = old_cfge;
+ }
+}
+
+static void netc_port_set_rx_pause(struct netc_port *np, bool rx_pause)
+{
+ netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_PAUSE_IGN,
+ rx_pause ? 0 : PM_CMD_CFG_PAUSE_IGN);
+}
+
static void netc_port_mac_rx_enable(struct netc_port *np)
{
netc_port_rmw(np, NETC_POR, PCR_RXDIS, 0);
@@ -1256,6 +1417,8 @@ static void netc_mac_link_up(struct phylink_config *config,
interface == PHY_INTERFACE_MODE_MII)
netc_port_set_rmii_mii_mac(np, speed, duplex);
+ netc_port_set_tx_pause(np, tx_pause);
+ netc_port_set_rx_pause(np, rx_pause);
netc_port_mac_rx_enable(np);
}
diff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h
index 4b229a71578e..7ebffb136b2f 100644
--- a/drivers/net/dsa/netc/netc_switch.h
+++ b/drivers/net/dsa/netc/netc_switch.h
@@ -32,6 +32,12 @@
#define NETC_STANDALONE_PVID 0
+#define NETC_IPV_NUM 8
+/* MANT = bits 11:4, EXP = bits 3:0, threshold = MANT * 2 ^ EXP */
+#define NETC_BP_THRESH 0x334
+#define NETC_FC_THRESH_ON 0x533
+#define NETC_FC_THRESH_OFF 0x3c3
+
struct netc_switch;
struct netc_switch_info {
@@ -90,6 +96,9 @@ struct netc_switch {
struct ntmp_user ntmp;
struct hlist_head fdb_list;
struct mutex fdbt_lock; /* FDB table lock */
+
+ u32 num_bp;
+ struct bpt_cfge_data *bpt_list;
};
#define NETC_PRIV(ds) ((struct netc_switch *)((ds)->priv))
diff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h
index c6a0c0a8ff8a..1e1c0d279a21 100644
--- a/drivers/net/dsa/netc/netc_switch_hw.h
+++ b/drivers/net/dsa/netc/netc_switch_hw.h
@@ -12,6 +12,12 @@
#define NETC_SWITCH_DEVICE_ID 0xeef2
/* Definition of Switch base registers */
+#define NETC_BPCAPR 0x0008
+#define BPCAPR_NUM_BP GENMASK(7, 0)
+
+#define NETC_PBPMCR0 0x0400
+#define NETC_PBPMCR1 0x0404
+
#define NETC_CBDRMR(a) (0x0800 + (a) * 0x30)
#define NETC_CBDRBAR0(a) (0x0810 + (a) * 0x30)
#define NETC_CBDRBAR1(a) (0x0814 + (a) * 0x30)
@@ -138,6 +144,7 @@ enum netc_stg_stage {
#define NETC_PM_CMD_CFG(a) (0x1008 + (a) * 0x400)
#define PM_CMD_CFG_TX_EN BIT(0)
#define PM_CMD_CFG_RX_EN BIT(1)
+#define PM_CMD_CFG_PAUSE_IGN BIT(8)
#define NETC_PM_MAXFRM(a) (0x1014 + (a) * 0x400)
#define PM_MAXFRAM GENMASK(15, 0)
@@ -145,6 +152,12 @@ enum netc_stg_stage {
#define NETC_PM_IEVENT(a) (0x1040 + (a) * 0x400)
#define PM_IEVENT_RX_EMPTY BIT(6)
+#define NETC_PM_PAUSE_QUANTA(a) (0x1054 + (a) * 0x400)
+#define PAUSE_QUANTA_PQNT GENMASK(15, 0)
+
+#define NETC_PM_PAUSE_TRHESH(a) (0x1064 + (a) * 0x400)
+#define PAUSE_TRHESH_QTH GENMASK(15, 0)
+
#define NETC_PM_IF_MODE(a) (0x1300 + (a) * 0x400)
#define PM_IF_MODE_IFMODE GENMASK(2, 0)
#define IFMODE_MII 1
--
2.34.1
^ permalink raw reply related
* [PATCH v3 net-next 14/14] net: dsa: netc: add support for the standardized counters
From: Wei Fang @ 2026-03-26 6:29 UTC (permalink / raw)
To: claudiu.manoil, vladimir.oltean, xiaoning.wang, andrew+netdev,
davem, edumazet, kuba, pabeni, robh, krzk+dt, conor+dt,
f.fainelli, frank.li, chleroy, horms, linux, andrew
Cc: netdev, linux-kernel, devicetree, linuxppc-dev, linux-arm-kernel,
imx
In-Reply-To: <20260326062917.3552334-1-wei.fang@nxp.com>
Each user port of the NETC switch supports 802.3 basic and mandatory
managed objects statistic counters and IETF Management Information
Database (MIB) package (RFC2665) and Remote Network Monitoring (RMON)
counters. And all of these counters are 64-bit registers. In addition,
some user ports support preemption, so these ports have two MACs, MAC
0 is the express MAC (eMAC), MAC 1 is the preemptible MAC (pMAC). So
for ports that support preemption, the statistics are the sum of the
pMAC and eMAC statistics.
Note that the current switch driver does not support preemption, all
frames are sent and received via the eMAC by default. The statistics
read from the pMAC should be zero.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
drivers/net/dsa/netc/Makefile | 2 +-
drivers/net/dsa/netc/netc_ethtool.c | 192 ++++++++++++++++++++++++++
drivers/net/dsa/netc/netc_main.c | 4 +
drivers/net/dsa/netc/netc_switch.h | 17 +++
drivers/net/dsa/netc/netc_switch_hw.h | 153 ++++++++++++++++++++
include/linux/fsl/netc_global.h | 6 +
6 files changed, 373 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/dsa/netc/netc_ethtool.c
diff --git a/drivers/net/dsa/netc/Makefile b/drivers/net/dsa/netc/Makefile
index 4a5767562574..f40b13c702e0 100644
--- a/drivers/net/dsa/netc/Makefile
+++ b/drivers/net/dsa/netc/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_NET_DSA_NETC_SWITCH) += nxp-netc-switch.o
-nxp-netc-switch-objs := netc_main.o netc_platform.o
+nxp-netc-switch-objs := netc_main.o netc_platform.o netc_ethtool.o
diff --git a/drivers/net/dsa/netc/netc_ethtool.c b/drivers/net/dsa/netc/netc_ethtool.c
new file mode 100644
index 000000000000..8e5861543d30
--- /dev/null
+++ b/drivers/net/dsa/netc/netc_ethtool.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * NXP NETC switch driver
+ * Copyright 2025-2026 NXP
+ */
+
+#include <linux/ethtool_netlink.h>
+
+#include "netc_switch.h"
+
+static void netc_port_pause_stats(struct netc_port *np,
+ enum netc_port_mac mac,
+ struct ethtool_pause_stats *stats)
+{
+ if (mac == NETC_PORT_PMAC && !np->caps.pmac)
+ return;
+
+ stats->tx_pause_frames = netc_port_rd64(np, NETC_PM_TXPF(mac));
+ stats->rx_pause_frames = netc_port_rd64(np, NETC_PM_RXPF(mac));
+}
+
+void netc_port_get_pause_stats(struct dsa_switch *ds, int port,
+ struct ethtool_pause_stats *pause_stats)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+ struct net_device *ndev;
+
+ switch (pause_stats->src) {
+ case ETHTOOL_MAC_STATS_SRC_EMAC:
+ netc_port_pause_stats(np, NETC_PORT_EMAC, pause_stats);
+ break;
+ case ETHTOOL_MAC_STATS_SRC_PMAC:
+ netc_port_pause_stats(np, NETC_PORT_PMAC, pause_stats);
+ break;
+ case ETHTOOL_MAC_STATS_SRC_AGGREGATE:
+ ndev = dsa_to_port(ds, port)->user;
+ ethtool_aggregate_pause_stats(ndev, pause_stats);
+ break;
+ }
+}
+
+static const struct ethtool_rmon_hist_range netc_rmon_ranges[] = {
+ { 64, 64 },
+ { 65, 127 },
+ { 128, 255 },
+ { 256, 511 },
+ { 512, 1023 },
+ { 1024, 1522 },
+ { 1523, NETC_MAX_FRAME_LEN },
+ { }
+};
+
+static void netc_port_rmon_stats(struct netc_port *np,
+ enum netc_port_mac mac,
+ struct ethtool_rmon_stats *stats)
+{
+ if (mac == NETC_PORT_PMAC && !np->caps.pmac)
+ return;
+
+ stats->undersize_pkts = netc_port_rd64(np, NETC_PM_RUND(mac));
+ stats->oversize_pkts = netc_port_rd64(np, NETC_PM_ROVR(mac));
+ stats->fragments = netc_port_rd64(np, NETC_PM_RFRG(mac));
+ stats->jabbers = netc_port_rd64(np, NETC_PM_RJBR(mac));
+
+ stats->hist[0] = netc_port_rd64(np, NETC_PM_R64(mac));
+ stats->hist[1] = netc_port_rd64(np, NETC_PM_R127(mac));
+ stats->hist[2] = netc_port_rd64(np, NETC_PM_R255(mac));
+ stats->hist[3] = netc_port_rd64(np, NETC_PM_R511(mac));
+ stats->hist[4] = netc_port_rd64(np, NETC_PM_R1023(mac));
+ stats->hist[5] = netc_port_rd64(np, NETC_PM_R1522(mac));
+ stats->hist[6] = netc_port_rd64(np, NETC_PM_R1523X(mac));
+
+ stats->hist_tx[0] = netc_port_rd64(np, NETC_PM_T64(mac));
+ stats->hist_tx[1] = netc_port_rd64(np, NETC_PM_T127(mac));
+ stats->hist_tx[2] = netc_port_rd64(np, NETC_PM_T255(mac));
+ stats->hist_tx[3] = netc_port_rd64(np, NETC_PM_T511(mac));
+ stats->hist_tx[4] = netc_port_rd64(np, NETC_PM_T1023(mac));
+ stats->hist_tx[5] = netc_port_rd64(np, NETC_PM_T1522(mac));
+ stats->hist_tx[6] = netc_port_rd64(np, NETC_PM_T1523X(mac));
+}
+
+void netc_port_get_rmon_stats(struct dsa_switch *ds, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+ struct net_device *ndev;
+
+ *ranges = netc_rmon_ranges;
+
+ switch (rmon_stats->src) {
+ case ETHTOOL_MAC_STATS_SRC_EMAC:
+ netc_port_rmon_stats(np, NETC_PORT_EMAC, rmon_stats);
+ break;
+ case ETHTOOL_MAC_STATS_SRC_PMAC:
+ netc_port_rmon_stats(np, NETC_PORT_PMAC, rmon_stats);
+ break;
+ case ETHTOOL_MAC_STATS_SRC_AGGREGATE:
+ ndev = dsa_to_port(ds, port)->user;
+ ethtool_aggregate_rmon_stats(ndev, rmon_stats);
+ break;
+ }
+}
+
+static void netc_port_ctrl_stats(struct netc_port *np,
+ enum netc_port_mac mac,
+ struct ethtool_eth_ctrl_stats *stats)
+{
+ if (mac == NETC_PORT_PMAC && !np->caps.pmac)
+ return;
+
+ stats->MACControlFramesTransmitted =
+ netc_port_rd64(np, NETC_PM_TCNP(mac));
+ stats->MACControlFramesReceived =
+ netc_port_rd64(np, NETC_PM_RCNP(mac));
+}
+
+void netc_port_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+ struct net_device *ndev;
+
+ switch (ctrl_stats->src) {
+ case ETHTOOL_MAC_STATS_SRC_EMAC:
+ netc_port_ctrl_stats(np, NETC_PORT_EMAC, ctrl_stats);
+ break;
+ case ETHTOOL_MAC_STATS_SRC_PMAC:
+ netc_port_ctrl_stats(np, NETC_PORT_PMAC, ctrl_stats);
+ break;
+ case ETHTOOL_MAC_STATS_SRC_AGGREGATE:
+ ndev = dsa_to_port(ds, port)->user;
+ ethtool_aggregate_ctrl_stats(ndev, ctrl_stats);
+ break;
+ }
+}
+
+static void netc_port_mac_stats(struct netc_port *np,
+ enum netc_port_mac mac,
+ struct ethtool_eth_mac_stats *stats)
+{
+ if (mac == NETC_PORT_PMAC && !np->caps.pmac)
+ return;
+
+ stats->FramesTransmittedOK = netc_port_rd64(np, NETC_PM_TFRM(mac));
+ stats->SingleCollisionFrames = netc_port_rd64(np, NETC_PM_TSCOL(mac));
+ stats->MultipleCollisionFrames =
+ netc_port_rd64(np, NETC_PM_TMCOL(mac));
+ stats->FramesReceivedOK = netc_port_rd64(np, NETC_PM_RFRM(mac));
+ stats->FrameCheckSequenceErrors =
+ netc_port_rd64(np, NETC_PM_RFCS(mac));
+ stats->AlignmentErrors = netc_port_rd64(np, NETC_PM_RALN(mac));
+ stats->OctetsTransmittedOK = netc_port_rd64(np, NETC_PM_TEOCT(mac));
+ stats->FramesWithDeferredXmissions =
+ netc_port_rd64(np, NETC_PM_TDFR(mac));
+ stats->LateCollisions = netc_port_rd64(np, NETC_PM_TLCOL(mac));
+ stats->FramesAbortedDueToXSColls =
+ netc_port_rd64(np, NETC_PM_TECOL(mac));
+ stats->FramesLostDueToIntMACXmitError =
+ netc_port_rd64(np, NETC_PM_TERR(mac));
+ stats->OctetsReceivedOK = netc_port_rd64(np, NETC_PM_REOCT(mac));
+ stats->FramesLostDueToIntMACRcvError =
+ netc_port_rd64(np, NETC_PM_RDRNTP(mac));
+ stats->MulticastFramesXmittedOK =
+ netc_port_rd64(np, NETC_PM_TMCA(mac));
+ stats->BroadcastFramesXmittedOK =
+ netc_port_rd64(np, NETC_PM_TBCA(mac));
+ stats->MulticastFramesReceivedOK =
+ netc_port_rd64(np, NETC_PM_RMCA(mac));
+ stats->BroadcastFramesReceivedOK =
+ netc_port_rd64(np, NETC_PM_RBCA(mac));
+}
+
+void netc_port_get_eth_mac_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_mac_stats *mac_stats)
+{
+ struct netc_port *np = NETC_PORT(ds, port);
+ struct net_device *ndev;
+
+ switch (mac_stats->src) {
+ case ETHTOOL_MAC_STATS_SRC_EMAC:
+ netc_port_mac_stats(np, NETC_PORT_EMAC, mac_stats);
+ break;
+ case ETHTOOL_MAC_STATS_SRC_PMAC:
+ netc_port_mac_stats(np, NETC_PORT_PMAC, mac_stats);
+ break;
+ case ETHTOOL_MAC_STATS_SRC_AGGREGATE:
+ ndev = dsa_to_port(ds, port)->user;
+ ethtool_aggregate_mac_stats(ndev, mac_stats);
+ break;
+ }
+}
diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c
index 62611263a93f..9f145082921e 100644
--- a/drivers/net/dsa/netc/netc_main.c
+++ b/drivers/net/dsa/netc/netc_main.c
@@ -1453,6 +1453,10 @@ static const struct dsa_switch_ops netc_switch_ops = {
.port_mdb_add = netc_port_mdb_add,
.port_mdb_del = netc_port_mdb_del,
.port_set_host_flood = netc_port_set_host_flood,
+ .get_pause_stats = netc_port_get_pause_stats,
+ .get_rmon_stats = netc_port_get_rmon_stats,
+ .get_eth_ctrl_stats = netc_port_get_eth_ctrl_stats,
+ .get_eth_mac_stats = netc_port_get_eth_mac_stats,
};
static int netc_switch_probe(struct pci_dev *pdev,
diff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h
index 7ebffb136b2f..825601847c89 100644
--- a/drivers/net/dsa/netc/netc_switch.h
+++ b/drivers/net/dsa/netc/netc_switch.h
@@ -70,6 +70,11 @@ struct netc_port {
struct ipft_entry_data *host_flood;
};
+enum netc_port_mac {
+ NETC_PORT_EMAC = 0,
+ NETC_PORT_PMAC,
+};
+
struct netc_switch_regs {
void __iomem *base;
void __iomem *port;
@@ -110,6 +115,7 @@ struct netc_switch {
/* Write/Read registers of Switch Port (including pseudo MAC port) */
#define netc_port_rd(p, o) netc_read((p)->iobase + (o))
+#define netc_port_rd64(p, o) netc_read64((p)->iobase + (o))
#define netc_port_wr(p, o, v) netc_write((p)->iobase + (o), v)
/* Write/Read Switch global registers */
@@ -135,4 +141,15 @@ static inline void netc_del_fdb_entry(struct netc_fdb_entry *entry)
int netc_switch_platform_probe(struct netc_switch *priv);
+/* ethtool APIs */
+void netc_port_get_pause_stats(struct dsa_switch *ds, int port,
+ struct ethtool_pause_stats *pause_stats);
+void netc_port_get_rmon_stats(struct dsa_switch *ds, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges);
+void netc_port_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats);
+void netc_port_get_eth_mac_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_mac_stats *mac_stats);
+
#endif
diff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h
index 1e1c0d279a21..05a1c3e239fa 100644
--- a/drivers/net/dsa/netc/netc_switch_hw.h
+++ b/drivers/net/dsa/netc/netc_switch_hw.h
@@ -172,6 +172,159 @@ enum netc_stg_stage {
#define SSP_10M 1
#define SSP_1G 2
+/* Port MAC 0/1 Receive Ethernet Octets Counter */
+#define NETC_PM_REOCT(a) (0x1100 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Octets Counter */
+#define NETC_PM_ROCT(a) (0x1108 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Alignment Error Counter Register */
+#define NETC_PM_RALN(a) (0x1110 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Valid Pause Frame Counter */
+#define NETC_PM_RXPF(a) (0x1118 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Frame Counter */
+#define NETC_PM_RFRM(a) (0x1120 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Frame Check Sequence Error Counter */
+#define NETC_PM_RFCS(a) (0x1128 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive VLAN Frame Counter */
+#define NETC_PM_RVLAN(a) (0x1130 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Frame Error Counter */
+#define NETC_PM_RERR(a) (0x1138 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Unicast Frame Counter */
+#define NETC_PM_RUCA(a) (0x1140 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Multicast Frame Counter */
+#define NETC_PM_RMCA(a) (0x1148 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Broadcast Frame Counter */
+#define NETC_PM_RBCA(a) (0x1150 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Dropped Packets Counter */
+#define NETC_PM_RDRP(a) (0x1158 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Packets Counter */
+#define NETC_PM_RPKT(a) (0x1160 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Undersized Packet Counter */
+#define NETC_PM_RUND(a) (0x1168 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive 64-Octet Packet Counter */
+#define NETC_PM_R64(a) (0x1170 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive 65 to 127-Octet Packet Counter */
+#define NETC_PM_R127(a) (0x1178 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive 128 to 255-Octet Packet Counter */
+#define NETC_PM_R255(a) (0x1180 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive 256 to 511-Octet Packet Counter */
+#define NETC_PM_R511(a) (0x1188 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive 512 to 1023-Octet Packet Counter */
+#define NETC_PM_R1023(a) (0x1190 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive 1024 to 1522-Octet Packet Counter */
+#define NETC_PM_R1522(a) (0x1198 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive 1523 to Max-Octet Packet Counter */
+#define NETC_PM_R1523X(a) (0x11a0 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Oversized Packet Counter */
+#define NETC_PM_ROVR(a) (0x11a8 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Jabber Packet Counter */
+#define NETC_PM_RJBR(a) (0x11b0 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Fragment Packet Counter */
+#define NETC_PM_RFRG(a) (0x11b8 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Control Packet Counter */
+#define NETC_PM_RCNP(a) (0x11c0 + (a) * 0x400)
+
+/* Port MAC 0/1 Receive Dropped Not Truncated Packets Counter */
+#define NETC_PM_RDRNTP(a) (0x11c8 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Ethernet Octets Counter */
+#define NETC_PM_TEOCT(a) (0x1200 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Octets Counter */
+#define NETC_PM_TOCT(a) (0x1208 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Valid Pause Frame Counter */
+#define NETC_PM_TXPF(a) (0x1218 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Frame Counter */
+#define NETC_PM_TFRM(a) (0x1220 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Frame Check Sequence Error Counter */
+#define NETC_PM_TFCS(a) (0x1228 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit VLAN Frame Counter */
+#define NETC_PM_TVLAN(a) (0x1230 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Frame Error Counter */
+#define NETC_PM_TERR(a) (0x1238 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Unicast Frame Counter */
+#define NETC_PM_TUCA(a) (0x1240 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Multicast Frame Counter */
+#define NETC_PM_TMCA(a) (0x1248 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Broadcast Frame Counter */
+#define NETC_PM_TBCA(a) (0x1250 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Packets Counter */
+#define NETC_PM_TPKT(a) (0x1260 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Undersized Packet Counter */
+#define NETC_PM_TUND(a) (0x1268 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit 64-Octet Packet Counter */
+#define NETC_PM_T64(a) (0x1270 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit 65 to 127-Octet Packet Counter */
+#define NETC_PM_T127(a) (0x1278 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit 128 to 255-Octet Packet Counter */
+#define NETC_PM_T255(a) (0x1280 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit 256 to 511-Octet Packet Counter */
+#define NETC_PM_T511(a) (0x1288 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit 512 to 1023-Octet Packet Counter */
+#define NETC_PM_T1023(a) (0x1290 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit 1024 to 1522-Octet Packet Counter */
+#define NETC_PM_T1522(a) (0x1298 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit 1523 to TX_MTU-Octet Packet Counter */
+#define NETC_PM_T1523X(a) (0x12a0 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Control Packet Counter */
+#define NETC_PM_TCNP(a) (0x12c0 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Deferred Packet Counter */
+#define NETC_PM_TDFR(a) (0x12d0 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Multiple Collisions Counter */
+#define NETC_PM_TMCOL(a) (0x12d8 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Single Collision */
+#define NETC_PM_TSCOL(a) (0x12e0 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Late Collision Counter */
+#define NETC_PM_TLCOL(a) (0x12e8 + (a) * 0x400)
+
+/* Port MAC 0/1 Transmit Excessive Collisions Counter */
+#define NETC_PM_TECOL(a) (0x12f0 + (a) * 0x400)
+
#define NETC_PEMDIOCR 0x1c00
#define NETC_EMDIO_BASE NETC_PEMDIOCR
diff --git a/include/linux/fsl/netc_global.h b/include/linux/fsl/netc_global.h
index fdecca8c90f0..5b8ff528d369 100644
--- a/include/linux/fsl/netc_global.h
+++ b/include/linux/fsl/netc_global.h
@@ -5,6 +5,7 @@
#define __NETC_GLOBAL_H
#include <linux/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
static inline u32 netc_read(void __iomem *reg)
{
@@ -16,4 +17,9 @@ static inline void netc_write(void __iomem *reg, u32 val)
iowrite32(val, reg);
}
+static inline u64 netc_read64(void __iomem *reg)
+{
+ return ioread64(reg);
+}
+
#endif
--
2.34.1
^ permalink raw reply related
* Re: [PATCH] ARM: dts: aspeed: anacapa: Add eeprom device node
From: Andrew Jeffery @ 2026-03-26 6:33 UTC (permalink / raw)
To: Colin Huang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2
In-Reply-To: <CAPBH0A9oatx7U2+3dvGVgonHEm+yq5TFM9mTcdStau2Lk1XytA@mail.gmail.com>
On Fri, 2026-03-06 at 14:06 +0800, Colin Huang wrote:
> Hi Andrew,
>
> Thanks for the feedback.
>
> In our case the only functional difference between DCSCM rev B/C and
> rev D is the EEPROM I²C address change (0x50 → 0x51).
> Other than this, the hardware is identical and all device-tree
> described components share the same wiring and behaviour.
>
> Maintaining two separate devicetrees for a single‑byte address shift
> doesn’t scale well for us.
I disagree that there's a problem of scale. The kernel's dts files are
processed with the C pre-processor - you can #include one file from
another. .dtsi files work this way, and as a related example, we
maintain two devicetrees for the AST2600 EVB where -A1 had some minor
differences in the regulator configuration:
* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts?h=v7.0-rc5
* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts?h=v7.0-rc5
See also my response to Kevin Tung earlier:
https://lore.kernel.org/all/d7794f74b26bbc1ee0a70e39c5671acc018f80eb.camel@codeconstruct.com.au/
Andrew
^ permalink raw reply
* [PATCH 2/2] pwm: meson: Add support for Amlogic S7
From: Xianwei Zhao via B4 Relay @ 2026-03-26 6:35 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic, Xianwei Zhao
In-Reply-To: <20260326-s6-s7-pwm-v1-0-67e2f72b98bc@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add support for Amlogic S7 PWM. Amlogic S7 different from the
previous SoCs, a controller includes one pwm, at the same time,
the controller has only one input clock source.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
drivers/pwm/pwm-meson.c | 32 ++++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 8c6bf3d49753..3d16694e254e 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -113,6 +113,7 @@ struct meson_pwm_data {
int (*channels_init)(struct pwm_chip *chip);
bool has_constant;
bool has_polarity;
+ bool single_pwm;
};
struct meson_pwm {
@@ -503,6 +504,18 @@ static void meson_pwm_s4_put_clk(void *data)
clk_put(clk);
}
+static int meson_pwm_init_channels_s7(struct pwm_chip *chip)
+{
+ struct device *dev = pwmchip_parent(chip);
+ struct meson_pwm *meson = to_meson_pwm(chip);
+
+ meson->channels[0].clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(meson->channels[0].clk))
+ return dev_err_probe(dev, PTR_ERR(meson->channels[0].clk),
+ "Failed to get clk\n");
+ return 0;
+}
+
static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
{
struct device *dev = pwmchip_parent(chip);
@@ -592,6 +605,13 @@ static const struct meson_pwm_data pwm_s4_data = {
.has_polarity = true,
};
+static const struct meson_pwm_data pwm_s7_data = {
+ .channels_init = meson_pwm_init_channels_s7,
+ .has_constant = true,
+ .has_polarity = true,
+ .single_pwm = true,
+};
+
static const struct of_device_id meson_pwm_matches[] = {
{
.compatible = "amlogic,meson8-pwm-v2",
@@ -642,6 +662,10 @@ static const struct of_device_id meson_pwm_matches[] = {
.compatible = "amlogic,meson-s4-pwm",
.data = &pwm_s4_data
},
+ {
+ .compatible = "amlogic,s7-pwm",
+ .data = &pwm_s7_data
+ },
{},
};
MODULE_DEVICE_TABLE(of, meson_pwm_matches);
@@ -650,9 +674,13 @@ static int meson_pwm_probe(struct platform_device *pdev)
{
struct pwm_chip *chip;
struct meson_pwm *meson;
+ const struct meson_pwm_data *pdata = of_device_get_match_data(&pdev->dev);
int err;
- chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson));
+ if (pdata->single_pwm)
+ chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*meson));
+ else
+ chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson));
if (IS_ERR(chip))
return PTR_ERR(chip);
meson = to_meson_pwm(chip);
@@ -664,7 +692,7 @@ static int meson_pwm_probe(struct platform_device *pdev)
spin_lock_init(&meson->lock);
chip->ops = &meson_pwm_ops;
- meson->data = of_device_get_match_data(&pdev->dev);
+ meson->data = pdata;
err = meson->data->channels_init(chip);
if (err < 0)
--
2.52.0
^ permalink raw reply related
* [PATCH 0/2] Add PWM support Amlogic S7 S7D S6
From: Xianwei Zhao via B4 Relay @ 2026-03-26 6:35 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic, Xianwei Zhao, Junyi Zhao
Add bindings and driver support Amlogic S7/S7D/S6 SoCs.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Junyi Zhao (1):
dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D
Xianwei Zhao (1):
pwm: meson: Add support for Amlogic S7
.../devicetree/bindings/pwm/pwm-amlogic.yaml | 27 ++++++++++++++++++
drivers/pwm/pwm-meson.c | 32 ++++++++++++++++++++--
2 files changed, 57 insertions(+), 2 deletions(-)
---
base-commit: 8ab1fc9104158045f68fde2d0ae16f5fbcf8bfbd
change-id: 20260325-s6-s7-pwm-281658b88736
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D
From: Xianwei Zhao via B4 Relay @ 2026-03-26 6:35 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic, Xianwei Zhao, Junyi Zhao
In-Reply-To: <20260326-s6-s7-pwm-v1-0-67e2f72b98bc@amlogic.com>
From: Junyi Zhao <junyi.zhao@amlogic.com>
Amlogic S7/S7D/S6 different from the previous SoCs, a controller
includes one pwm, at the same time, the controller has only one
input clock source.
Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
.../devicetree/bindings/pwm/pwm-amlogic.yaml | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
index c337d85da40f..f0c40dc359ad 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
@@ -37,6 +37,7 @@ properties:
- enum:
- amlogic,meson8-pwm-v2
- amlogic,meson-s4-pwm
+ - amlogic,s7-pwm
- items:
- enum:
- amlogic,a4-pwm
@@ -45,6 +46,11 @@ properties:
- amlogic,t7-pwm
- amlogic,meson-a1-pwm
- const: amlogic,meson-s4-pwm
+ - items:
+ - enum:
+ - amlogic,s6-pwm
+ - amlogic,s7d-pwm
+ - const: amlogic,s7-pwm
- items:
- enum:
- amlogic,meson8b-pwm-v2
@@ -146,6 +152,20 @@ allOf:
clock-names: false
required:
- clocks
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,s7-pwm
+ then:
+ properties:
+ clocks:
+ items:
+ - description: input clock of PWM
+ clock-names: false
+ required:
+ - clocks
- if:
properties:
@@ -182,3 +202,10 @@ examples:
clocks = <&pwm_src_a>, <&pwm_src_b>;
#pwm-cells = <3>;
};
+ - |
+ pwm@1000 {
+ compatible = "amlogic,s7-pwm";
+ reg = <0x1000 0x10>;
+ clocks = <&pwm_src>;
+ #pwm-cells = <3>;
+ };
--
2.52.0
^ permalink raw reply related
* Re: [PATCH v2 1/3] clk: mediatek: add MUX_CLR_SET macro
From: Chen-Yu Tsai @ 2026-03-26 6:37 UTC (permalink / raw)
To: Daniel Golle
Cc: Michael Turquette, Stephen Boyd, Matthias Brugger,
AngeloGioacchino Del Regno, Nícolas F. R. A. Prado,
Laura Nao, Weiyi Lu, Chun-Jie Chen, Ikjoon Jang, Sam Shih,
linux-clk, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <65e504ac2c2d19b4baba6b79a241788220b19b34.1774499536.git.daniel@makrotopia.org>
On Thu, Mar 26, 2026 at 1:09 PM Daniel Golle <daniel@makrotopia.org> wrote:
>
> Some MediaTek SoCs (e.g. MT7988) define infra muxes that have neither
> a clock gate nor an update register.
>
> Add a MUX_CLR_SET convenience macro that takes only the mux register
> offsets, bit shift, and width, hardcoding upd_ofs = 0 and
> upd_shift = -1 so callers cannot accidentally pass bogus sentinel
> values to wrongly-typed fields.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply
* Re: [PATCH v2 2/3] clk: mediatek: mt8192: use MUX_CLR_SET
From: Chen-Yu Tsai @ 2026-03-26 6:37 UTC (permalink / raw)
To: Daniel Golle
Cc: Michael Turquette, Stephen Boyd, Matthias Brugger,
AngeloGioacchino Del Regno, Nícolas F. R. A. Prado,
Laura Nao, Weiyi Lu, Chun-Jie Chen, Ikjoon Jang, Sam Shih,
linux-clk, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <9667e8a7a0757f7fb9d6bb3fca105df97afd007b.1774499536.git.daniel@makrotopia.org>
On Thu, Mar 26, 2026 at 1:10 PM Daniel Golle <daniel@makrotopia.org> wrote:
>
> The mfg_pll_sel mux has neither a clock gate nor an update register,
> and upd_ofs is stored as u32, so the -1 truncates to 0xFFFFFFFF.
>
> While upd_shift being -1 (as s8) prevents the update path from
> executing at runtime, the bogus upd_ofs value is still stored in the
> struct.
>
> Use MUX_CLR_SET to avoid passing sentinel values to wrongly-typed
> fields.
>
> Fixes: 710573dee31b4 ("clk: mediatek: Add MT8192 basic clocks support")
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply
* Re: [PATCH v2 3/3] clk: mediatek: mt7988: use MUX_CLR_SET for gate-less muxes
From: Chen-Yu Tsai @ 2026-03-26 6:39 UTC (permalink / raw)
To: Daniel Golle
Cc: Michael Turquette, Stephen Boyd, Matthias Brugger,
AngeloGioacchino Del Regno, Nícolas F. R. A. Prado,
Laura Nao, Weiyi Lu, Chun-Jie Chen, Ikjoon Jang, Sam Shih,
linux-clk, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <d1a9b393d9929dc670dc6d5bfcc5cd43561d0be4.1774499536.git.daniel@makrotopia.org>
On Thu, Mar 26, 2026 at 1:11 PM Daniel Golle <daniel@makrotopia.org> wrote:
>
> All 19 muxes in the infra_muxes[] array are pure mux selectors without
> a clock gate or update register, yet they were defined using
> MUX_GATE_CLR_SET_UPD with gate_shift = -1.
>
> This macro assigns mtk_mux_gate_clr_set_upd_ops, whose
> enable/disable/is_enabled callbacks perform BIT(gate_shift). Since
> gate_shift is stored as u8, the -1 truncates to 255, causing a
> shift-out-of-bounds at runtime:
>
> UBSAN: shift-out-of-bounds in drivers/clk/mediatek/clk-mux.c:76:8
> shift exponent 255 is too large for 64-bit type 'long unsigned int'
>
> UBSAN: shift-out-of-bounds in drivers/clk/mediatek/clk-mux.c:102:4
> shift exponent 255 is too large for 64-bit type 'long unsigned int'
>
> UBSAN: shift-out-of-bounds in drivers/clk/mediatek/clk-mux.c:122:16
> shift exponent 255 is too large for 64-bit type 'long unsigned int'
>
> Switch these definitions to MUX_CLR_SET, which uses
> mtk_mux_clr_set_upd_ops (no gate callbacks) and does not require
> callers to pass sentinel values for unused update register fields.
> The actual clock gating for these peripherals is handled by the
> separate GATE_INFRA* definitions further down.
>
> Fixes: 4b4719437d85f ("clk: mediatek: add drivers for MT7988 SoC")
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply
* Re: [PATCH v3 2/3] ARM: dts: aspeed: anacapa: update SGPIO mappings for DFT integration
From: Andrew Jeffery @ 2026-03-26 6:43 UTC (permalink / raw)
To: Colin Huang, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
Colin.Huang2, Carl.Lee, Peter.Shen
In-Reply-To: <20260310-anacapa-dts-sgpio-v3-2-12d9b7f1202e@gmail.com>
Hi Colin,
On Tue, 2026-03-10 at 17:49 +0800, Colin Huang wrote:
> Update SGPIOM0 GPIO line names and signal mappings to align with the
> latest DFT (Design For Tooling) integration requirements.
>
> This change reworks SGPIO input/output assignments, replaces legacy
> or reserved placeholders, and updates signal naming to match the
> definitions provided by the CPLD on 2026-03-03.
>
I feel this statement isn't super helpful, but no matter.
> The update improves
> signal clarity and correctness across leakage detection, presence,
> fault, power-good, and debug-related GPIOs.
I prefer you drop this assessment.
>
> Signed-off-by: Colin Huang <u8813345@gmail.com>
> ---
> .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 143 ++++++++++++---------
> 1 file changed, 83 insertions(+), 60 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> index 3e297abc5ba4..85b7e027daef 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> @@ -862,89 +862,106 @@ &sgpiom0 {
> ngpios = <128>;
> bus-frequency = <2000000>;
> gpio-line-names =
> - /*in - out - in - out */
> + /*in - out */
> /* A0-A7 line 0-15 */
> - "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N",
> - "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0",
> - "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle",
> - "", "", "", "",
> + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N",
> + "L_BNIC0_FLT", "CPU0_KBRST_N",
> + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N",
> + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0",
> + "L_BNIC3_FLT", "Force_I3C_SEL",
> + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle",
> + "", "",
> + "", "",
>
> /* B0-B7 line 16-31 */
> "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
> "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
> "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
> "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
> - "Channel4_leakage_Manifold2", "",
> - "Channel5_leakage_EAM1", "",
> - "Channel6_leakage_CPU_DIMM", "",
> - "Channel7_leakage_EAM2", "",
> + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L",
> + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L",
> + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330",
> + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331",
>
> /* C0-C7 line 32-47 */
> - "RSVD_RMC_GPIO3", "", "LEAK_DETECT_RMC_N", "",
> - "", "", "", "",
> - "", "", "", "",
> - "", "", "", "",
> + "RSVD_RMC_GPIO3", "RTM_MUX_L",
> + "LEAK_DETECT_RMC_N", "RTM_MUX_R",
> + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N",
> + "No_Leak_Sensor_flag", "whdt_sel",
> + "", "",
> + "", "",
> + "", "",
> + "", "",
>
> /* D0-D7 line 48-63 */
> - "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "",
> - "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "",
> - "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "",
> - "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "",
> - "AMC_BRD_PRSNT_CPLD_L", "", "", "",
> - "", "", "", "",
> + "PWRGD_CHAD_CPU0_FPGA", "",
> + "PWRGD_CHEH_CPU0_FPGA", "",
> + "PWRGD_CHIL_CPU0_FPGA", "",
> + "PWRGD_CHMP_CPU0_FPGA", "",
> + "AMC_BRD_PRSNT_CPLD_L", "",
Can you discuss this patch in the context of my other replies to both
yourself and Kevin?
https://lore.kernel.org/all/d7794f74b26bbc1ee0a70e39c5671acc018f80eb.camel@codeconstruct.com.au/
Andrew
^ permalink raw reply
* Re: [PATCH v3 0/2] Add Meta (Facebook) SanMiguel BMC (AST2620)
From: Andrew Jeffery @ 2026-03-26 6:47 UTC (permalink / raw)
To: Potin Lai, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Patrick Williams
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
Cosmo Chou, Mike Hsieh, Potin Lai, Conor Dooley
In-Reply-To: <20260311-sanmiguel_init_dts-v3-0-2b4d1ab7a8a1@gmail.com>
Hi Potin,
On Wed, 2026-03-11 at 14:19 +0800, Potin Lai wrote:
> Add Linux device tree entries for Meta (Facebook) SanMiguel specific
> devices connected to the AST2620 BMC SoC.
>
> Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
> ---
> Changes in v3:
> - Update the model name to "Facebook SanMiguel BMC".
> - Remove CP2112 and downstream IOEXP nodes as the upstream driver
> is not yet available.
> - Remove the following EEPROM nodes until the bus numbers and
> addresses are confirmed:
> - 3-0051: HMC FRU EEPROM
> - 3-0052: HPM0 FRU EEPROM
> - 3-0053: HPM1 FRU EEPROM
> - Change the compatible property of the following EEPROM nodes
> from 24c02 to 24c128:
> - 5-0050: SMM FRU EEPROM
> - 9-0050: PDB FRU EEPROM
> - 13-0055: SMM EXT FRU EEPROM
> - Fix the smm_temp node address typo (0x4e -> 0x48).
> - Remove nodes that no longer exist in the latest board design:
> - 19-006f: RTC (nct3018y)
> - 9-0075: IO expander (pca9555)
> - Update linenames to match the reference design:
> - B0_M0_AIC_USB_EN-O -> B0_M0_CPU_L0_RST_IND_L-O
> - B0_M0_BRD_ID_2-I -> B0_M0_BMC_TO_GPU_MCU_I2C_EN-O
> - B1_M0_AIC_USB_EN-O -> B1_M0_CPU_L0_RST_IND_L-O
> - B1_M0_BRD_ID_2-I -> B1_M0_BMC_TO_GPU_MCU_I2C_EN-O
> - IOX_GPIO_P16_TP -> USB2_BMC_HUB2_RST_L-O
> - I2C_PDB_ALERT_L-I -> X86_TPM_RST_SEL_L-O
> - Remove unexpected or unsupported properties from SSIF and IOEXP
> nodes.
> - Change all status values from "ok" to "okay" for consistency.
> - Link to v2: https://lore.kernel.org/r/20260203-sanmiguel_init_dts-v2-0-6a5682c32b38@gmail.com
Can you please discuss these proposed changes in the context of my
reply to Kevin below?
https://lore.kernel.org/all/d7794f74b26bbc1ee0a70e39c5671acc018f80eb.camel@codeconstruct.com.au/
Thanks,
Andrew
^ permalink raw reply
* [PATCH v5] nvme: Skip trace complete_rq on host path error
From: 전민식 @ 2026-03-26 6:51 UTC (permalink / raw)
To: hch@lst.de
Cc: Keith Busch, Justin Tee, axboe@kernel.dk, sven@kernel.org,
j@jannau.net, neal@gompa.dev, sagi@grimberg.me,
justin.tee@broadcom.com, nareshgottumukkala83@gmail.com,
paul.ely@broadcom.com, James Smart, kch@nvidia.com,
linux-arm-kernel@lists.infradead.org,
linux-nvme@lists.infradead.org, asahi@lists.linux.dev,
linux-kernel@vger.kernel.org, 이은수,
칸찬, 전민식
In-Reply-To: <20260326061443.GA23850@lst.de>
Hi hch,
I added a comment about why I do trace skip if it's host path error.
Thanks
Regards,
Minsik Jeon
From 3ee001c00cb4c7843d7bbb0c11fcc1fafeded9b4 Mon Sep 17 00:00:00 2001
From: Minsik Jeon <hmi.jeon@samsung.com>
Date: Thu, 26 Mar 2026 11:09:57 +0900
Subject: [PATCH v5] nvme: Skip trace complete_rq on host path error
we were checking host_pathing_error before calling nvme_setup_cmd().
This is caused the command setup to be skipped entirely when a pathing
error occurred, making it impossible to trace the nvme command via
trace_cmd nvme_complete_rq().
As a result, when nvme_complete_rq() logged a completion with cmdid=0,
it was impossible to correlate the completion with the nvme command
request.
This patch Skip trace_nvme_complete_rq() on NVMe host path error.
Co-authored-by: Beomsoo Kim <beomsooo.kim@samsung.com>
Co-authored-by: Eunsoo Lee <euns212.lee@samsung.com>
Co-authored-by: Steven Seungcheol Lee <sc108.lee@samsung.com>
Signed-off-by: Minsik Jeon <hmi.jeon@samsung.com>
---
drivers/nvme/host/core.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 766e9cc4ffca..df5a47b8560d 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -458,7 +458,14 @@ void nvme_complete_rq(struct request *req)
{
struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
- trace_nvme_complete_rq(req);
+ /*
+ * The idea for these trace events was to match up commands
+ * dispatched to hardware with the hardware's posted response.
+ * So skip tracing for undispatched commands.
+ */
+ if (nvme_req(req)->status != NVME_SC_HOST_PATH_ERROR)
+ trace_nvme_complete_rq(req);
+
nvme_cleanup_cmd(req);
/*
--
2.52.0
^ permalink raw reply related
* Re: [PATCH] soc: aspeed: cleanup dead default for ASPEED_SOCINFO
From: Andrew Jeffery @ 2026-03-26 6:57 UTC (permalink / raw)
To: joel, Julian Braha; +Cc: linux-arm-kernel, linux-aspeed, linux-kernel
In-Reply-To: <20260322230223.1393885-1-julianbraha@gmail.com>
On Sun, 22 Mar 2026 23:02:23 +0000, Julian Braha wrote:
> The same kconfig 'default' statement appears twice for ASPEED_SOCINFO,
> which is unnecessary.
>
> This dead code was found by kconfirm, a static analysis tool for Kconfig.
Thanks, I've applied this to the BMC tree.
--
Andrew Jeffery <andrew@codeconstruct.com.au>
^ permalink raw reply
* Re: [PATCH v2 0/4] drm/gem-dma: Support dedicated DMA device for allocation
From: Chen-Yu Tsai @ 2026-03-26 6:58 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu,
Philipp Zabel, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
David Airlie, Simona Vetter, Chen-Yu Tsai
Cc: linux-sunxi, Paul Kocialkowski, linux-mediatek, dri-devel,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260311094929.3393338-1-wenst@chromium.org>
On Wed, 11 Mar 2026 17:49:24 +0800, Chen-Yu Tsai wrote:
> This is v2 of my "support dedicated DMA device for allocation and mmap
> in GEM DMA helpers" series.
>
> Changes since v1:
> - Link to v1: https://lore.kernel.org/all/20260310032511.2545500-1-wenst@chromium.org/
> - Collected tags
> - Removed reference to mtk_gem.c from the Makefile
>
> [...]
Applied to drm-misc-next in drm-misc, thanks!
[1/4] drm/prime: Limit scatter list size with dedicated DMA device
commit: 864279920b2b2c1dd491eba0d0c64764c0c03d9f
[2/4] drm/gem-dma: Support dedicated DMA device for allocation and mapping
commit: a9da24732aaa80d631bffc8a1390836d4b896690
[3/4] drm/mediatek: Set dedicated DMA device and drop custom GEM callbacks
commit: e21b1a91430d5ff626a35f72951ed80268e26de6
[4/4] drm/sun4i: Use backend/mixer as dedicated DMA device
commit: 25e90f486f5bc8f606f4263c9d86e2d2b1db4613
Best regards,
--
Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply
* Re: [PATCH 1/1] arm64: defconfig: Enable options for CIX Sky1 SoC
From: Krzysztof Kozlowski @ 2026-03-26 7:14 UTC (permalink / raw)
To: Peter Chen, arnd
Cc: geert+renesas, linux-kernel, linux-arm-kernel, Yunseong Kim
In-Reply-To: <20260326033939.3789800-1-peter.chen@cixtech.com>
On 26/03/2026 04:39, Peter Chen wrote:
> Enable pinctrl, gpio, pcie and hda audio support.
Why?
Please search within similar patches for explanation how why this is not
enough and what should be here.
Best regards,
Krzysztof
^ permalink raw reply
* RE: [PATCH v2 0/9] accel: New driver for NXP's Neutron NPU
From: Ioana Ciocoi Radulescu @ 2026-03-26 7:18 UTC (permalink / raw)
To: Tomeu Vizoso
Cc: Oded Gabbay, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Simona Vetter, Sumit Semwal, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Frank Li,
Christian König, dri-devel@lists.freedesktop.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org,
linaro-mm-sig@lists.linaro.org, Jiwei Fu, Forrest Shi,
Alexandru Iulian Taran, Daniel Baluta
In-Reply-To: <CAPsqS2QXcgbi9_e4QmCn1Cgkr-bOVsY-E9qpZsFw3WYWWLugEw@mail.gmail.com>
On Tuesday, March 24, 2026 at 6:40 PM, Tomeu Vizoso wrote:
> > >
> > > Hi Ioana,
> > >
> > > Looks like the userspace portion of the driver is closed source
> > > (libNeutronDriver.so)?
> > >
> > > https://github.com/nxp-imx/tflite-neutron-delegate/blob/lf-6.12.49_2.2.0/CMakeLists.txt
> > Hi Tomeu,
> >
> > Yes, it's closed for now. We do plan to publish the source code
> > on github, but I believe that's still a few months away.
> I think you may want to sync with your userspace team sooner rather than
> later, so you can comply with this requirement:
>
> https://docs.kernel.org/gpu/drm-uapi.html#open-source-userspace-requirements
Thanks for bringing this up, it helps us raise internally the priority for
the userspace side. In the meantime, I still hope to gather additional
feedback on the kernel driver.
> It could be good to also share firmware code with other firmware-mediated
> NPU drivers if possible, or at least the part of the rpmsg protocol that
> makes sense to share.
>
> You can see my submission for the Thames driver for a link to the firmware
> code.
>
> I would be happy to help consolidate code between this category of drivers
> if you want.
Thanks for the offer. We are considering our options, I'll get back once we
reach an internal decision.
Regards,
Ioana
^ permalink raw reply
* [PATCH] arm64: dts: ti: k3-j721e: Fix QSGMII overlay by adding SERDES PHY
From: Chintan Vankar @ 2026-03-26 7:22 UTC (permalink / raw)
To: Andrew Davis, Siddharth Vadapalli, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, c-vankar
For CPSW9G QSGMII ports, CPSW assumes SERDES to be configured. Since it
may not be always true, add SERDES phys to guarantee it.
Fixes: 86e7de8bf908 ("arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode")
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
This patch is based on commit "0138af2472df" of origin/master branch
of Linux repo.
arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
index 8376fa4b6ee1..d403a3db0265 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
@@ -42,7 +42,8 @@ &cpsw0_port2 {
phy-handle = <&cpsw9g_phy1>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
- phys = <&cpsw0_phy_gmii_sel 2>;
+ phys = <&cpsw0_phy_gmii_sel 2>, <&serdes0_qsgmii_link>;
+ phy-names = "mac", "serdes";
};
&cpsw0_port3 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 00/12] arm64: dts: imx8mp: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan,
Kieran Bingham
As reported in [1], there is interrupt storm for i.MX8MP DEBIX Model A.
Per schematic, there is no on board PULL-UP resistors for GPIO1_IO03,
so need to set PAD PUE and PU together to make pull up work properly.
DEBIX Model SOM also has same issue as reported in [2].
I gave a check on current i.MX8MP based boards, most boards have wrong
PAD settings with PMIC_nINT. It is low level triggered interrupt.
many boards only set PU, but PUE not set, so pull up not work properly.
Patch 1 and 2 are to fix issue that confirmed by Laurent and Kieran.
I checked AB2 and NAVQ schematic, so these two boards are also having
same issue.
For other boards, I not able to find any public schematics. For per
the DT settings(interrupt is configured LOW LEVEL trigger), so PMIC_nINT
should be configured as PULL UP, per NXP reference design, there is no
on-board resistors for PMIC_nINT, it counts on SoC internal PULL. So I think
these boards are also having issues. But I use phase "there might be" in
commit log.
The last two patches, I think the PAD settings are wrong, but not sure
they have interrupt storm issues, so just correct the settings.
For imx8mp-skov-reva.dtsi, I am not sure whether it needs same fix, so
not touch it.
[1] https://lore.kernel.org/all/20260323105858.GA2185714@killaraus.ideasonboard.com/
[2] https://lore.kernel.org/all/20260324194353.GB2352505@killaraus.ideasonboard.com/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Changes in V2:
- Fix more boards
- Drop preceding zero
- Link to v1: https://lore.kernel.org/all/20260324-imx8mp-dts-fix-v1-1-df0eb2f62543@nxp.com/
---
Peng Fan (12):
arm64: dts: imx8mp-debix-model-a: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-debix-som-a: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-navqp: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-ab2: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-icore-mx8mp: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-edm-g: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-aristainetos3a-som-v1: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-nitrogen-som: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-sr-som: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-ultra-mach-sbc: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT
arch/arm64/boot/dts/freescale/imx8mp-ab2.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 4 ++--
arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts | 4 ++--
13 files changed, 15 insertions(+), 15 deletions(-)
---
base-commit: 66ba480978ce390e631e870b740a3406e3eb6b01
change-id: 20260326-imx8mp-dts-fix-v2-89ede7320c6a
Best regards,
--
Peng Fan <peng.fan@nxp.com>
^ permalink raw reply
* [PATCH v2 01/12] arm64: dts: imx8mp-debix-model-a: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there is interrupt storm for i.MX8MP DEBIX Model A. Per schematic, there
is no on board PULL-UP resistors for GPIO1_IO03, so need to set PAD
PUE and PU together to make pull up work properly.
Fixes: c86d350aae68e ("arm64: dts: Add device tree for the Debix Model A Board")
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Closes: https://lore.kernel.org/all/20260323105858.GA2185714@killaraus.ideasonboard.com/
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
index 9422beee30b29c5a551b08476c80fbff96af3439..201cf7f5eb0ea0d6aa60c4fefffc5d0052224d08 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
@@ -440,7 +440,7 @@ MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 02/12] arm64: dts: imx8mp-debix-som-a: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan,
Kieran Bingham
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there is interrupt storm for i.MX8MP DEBIX SOM A. Need to set PAD
PUE and PU together to make pull up work properly.
Fixes: 21baf0b47f81b ("arm64: dts: freescale: Add DEBIX SOM A and SOM A I/O Board support")
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Closes: https://lore.kernel.org/all/20260323105858.GA2185714@killaraus.ideasonboard.com/
Reported-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Closes: https://lore.kernel.org/imx/20260324194353.GB2352505@killaraus.ideasonboard.com/T/#m9a07fdc75496369a7d76d52c5e34ed140dcabfe3
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
index 04619a7229065be496611128ecf6848c9dd7102c..1471ff361b54cba05bb0e0734aa6e8d149309025 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
@@ -499,7 +499,7 @@ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140
pinctrl_pmic: pmicgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
index 91094c2277443c1585dfb7f31dccfb27aa1bcc8d..b31e8fe95ca74500fdc459aecfeb3f4b573f4244 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
@@ -241,7 +241,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
pinctrl_pmic: pmicgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 03/12] arm64: dts: imx8mp-navqp: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there will be interrupt storm for i.MX8MP NAVQP. Per schematic, there
is no on board PULL-UP resistors for GPIO1_IO03, so need to set PAD
PUE and PU together to make pull up work properly.
Fixes: 682729a9d506d ("arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
index 4a4f7c1adc23fe2615d8eb4904d795b46af4ca9f..9dedb9f11145ea842b4e718687dd153489ef4337 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
@@ -356,7 +356,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
pinctrl_pmic: pmicgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox