* [PATCH v2 4/4] KVM: arm64: selftests: Enhance hello_nested test
From: Wei-Lin Chang @ 2026-04-12 14:22 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, kvm, linux-kselftest, linux-kernel
Cc: Marc Zyngier, Oliver Upton, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Paolo Bonzini,
Shuah Khan, Wei-Lin Chang
In-Reply-To: <20260412142216.3806482-1-weilin.chang@arm.com>
Handle an "add" hypercall in L1 to add 2 numbers passed by L2, and
return the result. This better tests our save/restore functionality.
Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
---
.../selftests/kvm/arm64/hello_nested.c | 31 ++++++++++++++++++-
.../selftests/kvm/include/arm64/nested.h | 2 +-
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/kvm/arm64/hello_nested.c b/tools/testing/selftests/kvm/arm64/hello_nested.c
index 97387e4697b3..69f4d8e750e2 100644
--- a/tools/testing/selftests/kvm/arm64/hello_nested.c
+++ b/tools/testing/selftests/kvm/arm64/hello_nested.c
@@ -11,6 +11,10 @@
#define XLATE2GPA (0xABCD)
#define L2STACKSZ (0x100)
+#define L2SUCCESS (0x0)
+#define L2FAILED (0x1)
+#define L2ADD (0x2)
+
/*
* TPIDR_EL2 is used to store vcpu id, so save and restore it.
*/
@@ -31,7 +35,14 @@ static vm_paddr_t ucall_translate_to_gpa(void *gva)
static void l2_guest_code(void)
{
- do_hvc();
+ int ans = 0;
+
+ ans = do_hvc(L2ADD, 2, 3);
+
+ if (ans == 5)
+ do_hvc(L2SUCCESS, 0, 0);
+ else
+ do_hvc(L2FAILED, 0, 0);
}
static void guest_code(void)
@@ -42,6 +53,7 @@ static void guest_code(void)
vm_paddr_t l2_pc, l2_stack_top;
/* force 16-byte alignment for the stack pointer */
u8 l2_stack[L2STACKSZ] __attribute__((aligned(16)));
+ u64 arg1, arg2;
GUEST_ASSERT_EQ(get_current_el(), 2);
GUEST_PRINTF("vEL2 entry\n");
@@ -54,6 +66,23 @@ static void guest_code(void)
ret = run_l2(&vcpu, &hyp_data);
GUEST_ASSERT_EQ(ret, ARM_EXCEPTION_TRAP);
+
+ if (vcpu.context.regs.regs[0] == L2ADD) {
+ arg1 = vcpu.context.regs.regs[1];
+ arg2 = vcpu.context.regs.regs[2];
+ GUEST_PRINTF("L2 add request, arg1: %lx, arg2: %lx\n", arg1, arg2);
+ vcpu.context.regs.regs[0] = arg1 + arg2;
+ } else {
+ GUEST_FAIL("Unexpected hvc action\n");
+ }
+
+ ret = run_l2(&vcpu, &hyp_data);
+ GUEST_ASSERT_EQ(ret, ARM_EXCEPTION_TRAP);
+
+ if (vcpu.context.regs.regs[0] != L2SUCCESS)
+ GUEST_FAIL("L2 failed\n");
+
+ GUEST_PRINTF("L2 success!\n");
GUEST_DONE();
}
diff --git a/tools/testing/selftests/kvm/include/arm64/nested.h b/tools/testing/selftests/kvm/include/arm64/nested.h
index 7928ef89494a..b16a72488858 100644
--- a/tools/testing/selftests/kvm/include/arm64/nested.h
+++ b/tools/testing/selftests/kvm/include/arm64/nested.h
@@ -50,7 +50,7 @@ void prepare_hyp(void);
void init_vcpu(struct vcpu *vcpu, vm_paddr_t l2_pc, vm_paddr_t l2_stack_top);
int run_l2(struct vcpu *vcpu, struct hyp_data *hyp_data);
-void do_hvc(void);
+u64 do_hvc(u64 action, u64 arg1, u64 arg2);
u64 __guest_enter(struct vcpu *vcpu, struct cpu_context *hyp_context);
void __hyp_exception(u64 type);
--
2.43.0
^ permalink raw reply related
* [PATCH v2 3/4] KVM: arm64: sefltests: Add basic NV selftest
From: Wei-Lin Chang @ 2026-04-12 14:22 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, kvm, linux-kselftest, linux-kernel
Cc: Marc Zyngier, Oliver Upton, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Paolo Bonzini,
Shuah Khan, Wei-Lin Chang
In-Reply-To: <20260412142216.3806482-1-weilin.chang@arm.com>
This selftest simply starts an L1, which starts its own guest (L2). L2
runs without stage-1 and 2 translations, it calls an HVC to jump back
to L1.
Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
---
tools/testing/selftests/kvm/Makefile.kvm | 1 +
.../selftests/kvm/arm64/hello_nested.c | 103 ++++++++++++++++++
2 files changed, 104 insertions(+)
create mode 100644 tools/testing/selftests/kvm/arm64/hello_nested.c
diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selftests/kvm/Makefile.kvm
index 3dc3e39f7025..e8c108e0c487 100644
--- a/tools/testing/selftests/kvm/Makefile.kvm
+++ b/tools/testing/selftests/kvm/Makefile.kvm
@@ -168,6 +168,7 @@ TEST_GEN_PROGS_arm64 += arm64/arch_timer_edge_cases
TEST_GEN_PROGS_arm64 += arm64/at
TEST_GEN_PROGS_arm64 += arm64/debug-exceptions
TEST_GEN_PROGS_arm64 += arm64/hello_el2
+TEST_GEN_PROGS_arm64 += arm64/hello_nested
TEST_GEN_PROGS_arm64 += arm64/host_sve
TEST_GEN_PROGS_arm64 += arm64/hypercalls
TEST_GEN_PROGS_arm64 += arm64/external_aborts
diff --git a/tools/testing/selftests/kvm/arm64/hello_nested.c b/tools/testing/selftests/kvm/arm64/hello_nested.c
new file mode 100644
index 000000000000..97387e4697b3
--- /dev/null
+++ b/tools/testing/selftests/kvm/arm64/hello_nested.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * hello_nested - Go from vEL2 to EL1 then back
+ */
+
+#include "nested.h"
+#include "processor.h"
+#include "test_util.h"
+#include "ucall.h"
+
+#define XLATE2GPA (0xABCD)
+#define L2STACKSZ (0x100)
+
+/*
+ * TPIDR_EL2 is used to store vcpu id, so save and restore it.
+ */
+static vm_paddr_t ucall_translate_to_gpa(void *gva)
+{
+ vm_paddr_t gpa;
+ u64 vcpu_id = read_sysreg(tpidr_el2);
+
+ GUEST_SYNC2(XLATE2GPA, gva);
+
+ /* get the result from userspace */
+ gpa = read_sysreg(tpidr_el2);
+
+ write_sysreg(vcpu_id, tpidr_el2);
+
+ return gpa;
+}
+
+static void l2_guest_code(void)
+{
+ do_hvc();
+}
+
+static void guest_code(void)
+{
+ struct vcpu vcpu;
+ struct hyp_data hyp_data;
+ int ret;
+ vm_paddr_t l2_pc, l2_stack_top;
+ /* force 16-byte alignment for the stack pointer */
+ u8 l2_stack[L2STACKSZ] __attribute__((aligned(16)));
+
+ GUEST_ASSERT_EQ(get_current_el(), 2);
+ GUEST_PRINTF("vEL2 entry\n");
+
+ l2_pc = ucall_translate_to_gpa(l2_guest_code);
+ l2_stack_top = ucall_translate_to_gpa(&l2_stack[L2STACKSZ]);
+
+ init_vcpu(&vcpu, l2_pc, l2_stack_top);
+ prepare_hyp();
+
+ ret = run_l2(&vcpu, &hyp_data);
+ GUEST_ASSERT_EQ(ret, ARM_EXCEPTION_TRAP);
+ GUEST_DONE();
+}
+
+int main(void)
+{
+ struct kvm_vcpu_init init;
+ struct kvm_vcpu *vcpu;
+ struct kvm_vm *vm;
+ struct ucall uc;
+ vm_paddr_t gpa;
+
+ TEST_REQUIRE(kvm_check_cap(KVM_CAP_ARM_EL2));
+ vm = vm_create(1);
+
+ kvm_get_default_vcpu_target(vm, &init);
+ init.features[0] |= BIT(KVM_ARM_VCPU_HAS_EL2);
+ vcpu = aarch64_vcpu_add(vm, 0, &init, guest_code);
+ kvm_arch_vm_finalize_vcpus(vm);
+
+ while (true) {
+ vcpu_run(vcpu);
+
+ switch (get_ucall(vcpu, &uc)) {
+ case UCALL_SYNC:
+ if (uc.args[0] == XLATE2GPA) {
+ gpa = addr_gva2gpa(vm, (vm_vaddr_t)uc.args[1]);
+ vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL2), gpa);
+ }
+ break;
+ case UCALL_PRINTF:
+ pr_info("%s", uc.buffer);
+ break;
+ case UCALL_DONE:
+ pr_info("DONE!\n");
+ goto end;
+ case UCALL_ABORT:
+ REPORT_GUEST_ASSERT(uc);
+ fallthrough;
+ default:
+ TEST_FAIL("Unhandled ucall: %ld\n", uc.cmd);
+ }
+ }
+
+end:
+ kvm_vm_free(vm);
+ return 0;
+}
--
2.43.0
^ permalink raw reply related
* Re: [PATCH net-next] net: stmmac: enable RPS and RBU interrupts
From: Russell King (Oracle) @ 2026-04-12 14:23 UTC (permalink / raw)
To: Maxime Chevallier
Cc: Andrew Lunn, Alexandre Torgue, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, linux-arm-kernel, linux-stm32,
netdev, Paolo Abeni, Sam Edwards
In-Reply-To: <266998d8-7e38-4bae-a4df-2f889538fe88@bootlin.com>
On Sun, Apr 12, 2026 at 04:01:59PM +0200, Maxime Chevallier wrote:
> Hi Russell,
>
> On 10/04/2026 15:07, Russell King (Oracle) wrote:
> > Enable receive process stopped and receive buffer unavailable
> > interrupts, so that the statistic counters can be updated.
> >
> > Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> > ---
> > Since we are seeing receive buffer exhaustion on several platforms,
> > let's enable the interrupts so the statistics we publish via ethtool -S
> > actually work to aid diagnosis. I've been in two minds about whether
> > to send this patch, but given the problems with stmmac at the moment,
> > I think it should be merged.
>
> Looks like my reply to your original RFC was lost in limbo as the review/test tags are missing.
Thanks. Unfortunately, I can't run iperf3 against stmmac on the Jetson
NX because stmmac just totally screws itself (at the first RBU, the
receive side irrevocably collapses.)
Against i.MX6 (which is limited to around 480Mbps,) it's recoverable by
taking the interface down and back up a couple of times.
Against x86 (which will saturate the link) its pretty much
irrecoverable without entire system reboot - if one tries the down+up,
we then get arm-smmu errors because it seems that, despite stmmac being
reset, it still attempts to access a previous receive buffer from
before the down/up sometime after the up. Moreover, transmit stops
working - packets get queued but they are never processed by the
hardware. This is a scenario that I can only rarely test myself (as
it depends on my physical location.)
As the dwmac 5.0 core receive path seems to lock up after the first
RBU, I never see more than one of those at a time.
Right now, I consider this pretty much unsolvable - I've spent quite
some time looking at it and trying various approaches, nothing seems
to fix it. However, adding dma_rmb() in the descriptor cleanup/refill
paths does seem to improve the situation a little with the 480Mbps
case, because I think it means that we're reading the descriptors in
a more timely manner after the hardware has updated them.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH v2 4/5] coresight: etm3x: introduce struct etm_caps
From: Jie Gan @ 2026-04-12 14:24 UTC (permalink / raw)
To: Yeoreum Yun, coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan
In-Reply-To: <4feaf157-4015-471e-accf-d588e2345c13@oss.qualcomm.com>
On 4/12/2026 10:21 PM, Jie Gan wrote:
>
>
> On 4/10/2026 3:43 PM, Yeoreum Yun wrote:
>> Introduce struct etm_caps to describe ETMv3 capabilities
>> and move capabilities information into it.
>>
>> Since drvdata->etmccr and drvdata->etmccer are used to check
>> whether it supports fifofull logic and timestamping,
>> remove etmccr and etmccer field from drvdata and add relevant fields
>> in etm_caps structure.
>>
>> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
>> ---
>> drivers/hwtracing/coresight/coresight-etm.h | 40 +++++++++++--------
>> .../coresight/coresight-etm3x-core.c | 33 ++++++++-------
>> .../coresight/coresight-etm3x-sysfs.c | 14 ++++---
>> 3 files changed, 52 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/
>> hwtracing/coresight/coresight-etm.h
>> index 1d753cca2943..6fda26039db8 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm.h
>> +++ b/drivers/hwtracing/coresight/coresight-etm.h
>> @@ -140,6 +140,28 @@
>> ETM_ADD_COMP_0 | \
>> ETM_EVENT_NOT_A)
>> +/**
>> + * struct etmv4_caps - specifics ETM capabilities
>> + * @port_size: port size as reported by ETMCR bit 4-6 and 21.
>> + * @nr_addr_cmp:Number of pairs of address comparators as found in
>> ETMCCR.
>> + * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
>> + * @nr_ext_inp: Number of external input as found in ETMCCR bit
>> 17-19.
>> + * @nr_ext_out: Number of external output as found in ETMCCR bit
>> 20-22.
>> + * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR
>> bit 24-25.
>> + * @fifofull: FIFOFULL logic is present.
>> + * @timestamp: Timestamping is implemented.
>> + */
>> +struct etm_caps {
>> + int port_size;
>> + u8 nr_addr_cmp;
>> + u8 nr_cntr;
>> + u8 nr_ext_inp;
>> + u8 nr_ext_out;
>> + u8 nr_ctxid_cmp;
>> + bool fifofull : 1;
>> + bool timestamp : 1;
>> +};
>> +
>> /**
>> * struct etm_config - configuration information related to an ETM
>> * @mode: controls various modes supported by this ETM/PTM.
>> @@ -212,19 +234,12 @@ struct etm_config {
>> * @csdev: component vitals needed by the framework.
>> * @spinlock: only one at a time pls.
>> * @cpu: the cpu this component is affined to.
>> - * @port_size: port size as reported by ETMCR bit 4-6 and 21.
>> * @arch: ETM/PTM version number.
>> + * @caps: ETM capabilities.
>> * @use_cpu14: true if management registers need to be accessed
>> via CP14.
>> * @sticky_enable: true if ETM base configuration has been done.
>> * @boot_enable:true if we should start tracing at boot time.
>> * @os_unlock: true if access to management registers is allowed.
>> - * @nr_addr_cmp:Number of pairs of address comparators as found in
>> ETMCCR.
>> - * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
>> - * @nr_ext_inp: Number of external input as found in ETMCCR bit
>> 17-19.
>> - * @nr_ext_out: Number of external output as found in ETMCCR bit
>> 20-22.
>> - * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR
>> bit 24-25.
>> - * @etmccr: value of register ETMCCR.
>> - * @etmccer: value of register ETMCCER.
>> * @traceid: value of the current ID for this component.
>> * @config: structure holding configuration parameters.
>> */
>> @@ -234,19 +249,12 @@ struct etm_drvdata {
>> struct coresight_device *csdev;
>> spinlock_t spinlock;
>> int cpu;
>> - int port_size;
>> u8 arch;
>> + struct etm_caps caps;
>> bool use_cp14;
>> bool sticky_enable;
>> bool boot_enable;
>> bool os_unlock;
>> - u8 nr_addr_cmp;
>> - u8 nr_cntr;
>> - u8 nr_ext_inp;
>> - u8 nr_ext_out;
>> - u8 nr_ctxid_cmp;
>> - u32 etmccr;
>> - u32 etmccer;
>> u32 traceid;
>> struct etm_config config;
>> };
>> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/
>> drivers/hwtracing/coresight/coresight-etm3x-core.c
>> index a547a6d2e0bd..b7e977defb1c 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
>> @@ -367,6 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
>> {
>> int i, rc;
>> u32 etmcr;
>> + const struct etm_caps *caps = &drvdata->caps;
>> struct etm_config *config = &drvdata->config;
>> struct coresight_device *csdev = drvdata->csdev;
>> @@ -388,7 +389,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
>> etmcr = etm_readl(drvdata, ETMCR);
>> /* Clear setting from a previous run if need be */
>> etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
>> - etmcr |= drvdata->port_size;
>> + etmcr |= caps->port_size;
>> etmcr |= ETMCR_ETM_EN;
>> etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
>> etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
>> @@ -396,11 +397,11 @@ static int etm_enable_hw(struct etm_drvdata
>> *drvdata)
>> etm_writel(drvdata, config->enable_event, ETMTEEVR);
>> etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
>> etm_writel(drvdata, config->fifofull_level, ETMFFLR);
>> - for (i = 0; i < drvdata->nr_addr_cmp; i++) {
>> + for (i = 0; i < caps->nr_addr_cmp; i++) {
>> etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
>> etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
>> }
>> - for (i = 0; i < drvdata->nr_cntr; i++) {
>> + for (i = 0; i < caps->nr_cntr; i++) {
>> etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
>> etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
>> etm_writel(drvdata, config->cntr_rld_event[i],
>> @@ -414,9 +415,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
>> etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
>> etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
>> etm_writel(drvdata, config->seq_curr_state, ETMSQR);
>> - for (i = 0; i < drvdata->nr_ext_out; i++)
>> + for (i = 0; i < caps->nr_ext_out; i++)
>> etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
>> - for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
>> + for (i = 0; i < caps->nr_ctxid_cmp; i++)
>> etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
>> etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
>> etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
>> @@ -572,7 +573,7 @@ static void etm_disable_hw(struct etm_drvdata
>> *drvdata)
>> /* Read back sequencer and counters for post trace analysis */
>> config->seq_curr_state = (etm_readl(drvdata, ETMSQR) &
>> ETM_SQR_MASK);
>> - for (i = 0; i < drvdata->nr_cntr; i++)
>> + for (i = 0; i < caps->nr_cntr; i++)
>
> caps undeclared.
>
> Thanks,
> Jie
Have comments below in previous message... ignore the mistake to end the
message...
>
>> config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
>> etm_set_pwrdwn(drvdata);
>> @@ -754,7 +755,9 @@ static void etm_init_arch_data(void *info)
>> {
>> u32 etmidr;
>> u32 etmccr;
>> + u32 etmccer;
>> struct etm_drvdata *drvdata = info;
>> + struct etm_caps *caps = &drvdata->caps;
>> /* Make sure all registers are accessible */
>> etm_os_unlock(drvdata);
>> @@ -779,16 +782,18 @@ static void etm_init_arch_data(void *info)
>> /* Find all capabilities */
>> etmidr = etm_readl(drvdata, ETMIDR);
>> drvdata->arch = BMVAL(etmidr, 4, 11);
>> - drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
>> + caps->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
>> +
>> + etmccer = etm_readl(drvdata, ETMCCER);
>> + caps->timestamp = !!(drvdata->etmccer & ETMCCER_TIMESTAMP);
>
> caps->timestamp = !!(etmccer & ETMCCER_TIMESTAMP);
>
>> - drvdata->etmccer = etm_readl(drvdata, ETMCCER);
>> etmccr = etm_readl(drvdata, ETMCCR);
>> - drvdata->etmccr = etmccr;
>> - drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
>> - drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
>> - drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
>> - drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
>> - drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
>> + caps->fifofull = !!(drvdata->etmccr & ETMCCR_FIFOFULL);
>
> caps->fifofull = !!(etmccr & ETMCCR_FIFOFULL);
>
>> + caps->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
>> + caps->nr_cntr = BMVAL(etmccr, 13, 15);
>> + caps->nr_ext_inp = BMVAL(etmccr, 17, 19);
>> + caps->nr_ext_out = BMVAL(etmccr, 20, 22);
>> + caps->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
>> coresight_clear_self_claim_tag_unlocked(&drvdata->csa);
>> etm_set_pwrdwn(drvdata);
>> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/
>> drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
>> index 762109307b86..0d8dac29d055 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
>> @@ -111,6 +111,7 @@ static ssize_t mode_store(struct device *dev,
>> int ret;
>> unsigned long val;
>> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + const struct etm_caps *caps = &drvdata->caps;
>> struct etm_config *config = &drvdata->config;
>> ret = kstrtoul(buf, 16, &val);
>> @@ -131,7 +132,7 @@ static ssize_t mode_store(struct device *dev,
>> config->ctrl &= ~ETMCR_CYC_ACC;
>> if (config->mode & ETM_MODE_STALL) {
>> - if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
>> + if (!caps->fifofull) {
>> dev_warn(dev, "stall mode not supported\n");
>> ret = -EINVAL;
>> goto err_unlock;
>> @@ -141,7 +142,7 @@ static ssize_t mode_store(struct device *dev,
>> config->ctrl &= ~ETMCR_STALL_MODE;
>> if (config->mode & ETM_MODE_TIMESTAMP) {
>> - if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
>> + if (!caps->timestamp) {
>> dev_warn(dev, "timestamp not supported\n");
>> ret = -EINVAL;
>> goto err_unlock;
>> @@ -286,13 +287,14 @@ static ssize_t addr_idx_store(struct device *dev,
>> int ret;
>> unsigned long val;
>> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + const struct etm_caps *caps = &drvdata->caps;
>> struct etm_config *config = &drvdata->config;
>> ret = kstrtoul(buf, 16, &val);
>> if (ret)
>> return ret;
>> - if (val >= drvdata->nr_addr_cmp)
>> + if (val >= caps->nr_addr_cmp)
>> return -EINVAL;
>> /*
>> @@ -589,13 +591,14 @@ static ssize_t cntr_idx_store(struct device *dev,
>> int ret;
>> unsigned long val;
>> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + const struct etm_caps *caps = &drvdata->caps;
>> struct etm_config *config = &drvdata->config;
>> ret = kstrtoul(buf, 16, &val);
>> if (ret)
>> return ret;
>> - if (val >= drvdata->nr_cntr)
>> + if (val >= caps->nr_cntr)
>> return -EINVAL;
>> /*
>> * Use spinlock to ensure index doesn't change while it gets
>> @@ -999,13 +1002,14 @@ static ssize_t ctxid_idx_store(struct device *dev,
>> int ret;
>> unsigned long val;
>> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> + const struct etm_caps *caps = &drvdata->caps;
>> struct etm_config *config = &drvdata->config;
>> ret = kstrtoul(buf, 16, &val);
>> if (ret)
>> return ret;
>> - if (val >= drvdata->nr_ctxid_cmp)
>> + if (val >= caps->nr_ctxid_cmp)
>> return -EINVAL;
>> /*
>
^ permalink raw reply
* Re: [PATCH v2 1/5] coresight: etm4x: introduce struct etm4_caps
From: Jie Gan @ 2026-04-12 14:35 UTC (permalink / raw)
To: Yeoreum Yun, coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan
In-Reply-To: <20260410074310.2693385-2-yeoreum.yun@arm.com>
On 4/10/2026 3:43 PM, Yeoreum Yun wrote:
> introduce struct etm4_caps to describe ETMv4 capabilities
> and move capabilities information into it.
>
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> ---
> .../coresight/coresight-etm4x-core.c | 234 +++++++++---------
> .../coresight/coresight-etm4x-sysfs.c | 185 ++++++++------
> drivers/hwtracing/coresight/coresight-etm4x.h | 175 ++++++-------
> 3 files changed, 327 insertions(+), 267 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index d565a73f0042..6443f3717b37 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -88,8 +88,9 @@ static int etm4_probe_cpu(unsigned int cpu);
> */
> static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
> {
> - return (n < drvdata->nr_ss_cmp) &&
> - drvdata->nr_pe &&
> + const struct etmv4_caps *caps = &drvdata->caps;
> +
> + return (n < caps->nr_ss_cmp) && caps->nr_pe &&
> (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
> }
>
> @@ -160,17 +161,20 @@ static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
> struct csdev_access *csa)
> {
> + struct etmv4_caps *caps = &drvdata->caps;
> u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
>
> - drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
> + caps->os_lock_model = ETM_OSLSR_OSLM(oslsr);
> }
>
> static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
> struct csdev_access *csa, u32 val)
> {
> + const struct etmv4_caps *caps = &drvdata->caps;
> +
> val = !!val;
>
> - switch (drvdata->os_lock_model) {
> + switch (caps->os_lock_model) {
> case ETM_OSLOCK_PRESENT:
> etm4x_relaxed_write32(csa, val, TRCOSLAR);
> break;
> @@ -179,7 +183,7 @@ static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
> break;
> default:
> pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
> - smp_processor_id(), drvdata->os_lock_model);
> + smp_processor_id(), caps->os_lock_model);
> fallthrough;
> case ETM_OSLOCK_NI:
> return;
> @@ -494,6 +498,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata)
> static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> {
> int i, rc;
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
> struct device *etm_dev = &csdev->dev;
> @@ -525,14 +530,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1))
> dev_err(etm_dev,
> "timeout while waiting for Idle Trace Status\n");
> - if (drvdata->nr_pe)
> + if (caps->nr_pe)
> etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
> etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
> /* nothing specific implemented */
> etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
> etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
> etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
> - if (drvdata->stallctl)
> + if (caps->stallctl)
> etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
> etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
> etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
> @@ -542,17 +547,17 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
> etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
> etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
> - if (drvdata->nr_pe_cmp)
> + if (caps->nr_pe_cmp)
> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + for (i = 0; i < caps->nrseqstate - 1; i++)
> etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> - if (drvdata->nrseqstate) {
> + if (caps->nrseqstate) {
> etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> }
> - if (drvdata->numextinsel)
> + if (caps->numextinsel)
> etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
> - for (i = 0; i < drvdata->nr_cntr; i++) {
> + for (i = 0; i < caps->nr_cntr; i++) {
> etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
> etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
> etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
> @@ -562,10 +567,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> * Resource selector pair 0 is always implemented and reserved. As
> * such start at 2.
> */
> - for (i = 2; i < drvdata->nr_resource * 2; i++)
> + for (i = 2; i < caps->nr_resource * 2; i++)
> etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
>
> - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + for (i = 0; i < caps->nr_ss_cmp; i++) {
> /* always clear status bit on restart if using single-shot */
> if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> @@ -574,23 +579,23 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> if (etm4x_sspcicrn_present(drvdata, i))
> etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
> }
> - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> + for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
> etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
> etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
> }
> - for (i = 0; i < drvdata->numcidc; i++)
> + for (i = 0; i < caps->numcidc; i++)
> etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
> etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
> - if (drvdata->numcidc > 4)
> + if (caps->numcidc > 4)
> etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
>
> - for (i = 0; i < drvdata->numvmidc; i++)
> + for (i = 0; i < caps->numvmidc; i++)
> etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
> etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
> - if (drvdata->numvmidc > 4)
> + if (caps->numvmidc > 4)
> etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
>
> - if (!drvdata->skip_power_up) {
> + if (!caps->skip_power_up) {
> u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
>
> /*
> @@ -666,19 +671,20 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
> {
> int ctridx;
> int rselector;
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_config *config = &drvdata->config;
>
> /* No point in trying if we don't have at least one counter */
> - if (!drvdata->nr_cntr)
> + if (!caps->nr_cntr)
> return -EINVAL;
>
> /* Find a counter that hasn't been initialised */
> - for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
> + for (ctridx = 0; ctridx < caps->nr_cntr; ctridx++)
> if (config->cntr_val[ctridx] == 0)
> break;
>
> /* All the counters have been configured already, bail out */
> - if (ctridx == drvdata->nr_cntr) {
> + if (ctridx == caps->nr_cntr) {
> pr_debug("%s: no available counter found\n", __func__);
> return -ENOSPC;
> }
> @@ -694,11 +700,11 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
> * ETMIDR4 gives the number of resource selector _pairs_, hence multiply
> * by 2.
> */
> - for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
> + for (rselector = 2; rselector < caps->nr_resource * 2; rselector++)
> if (!config->res_ctrl[rselector])
> break;
>
> - if (rselector == drvdata->nr_resource * 2) {
> + if (rselector == caps->nr_resource * 2) {
> pr_debug("%s: no available resource selector found\n",
> __func__);
> return -ENOSPC;
> @@ -749,6 +755,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> {
> int ret = 0;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_config *config = &drvdata->config;
> struct perf_event_attr max_timestamp = {
> .ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
> @@ -788,8 +795,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> cc_threshold = ATTR_CFG_GET_FLD(attr, cc_threshold);
> if (!cc_threshold)
> cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
> - if (cc_threshold < drvdata->ccitmin)
> - cc_threshold = drvdata->ccitmin;
> + if (cc_threshold < caps->ccitmin)
> + cc_threshold = caps->ccitmin;
> config->ccctlr = cc_threshold;
> }
>
> @@ -837,7 +844,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> }
>
> /* return stack - enable if selected and supported */
> - if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack)
> + if (ATTR_CFG_GET_FLD(attr, retstack) && caps->retstack)
> /* bit[12], Return stack enable bit */
> config->cfg |= TRCCONFIGR_RS;
>
> @@ -853,7 +860,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>
> /* branch broadcast - enable if selected and supported */
> if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
> - if (!drvdata->trcbb) {
> + if (!caps->trcbb) {
> /*
> * Missing BB support could cause silent decode errors
> * so fail to open if it's not supported.
> @@ -1028,6 +1035,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata)
> static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> {
> u32 control;
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
> struct csdev_access *csa = &csdev->access;
> @@ -1036,7 +1044,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> etm4_cs_unlock(drvdata, csa);
> etm4_disable_arch_specific(drvdata);
>
> - if (!drvdata->skip_power_up) {
> + if (!caps->skip_power_up) {
> /* power can be removed from the trace unit now */
> control = etm4x_relaxed_read32(csa, TRCPDCR);
> control &= ~TRCPDCR_PU;
> @@ -1046,13 +1054,13 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> etm4_disable_trace_unit(drvdata);
>
> /* read the status of the single shot comparators */
> - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + for (i = 0; i < caps->nr_ss_cmp; i++) {
> config->ss_status[i] =
> etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> }
>
> /* read back the current counter values */
> - for (i = 0; i < drvdata->nr_cntr; i++) {
> + for (i = 0; i < caps->nr_cntr; i++) {
> config->cntr_val[i] =
> etm4x_relaxed_read32(csa, TRCCNTVRn(i));
> }
> @@ -1350,7 +1358,7 @@ static struct midr_range etm_wrong_ccitmin_cpus[] = {
> {},
> };
>
> -static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
> +static void etm4_fixup_wrong_ccitmin(struct etmv4_caps *caps)
> {
> /*
> * Erratum affected cpus will read 256 as the minimum
> @@ -1360,8 +1368,8 @@ static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
> * this problem.
> */
> if (is_midr_in_range_list(etm_wrong_ccitmin_cpus)) {
> - if (drvdata->ccitmin == 256)
> - drvdata->ccitmin = 4;
> + if (caps->ccitmin == 256)
> + caps->ccitmin = 4;
> }
> }
>
> @@ -1374,11 +1382,13 @@ static void etm4_init_arch_data(void *info)
> u32 etmidr5;
> struct etm4_init_arg *init_arg = info;
> struct etmv4_drvdata *drvdata;
> + struct etmv4_caps *caps;
> struct csdev_access *csa;
> struct device *dev = init_arg->dev;
> int i;
>
> drvdata = dev_get_drvdata(init_arg->dev);
> + caps = &drvdata->caps;
> csa = init_arg->csa;
>
> /*
> @@ -1391,7 +1401,7 @@ static void etm4_init_arch_data(void *info)
>
> if (!csa->io_mem ||
> fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
> - drvdata->skip_power_up = true;
> + caps->skip_power_up = true;
>
> /* Detect the support for OS Lock before we actually use it */
> etm_detect_os_lock(drvdata, csa);
> @@ -1406,71 +1416,71 @@ static void etm4_init_arch_data(void *info)
> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
>
> /* INSTP0, bits[2:1] P0 tracing support field */
> - drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
> + caps->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
> /* TRCBB, bit[5] Branch broadcast tracing support bit */
> - drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
> + caps->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
> /* TRCCOND, bit[6] Conditional instruction tracing support bit */
> - drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
> + caps->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
> /* TRCCCI, bit[7] Cycle counting instruction bit */
> - drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
> + caps->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
> /* RETSTACK, bit[9] Return stack bit */
> - drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
> + caps->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
> /* NUMEVENT, bits[11:10] Number of events field */
> - drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
> + caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
> /* QSUPP, bits[16:15] Q element support field */
> - drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
> - if (drvdata->q_support)
> - drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
> + caps->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
> + if (caps->q_support)
> + caps->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
> /* TSSIZE, bits[28:24] Global timestamp size field */
> - drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
> + caps->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
>
> /* maximum size of resources */
> etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
> /* CIDSIZE, bits[9:5] Indicates the Context ID size */
> - drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
> + caps->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
> /* VMIDSIZE, bits[14:10] Indicates the VMID size */
> - drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
> + caps->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
> /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
> - drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
> + caps->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
>
> etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
> /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
> - drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
> - etm4_fixup_wrong_ccitmin(drvdata);
> + caps->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
> + etm4_fixup_wrong_ccitmin(caps);
>
> /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
> - drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
> - drvdata->config.s_ex_level = drvdata->s_ex_level;
> + caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
> + drvdata->config.s_ex_level = caps->s_ex_level;
> /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
> - drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
> + caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
> /*
> * TRCERR, bit[24] whether a trace unit can trace a
> * system error exception.
> */
> - drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
> + caps->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
> /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
> - drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
> + caps->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
> /* STALLCTL, bit[26] is stall control implemented? */
> - drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
> + caps->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
> /* SYSSTALL, bit[27] implementation can support stall control? */
> - drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
> + caps->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
> /*
> * NUMPROC - the number of PEs available for tracing, 5bits
> * = TRCIDR3.bits[13:12]bits[30:28]
> * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
> * bits[3:0] = TRCIDR3.bits[30:28]
> */
> - drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
> - FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
> + caps->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
> + FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
> /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
> - drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
> + caps->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
>
> /* number of resources trace unit supports */
> etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
> /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
> - drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
> + caps->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
> /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
> - drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
> + caps->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
> /*
> * NUMRSPAIR, bits[19:16]
> * The number of resource pairs conveyed by the HW starts at 0, i.e a
> @@ -1481,41 +1491,41 @@ static void etm4_init_arch_data(void *info)
> * the default TRUE and FALSE resource selectors are omitted.
> * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
> */
> - drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
> - if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
> - drvdata->nr_resource += 1;
> + caps->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
> + if ((drvdata->arch < ETM_ARCH_V4_3) || (caps->nr_resource > 0))
> + caps->nr_resource += 1;
> /*
> * NUMSSCC, bits[23:20] the number of single-shot
> * comparator control for tracing. Read any status regs as these
> * also contain RO capability data.
> */
> - drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> + for (i = 0; i < caps->nr_ss_cmp; i++) {
> drvdata->config.ss_status[i] =
> etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> }
> /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> - drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
> + caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
> /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> - drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
> + caps->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
>
> etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
> /* NUMEXTIN, bits[8:0] number of external inputs implemented */
> - drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
> - drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
> + caps->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
> + caps->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
> /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
> - drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
> + caps->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
> /* ATBTRIG, bit[22] implementation can support ATB triggers? */
> - drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
> + caps->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
> /*
> * LPOVERRIDE, bit[23] implementation supports
> * low-power state override
> */
> - drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
> + caps->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!caps->skip_power_up);
> /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
> - drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
> + caps->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
> /* NUMCNTR, bits[30:28] number of counters available for tracing */
> - drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
> + caps->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
>
> coresight_clear_self_claim_tag_unlocked(csa);
> etm4_cs_lock(drvdata, csa);
> @@ -1691,7 +1701,7 @@ static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
> * nr_addr_cmp holds the number of comparator _pair_, so time 2
> * for the total number of comparators.
> */
> - nr_comparator = drvdata->nr_addr_cmp * 2;
> + nr_comparator = drvdata->caps.nr_addr_cmp * 2;
>
> /* Go through the tally of comparators looking for a free one. */
> while (index < nr_comparator) {
> @@ -1869,6 +1879,7 @@ static int etm4_dying_cpu(unsigned int cpu)
> static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
> {
> int i, ret = 0;
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_save_state *state;
> struct coresight_device *csdev = drvdata->csdev;
> struct csdev_access *csa;
> @@ -1905,57 +1916,57 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
>
> state = drvdata->save_state;
>
> - if (drvdata->nr_pe)
> + if (caps->nr_pe)
> state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
> state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
> state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
> state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
> state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
> - if (drvdata->stallctl)
> + if (caps->stallctl)
> state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
> state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
> state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
> state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
> state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
> state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
> - if (drvdata->q_filt)
> + if (caps->q_filt)
> state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
>
> state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
> state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
> state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
> - if (drvdata->nr_pe_cmp)
> + if (caps->nr_pe_cmp)
> state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
>
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + for (i = 0; i < caps->nrseqstate - 1; i++)
> state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
>
> - if (drvdata->nrseqstate) {
> + if (caps->nrseqstate) {
> state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> }
>
> - if (drvdata->numextinsel)
> + if (caps->numextinsel)
> state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
>
> - for (i = 0; i < drvdata->nr_cntr; i++) {
> + for (i = 0; i < caps->nr_cntr; i++) {
> state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
> state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
> state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
> }
>
> /* Resource selector pair 0 is reserved */
> - for (i = 2; i < drvdata->nr_resource * 2; i++)
> + for (i = 2; i < caps->nr_resource * 2; i++)
> state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
>
> - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + for (i = 0; i < caps->nr_ss_cmp; i++) {
> state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
> state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
> if (etm4x_sspcicrn_present(drvdata, i))
> state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
> }
>
> - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> + for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
> state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
> state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
> }
> @@ -1967,23 +1978,23 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
> * unit") of ARM IHI 0064D.
> */
>
> - for (i = 0; i < drvdata->numcidc; i++)
> + for (i = 0; i < caps->numcidc; i++)
> state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
>
> - for (i = 0; i < drvdata->numvmidc; i++)
> + for (i = 0; i < caps->numvmidc; i++)
> state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
>
> state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
> - if (drvdata->numcidc > 4)
> + if (caps->numcidc > 4)
> state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
>
> state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
> - if (drvdata->numvmidc > 4)
> + if (caps->numvmidc > 4)
> state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
>
> state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
>
> - if (!drvdata->skip_power_up)
> + if (!caps->skip_power_up)
> state->trcpdcr = etm4x_read32(csa, TRCPDCR);
>
> /* wait for TRCSTATR.IDLE to go up */
> @@ -2000,7 +2011,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
> * potentially save power on systems that respect the TRCPDCR_PU
> * despite requesting software to save/restore state.
> */
> - if (!drvdata->skip_power_up)
> + if (!caps->skip_power_up)
> etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
> TRCPDCR);
> out:
> @@ -2027,6 +2038,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> {
> int i;
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_save_state *state = drvdata->save_state;
> struct csdev_access *csa = &drvdata->csdev->access;
>
> @@ -2036,77 +2048,77 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> etm4_cs_unlock(drvdata, csa);
> etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
>
> - if (drvdata->nr_pe)
> + if (caps->nr_pe)
> etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
> etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
> etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
> etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
> etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
> - if (drvdata->stallctl)
> + if (caps->stallctl)
> etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
> etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
> etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
> etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
> etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
> etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
> - if (drvdata->q_filt)
> + if (caps->q_filt)
> etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
>
> etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
> etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
> etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
> - if (drvdata->nr_pe_cmp)
> + if (caps->nr_pe_cmp)
> etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
>
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + for (i = 0; i < caps->nrseqstate - 1; i++)
> etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
>
> - if (drvdata->nrseqstate) {
> + if (caps->nrseqstate) {
> etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> }
> - if (drvdata->numextinsel)
> + if (caps->numextinsel)
> etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
>
> - for (i = 0; i < drvdata->nr_cntr; i++) {
> + for (i = 0; i < caps->nr_cntr; i++) {
> etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
> etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
> etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
> }
>
> /* Resource selector pair 0 is reserved */
> - for (i = 2; i < drvdata->nr_resource * 2; i++)
> + for (i = 2; i < caps->nr_resource * 2; i++)
> etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
>
> - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + for (i = 0; i < caps->nr_ss_cmp; i++) {
> etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
> etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
> if (etm4x_sspcicrn_present(drvdata, i))
> etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
> }
>
> - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> + for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
> etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
> etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
> }
>
> - for (i = 0; i < drvdata->numcidc; i++)
> + for (i = 0; i < caps->numcidc; i++)
> etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
>
> - for (i = 0; i < drvdata->numvmidc; i++)
> + for (i = 0; i < caps->numvmidc; i++)
> etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
>
> etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
> - if (drvdata->numcidc > 4)
> + if (caps->numcidc > 4)
> etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
>
> etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
> - if (drvdata->numvmidc > 4)
> + if (caps->numvmidc > 4)
> etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
>
> etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
>
> - if (!drvdata->skip_power_up)
> + if (!caps->skip_power_up)
> etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
>
> /*
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index e9eeea6240d5..3d5f343130bd 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -62,8 +62,9 @@ static ssize_t nr_pe_cmp_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->nr_pe_cmp;
> + val = caps->nr_pe_cmp;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_pe_cmp);
> @@ -74,8 +75,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->nr_addr_cmp;
> + val = caps->nr_addr_cmp;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_addr_cmp);
> @@ -86,8 +88,9 @@ static ssize_t nr_cntr_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->nr_cntr;
> + val = caps->nr_cntr;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_cntr);
> @@ -98,8 +101,9 @@ static ssize_t nr_ext_inp_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->nr_ext_inp;
> + val = caps->nr_ext_inp;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_ext_inp);
> @@ -110,8 +114,9 @@ static ssize_t numcidc_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->numcidc;
> + val = caps->numcidc;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(numcidc);
> @@ -122,8 +127,9 @@ static ssize_t numvmidc_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->numvmidc;
> + val = caps->numvmidc;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(numvmidc);
> @@ -134,8 +140,9 @@ static ssize_t nrseqstate_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->nrseqstate;
> + val = caps->nrseqstate;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nrseqstate);
> @@ -146,8 +153,9 @@ static ssize_t nr_resource_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->nr_resource;
> + val = caps->nr_resource;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_resource);
> @@ -158,8 +166,9 @@ static ssize_t nr_ss_cmp_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
>
> - val = drvdata->nr_ss_cmp;
> + val = caps->nr_ss_cmp;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_ss_cmp);
> @@ -171,6 +180,7 @@ static ssize_t reset_store(struct device *dev,
> int i;
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_config *config = &drvdata->config;
>
> if (kstrtoul(buf, 16, &val))
> @@ -200,7 +210,7 @@ static ssize_t reset_store(struct device *dev,
> config->stall_ctrl = 0x0;
>
> /* Reset trace synchronization period to 2^8 = 256 bytes*/
> - if (drvdata->syncpr == false)
> + if (caps->syncpr == false)
> config->syncfreq = 0x8;
>
> /*
> @@ -209,7 +219,7 @@ static ssize_t reset_store(struct device *dev,
> * each trace run.
> */
> config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
> - if (drvdata->nr_addr_cmp > 0) {
> + if (caps->nr_addr_cmp > 0) {
> config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
> /* SSSTATUS, bit[9] */
> config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
> @@ -223,7 +233,7 @@ static ssize_t reset_store(struct device *dev,
> config->vipcssctlr = 0x0;
>
> /* Disable seq events */
> - for (i = 0; i < drvdata->nrseqstate-1; i++)
> + for (i = 0; i < caps->nrseqstate-1; i++)
from checkpatch:
CHECK: spaces preferred around '-'
coresight-etm4x-sysfs.c:236: caps->nrseqstate-1
> config->seq_ctrl[i] = 0x0;
> config->seq_rst = 0x0;
> config->seq_state = 0x0;
> @@ -232,38 +242,38 @@ static ssize_t reset_store(struct device *dev,
> config->ext_inp = 0x0;
>
> config->cntr_idx = 0x0;
> - for (i = 0; i < drvdata->nr_cntr; i++) {
> + for (i = 0; i < caps->nr_cntr; i++) {
> config->cntrldvr[i] = 0x0;
> config->cntr_ctrl[i] = 0x0;
> config->cntr_val[i] = 0x0;
> }
>
> config->res_idx = 0x0;
> - for (i = 2; i < 2 * drvdata->nr_resource; i++)
> + for (i = 2; i < 2 * caps->nr_resource; i++)
> config->res_ctrl[i] = 0x0;
>
> config->ss_idx = 0x0;
> - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + for (i = 0; i < caps->nr_ss_cmp; i++) {
> config->ss_ctrl[i] = 0x0;
> config->ss_pe_cmp[i] = 0x0;
> }
>
> config->addr_idx = 0x0;
> - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> + for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
> config->addr_val[i] = 0x0;
> config->addr_acc[i] = 0x0;
> config->addr_type[i] = ETM_ADDR_TYPE_NONE;
> }
>
> config->ctxid_idx = 0x0;
> - for (i = 0; i < drvdata->numcidc; i++)
> + for (i = 0; i < caps->numcidc; i++)
> config->ctxid_pid[i] = 0x0;
>
> config->ctxid_mask0 = 0x0;
> config->ctxid_mask1 = 0x0;
>
> config->vmid_idx = 0x0;
> - for (i = 0; i < drvdata->numvmidc; i++)
> + for (i = 0; i < caps->numvmidc; i++)
> config->vmid_val[i] = 0x0;
> config->vmid_mask0 = 0x0;
> config->vmid_mask1 = 0x0;
> @@ -297,6 +307,7 @@ static ssize_t mode_store(struct device *dev,
> {
> unsigned long val, mode;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_config *config = &drvdata->config;
>
> if (kstrtoul(buf, 16, &val))
> @@ -305,7 +316,7 @@ static ssize_t mode_store(struct device *dev,
> raw_spin_lock(&drvdata->spinlock);
> config->mode = val & ETMv4_MODE_ALL;
>
> - if (drvdata->instrp0 == true) {
> + if (caps->instrp0 == true) {
find so many foo == true && foo == false formats from legacy codes.
I think it's worth to change all to if (foo) && if (!foo) ?
example here,
if (caps->instrp0)
> /* start by clearing instruction P0 field */
> config->cfg &= ~TRCCONFIGR_INSTP0_LOAD_STORE;
> if (config->mode & ETM_MODE_LOAD)
> @@ -323,45 +334,45 @@ static ssize_t mode_store(struct device *dev,
> }
>
> /* bit[3], Branch broadcast mode */
> - if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
> + if ((config->mode & ETM_MODE_BB) && (caps->trcbb == true))
> config->cfg |= TRCCONFIGR_BB;
<...>
> @@ -1037,46 +1081,11 @@ struct etmv4_drvdata {
> raw_spinlock_t spinlock;
> int cpu;
> u8 arch;
> - u8 nr_pe;
> - u8 nr_pe_cmp;
> - u8 nr_addr_cmp;
> - u8 nr_cntr;
> - u8 nr_ext_inp;
> - u8 numcidc;
> - u8 numextinsel;
> - u8 numvmidc;
> - u8 nrseqstate;
> - u8 nr_event;
> - u8 nr_resource;
> - u8 nr_ss_cmp;
> + struct etmv4_caps caps;
reported by checkpatch:
WARNING: please, no space before tabs
Thanks,
Jie
> u8 trcid;
> - u8 trcid_size;
> - u8 ts_size;
> - u8 ctxid_size;
> - u8 vmid_size;
> - u8 ccsize;
> - u16 ccitmin;
> - u8 s_ex_level;
> - u8 ns_ex_level;
> - u8 q_support;
> - u8 os_lock_model;
> bool sticky_enable : 1;
> bool boot_enable : 1;
> bool os_unlock : 1;
> - bool instrp0 : 1;
> - bool q_filt : 1;
> - bool trcbb : 1;
> - bool trccond : 1;
> - bool retstack : 1;
> - bool trccci : 1;
> - bool trc_error : 1;
> - bool syncpr : 1;
> - bool stallctl : 1;
> - bool sysstall : 1;
> - bool nooverflow : 1;
> - bool atbtrig : 1;
> - bool lpoverride : 1;
> - bool skip_power_up : 1;
> bool paused : 1;
> u64 trfcr;
> struct etmv4_config config;
^ permalink raw reply
* Re: [PATCH v2 2/5] coresight: etm4x: exclude ss_status from drvdata->config
From: Jie Gan @ 2026-04-12 14:40 UTC (permalink / raw)
To: Yeoreum Yun, coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan
In-Reply-To: <20260410074310.2693385-3-yeoreum.yun@arm.com>
On 4/10/2026 3:43 PM, Yeoreum Yun wrote:
> The purpose of TRCSSCSRn register is to show status of
> the corresponding Single-shot Comparator Control and input supports.
> That means writable field's purpose for reset or restore from idle status
> not for configuration.
>
> Therefore, exclude ss_status from drvdata->config, move it to etm4x_caps.
> This includes remove TRCSSCRn from configurable item and
> remove saving in etm4_disable_hw().
>
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> ---
> .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 -
> .../hwtracing/coresight/coresight-etm4x-core.c | 18 +++++-------------
> .../coresight/coresight-etm4x-sysfs.c | 7 ++-----
> drivers/hwtracing/coresight/coresight-etm4x.h | 3 ++-
> 4 files changed, 9 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> index c302072b293a..d14d7c8a23e5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> off_mask = (offset & GENMASK(11, 5));
> do {
> CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
> - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask);
> CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);
> } while (0);
> } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) {
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 6443f3717b37..b7abb171f523 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -91,7 +91,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
> const struct etmv4_caps *caps = &drvdata->caps;
>
> return (n < caps->nr_ss_cmp) && caps->nr_pe &&
> - (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
> + (caps->ss_status[n] & TRCSSCSRn_PC);
> }
>
> u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> @@ -571,11 +571,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
>
> for (i = 0; i < caps->nr_ss_cmp; i++) {
> - /* always clear status bit on restart if using single-shot */
> - if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> - config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
> - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
> + /* always clear status bit on restart if using single-shot */
the clear step for the status bit has been removed. but the comment
still here.
I think we cannot remove the clear step. The hardware requires the
STATUS bit to be cleared before re-arming a single-shot comparator;
failing to do so means the comparator will not fire on the next trace
session
Thanks,
Jie
> + etm4x_relaxed_write32(csa, caps->ss_status[i], TRCSSCSRn(i));
> if (etm4x_sspcicrn_present(drvdata, i))
> etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
> }
> @@ -1053,12 +1051,6 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
>
> etm4_disable_trace_unit(drvdata);
>
> - /* read the status of the single shot comparators */
> - for (i = 0; i < caps->nr_ss_cmp; i++) {
> - config->ss_status[i] =
> - etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> - }
> -
> /* read back the current counter values */
> for (i = 0; i < caps->nr_cntr; i++) {
> config->cntr_val[i] =
> @@ -1501,8 +1493,8 @@ static void etm4_init_arch_data(void *info)
> */
> caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> for (i = 0; i < caps->nr_ss_cmp; i++) {
> - drvdata->config.ss_status[i] =
> - etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> + caps->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> + caps->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> }
> /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 3d5f343130bd..c794fc9de5b6 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1832,8 +1832,6 @@ static ssize_t sshot_ctrl_store(struct device *dev,
> raw_spin_lock(&drvdata->spinlock);
> idx = config->ss_idx;
> config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
> - /* must clear bit 31 in related status register on programming */
> - config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
> raw_spin_unlock(&drvdata->spinlock);
> return size;
> }
> @@ -1844,10 +1842,11 @@ static ssize_t sshot_status_show(struct device *dev,
> {
> unsigned long val;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etmv4_caps *caps = &drvdata->caps;
> struct etmv4_config *config = &drvdata->config;
>
> raw_spin_lock(&drvdata->spinlock);
> - val = config->ss_status[config->ss_idx];
> + val = caps->ss_status[config->ss_idx];
> raw_spin_unlock(&drvdata->spinlock);
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> @@ -1882,8 +1881,6 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
> raw_spin_lock(&drvdata->spinlock);
> idx = config->ss_idx;
> config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
> - /* must clear bit 31 in related status register on programming */
> - config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
> raw_spin_unlock(&drvdata->spinlock);
> return size;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 3e20561672dc..57508d301327 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -213,6 +213,7 @@
> #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
>
> #define TRCSSCSRn_STATUS BIT(31)
> +#define TRCSSCSRn_PENDING BIT(30)
> #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
>
> #define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
> @@ -898,6 +899,7 @@ struct etmv4_caps {
> bool atbtrig : 1;
> bool lpoverride : 1;
> bool skip_power_up : 1;
> + u32 ss_status[ETM_MAX_SS_CMP];
> };
>
> /**
> @@ -976,7 +978,6 @@ struct etmv4_config {
> u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */
> u8 ss_idx;
> u32 ss_ctrl[ETM_MAX_SS_CMP];
> - u32 ss_status[ETM_MAX_SS_CMP];
> u32 ss_pe_cmp[ETM_MAX_SS_CMP];
> u8 addr_idx;
> u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
^ permalink raw reply
* Re: [RFC net-next v5 0/3] Add RSS and LRO support
From: Jakub Kicinski @ 2026-04-12 14:54 UTC (permalink / raw)
To: Frank Wunderlich
Cc: linux, nbd, sean.wang, lorenzo, andrew+netdev, davem, edumazet,
pabeni, matthias.bgg, angelogioacchino.delregno, linux, daniel,
netdev, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <trinity-1304ecb5-9a3f-4e37-b2c6-bcd7f35c2921-1775995067670@trinity-msg-rest-gmx-gmx-live-579dcf886d-nkpds>
On Sun, 12 Apr 2026 11:57:47 +0000 Frank Wunderlich wrote:
> some time has passed without a single comment, so i just send a friendly reminder ;)
You have a lot of people in the To:
Could you clarify who you expect to action these patches?
Patches are an RFC and I suppose ain't nobody got much comments?
^ permalink raw reply
* Re: [PATCH v2 4/5] coresight: etm3x: introduce struct etm_caps
From: Yeoreum Yun @ 2026-04-12 15:43 UTC (permalink / raw)
To: Jie Gan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, leo.yan
In-Reply-To: <4feaf157-4015-471e-accf-d588e2345c13@oss.qualcomm.com>
Hi Jie,
>
>
> On 4/10/2026 3:43 PM, Yeoreum Yun wrote:
> > Introduce struct etm_caps to describe ETMv3 capabilities
> > and move capabilities information into it.
> >
> > Since drvdata->etmccr and drvdata->etmccer are used to check
> > whether it supports fifofull logic and timestamping,
> > remove etmccr and etmccer field from drvdata and add relevant fields
> > in etm_caps structure.
> >
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > ---
> > drivers/hwtracing/coresight/coresight-etm.h | 40 +++++++++++--------
> > .../coresight/coresight-etm3x-core.c | 33 ++++++++-------
> > .../coresight/coresight-etm3x-sysfs.c | 14 ++++---
> > 3 files changed, 52 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
> > index 1d753cca2943..6fda26039db8 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm.h
> > @@ -140,6 +140,28 @@
> > ETM_ADD_COMP_0 | \
> > ETM_EVENT_NOT_A)
> > +/**
> > + * struct etmv4_caps - specifics ETM capabilities
> > + * @port_size: port size as reported by ETMCR bit 4-6 and 21.
> > + * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
> > + * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
> > + * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
> > + * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
> > + * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
> > + * @fifofull: FIFOFULL logic is present.
> > + * @timestamp: Timestamping is implemented.
> > + */
> > +struct etm_caps {
> > + int port_size;
> > + u8 nr_addr_cmp;
> > + u8 nr_cntr;
> > + u8 nr_ext_inp;
> > + u8 nr_ext_out;
> > + u8 nr_ctxid_cmp;
> > + bool fifofull : 1;
> > + bool timestamp : 1;
> > +};
> > +
> > /**
> > * struct etm_config - configuration information related to an ETM
> > * @mode: controls various modes supported by this ETM/PTM.
> > @@ -212,19 +234,12 @@ struct etm_config {
> > * @csdev: component vitals needed by the framework.
> > * @spinlock: only one at a time pls.
> > * @cpu: the cpu this component is affined to.
> > - * @port_size: port size as reported by ETMCR bit 4-6 and 21.
> > * @arch: ETM/PTM version number.
> > + * @caps: ETM capabilities.
> > * @use_cpu14: true if management registers need to be accessed via CP14.
> > * @sticky_enable: true if ETM base configuration has been done.
> > * @boot_enable:true if we should start tracing at boot time.
> > * @os_unlock: true if access to management registers is allowed.
> > - * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
> > - * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
> > - * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
> > - * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
> > - * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
> > - * @etmccr: value of register ETMCCR.
> > - * @etmccer: value of register ETMCCER.
> > * @traceid: value of the current ID for this component.
> > * @config: structure holding configuration parameters.
> > */
> > @@ -234,19 +249,12 @@ struct etm_drvdata {
> > struct coresight_device *csdev;
> > spinlock_t spinlock;
> > int cpu;
> > - int port_size;
> > u8 arch;
> > + struct etm_caps caps;
> > bool use_cp14;
> > bool sticky_enable;
> > bool boot_enable;
> > bool os_unlock;
> > - u8 nr_addr_cmp;
> > - u8 nr_cntr;
> > - u8 nr_ext_inp;
> > - u8 nr_ext_out;
> > - u8 nr_ctxid_cmp;
> > - u32 etmccr;
> > - u32 etmccer;
> > u32 traceid;
> > struct etm_config config;
> > };
> > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> > index a547a6d2e0bd..b7e977defb1c 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> > @@ -367,6 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> > {
> > int i, rc;
> > u32 etmcr;
> > + const struct etm_caps *caps = &drvdata->caps;
> > struct etm_config *config = &drvdata->config;
> > struct coresight_device *csdev = drvdata->csdev;
> > @@ -388,7 +389,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> > etmcr = etm_readl(drvdata, ETMCR);
> > /* Clear setting from a previous run if need be */
> > etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
> > - etmcr |= drvdata->port_size;
> > + etmcr |= caps->port_size;
> > etmcr |= ETMCR_ETM_EN;
> > etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
> > etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
> > @@ -396,11 +397,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> > etm_writel(drvdata, config->enable_event, ETMTEEVR);
> > etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
> > etm_writel(drvdata, config->fifofull_level, ETMFFLR);
> > - for (i = 0; i < drvdata->nr_addr_cmp; i++) {
> > + for (i = 0; i < caps->nr_addr_cmp; i++) {
> > etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
> > etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
> > }
> > - for (i = 0; i < drvdata->nr_cntr; i++) {
> > + for (i = 0; i < caps->nr_cntr; i++) {
> > etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
> > etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
> > etm_writel(drvdata, config->cntr_rld_event[i],
> > @@ -414,9 +415,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> > etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
> > etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
> > etm_writel(drvdata, config->seq_curr_state, ETMSQR);
> > - for (i = 0; i < drvdata->nr_ext_out; i++)
> > + for (i = 0; i < caps->nr_ext_out; i++)
> > etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
> > - for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
> > + for (i = 0; i < caps->nr_ctxid_cmp; i++)
> > etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
> > etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
> > etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
> > @@ -572,7 +573,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata)
> > /* Read back sequencer and counters for post trace analysis */
> > config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
> > - for (i = 0; i < drvdata->nr_cntr; i++)
> > + for (i = 0; i < caps->nr_cntr; i++)
>
> caps undeclared.
>
> Thanks,
> Jie
Sorry to mistake. I'll change.
>
> > config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
> > etm_set_pwrdwn(drvdata);
> > @@ -754,7 +755,9 @@ static void etm_init_arch_data(void *info)
> > {
> > u32 etmidr;
> > u32 etmccr;
> > + u32 etmccer;
> > struct etm_drvdata *drvdata = info;
> > + struct etm_caps *caps = &drvdata->caps;
> > /* Make sure all registers are accessible */
> > etm_os_unlock(drvdata);
> > @@ -779,16 +782,18 @@ static void etm_init_arch_data(void *info)
> > /* Find all capabilities */
> > etmidr = etm_readl(drvdata, ETMIDR);
> > drvdata->arch = BMVAL(etmidr, 4, 11);
> > - drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
> > + caps->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
> > +
> > + etmccer = etm_readl(drvdata, ETMCCER);
> > + caps->timestamp = !!(drvdata->etmccer & ETMCCER_TIMESTAMP);
>
> caps->timestamp = !!(etmccer & ETMCCER_TIMESTAMP);
>
> > - drvdata->etmccer = etm_readl(drvdata, ETMCCER);
> > etmccr = etm_readl(drvdata, ETMCCR);
> > - drvdata->etmccr = etmccr;
> > - drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
> > - drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
> > - drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
> > - drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
> > - drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
> > + caps->fifofull = !!(drvdata->etmccr & ETMCCR_FIFOFULL);
>
> caps->fifofull = !!(etmccr & ETMCCR_FIFOFULL);
>
> > + caps->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
> > + caps->nr_cntr = BMVAL(etmccr, 13, 15);
> > + caps->nr_ext_inp = BMVAL(etmccr, 17, 19);
> > + caps->nr_ext_out = BMVAL(etmccr, 20, 22);
> > + caps->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
> > coresight_clear_self_claim_tag_unlocked(&drvdata->csa);
> > etm_set_pwrdwn(drvdata);
> > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> > index 762109307b86..0d8dac29d055 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> > @@ -111,6 +111,7 @@ static ssize_t mode_store(struct device *dev,
> > int ret;
> > unsigned long val;
> > struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etm_caps *caps = &drvdata->caps;
> > struct etm_config *config = &drvdata->config;
> > ret = kstrtoul(buf, 16, &val);
> > @@ -131,7 +132,7 @@ static ssize_t mode_store(struct device *dev,
> > config->ctrl &= ~ETMCR_CYC_ACC;
> > if (config->mode & ETM_MODE_STALL) {
> > - if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
> > + if (!caps->fifofull) {
> > dev_warn(dev, "stall mode not supported\n");
> > ret = -EINVAL;
> > goto err_unlock;
> > @@ -141,7 +142,7 @@ static ssize_t mode_store(struct device *dev,
> > config->ctrl &= ~ETMCR_STALL_MODE;
> > if (config->mode & ETM_MODE_TIMESTAMP) {
> > - if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
> > + if (!caps->timestamp) {
> > dev_warn(dev, "timestamp not supported\n");
> > ret = -EINVAL;
> > goto err_unlock;
> > @@ -286,13 +287,14 @@ static ssize_t addr_idx_store(struct device *dev,
> > int ret;
> > unsigned long val;
> > struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etm_caps *caps = &drvdata->caps;
> > struct etm_config *config = &drvdata->config;
> > ret = kstrtoul(buf, 16, &val);
> > if (ret)
> > return ret;
> > - if (val >= drvdata->nr_addr_cmp)
> > + if (val >= caps->nr_addr_cmp)
> > return -EINVAL;
> > /*
> > @@ -589,13 +591,14 @@ static ssize_t cntr_idx_store(struct device *dev,
> > int ret;
> > unsigned long val;
> > struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etm_caps *caps = &drvdata->caps;
> > struct etm_config *config = &drvdata->config;
> > ret = kstrtoul(buf, 16, &val);
> > if (ret)
> > return ret;
> > - if (val >= drvdata->nr_cntr)
> > + if (val >= caps->nr_cntr)
> > return -EINVAL;
> > /*
> > * Use spinlock to ensure index doesn't change while it gets
> > @@ -999,13 +1002,14 @@ static ssize_t ctxid_idx_store(struct device *dev,
> > int ret;
> > unsigned long val;
> > struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etm_caps *caps = &drvdata->caps;
> > struct etm_config *config = &drvdata->config;
> > ret = kstrtoul(buf, 16, &val);
> > if (ret)
> > return ret;
> > - if (val >= drvdata->nr_ctxid_cmp)
> > + if (val >= caps->nr_ctxid_cmp)
> > return -EINVAL;
> > /*
>
--
Sincerely,
Yeoreum Yun
^ permalink raw reply
* [GIT PULL] Kbuild and Kconfig changes for v7.1
From: Nicolas Schier @ 2026-04-12 15:46 UTC (permalink / raw)
To: Linus Torvalds
Cc: Alexander Coffin, Ard Biesheuvel, Arnd Bergmann, Bill Wendling,
David Howells, Dodji Seketeli, H. Peter Anvin, Helge Deller,
John Moon, Jonathan Corbet, Josh Poimboeuf, Justin Stitt,
Kees Cook, Masahiro Yamada, Nathan Chancellor, Nick Desaulniers,
Shuah Khan, Song Liu, Thomas Weißschuh, Yonghong Song,
kernel-team, linux-arm-kernel, linux-efi, linux-hexagon,
linux-kbuild, linux-kernel, linux-parisc, linux-s390,
linuxppc-dev, llvm, loongarch
[-- Attachment #1: Type: text/plain, Size: 9589 bytes --]
Hi Linus,
please pull these changes to Kbuild and Kconfig for v7.1. Please let me
know if anything is incorrect and not matching your standards.
All changes have been in -next, most for several cycles without reported
problems.
Thanks and kind regards,
Nicolas
---
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
ssh://git@gitolite.kernel.org/pub/scm/linux/kernel/git/kbuild/linux.git tags/kbuild-7.1-1
for you to fetch changes up to 404927758daac5ec4594071e033c1fa6ee9ca9b6:
kbuild: expand inlining hints with -fdiagnostics-show-inlining-chain (2026-04-07 21:48:44 +0200)
----------------------------------------------------------------
Kbuild/Kconfig updates for 7.1
Kbuild changes
==============
* tools/build: Reject unexpected values for LLVM=
* kbuild: uapi: remove usage of toolchain headers
* kbuild: Switch from '-fms-extensions' to '-fms-anonymous-structs'
when available (currently: clang >= 23.0.0)
* kbuild: Reduce the number of compiler-generated suffixes for clang
thin-lto build
* kbuild: reduce output spam ("GEN Makefile") when building out of tree
* check-uapi: improve portability for testing headers
* uapi: also test UAPI headers against C++ compilers
* kbuild: vdso_install: drop build ID architecture allow-list
* checksyscalls: only run when necessary
* Documentation: kbuild: Update the debug information notes in
reproducible-builds.rst
* kconfig: forbid multiple entries with the same symbol in a choice
* kbuild: expand inlining hints with -fdiagnostics-show-inlining-chain
Kconfig changes
===============
* kconfig: Error out on duplicated kconfig inclusion
Cc: Alexander Coffin <alex@cyberialabs.net>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Bill Wendling <morbo@google.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Dodji Seketeli <dodji@seketeli.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Helge Deller <deller@gmx.de>
Cc: John Moon <john@jmoon.dev>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Josh Poimboeuf <jpoimboe@kernel.org>
Cc: Justin Stitt <justinstitt@google.com>
Cc: Kees Cook <kees@kernel.org>
Cc: Masahiro Yamada <masahiroy@kernel.org>
Cc: Nathan Chancellor <nathan@kernel.org>
Cc: Nick Desaulniers <nick.desaulniers+lkml@gmail.com>
Cc: Shuah Khan <skhan@linuxfoundation.org>
Cc: Song Liu <song@kernel.org>
Cc: Thomas Weißschuh <linux@weissschuh.net>
Cc: Yonghong Song <yonghong.song@linux.dev>
Cc: kernel-team@fb.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-efi@vger.kernel.org
Cc: linux-hexagon@vger.kernel.org
Cc: linux-kbuild@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-parisc@vger.kernel.org
Cc: linux-s390@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: llvm@lists.linux.dev
Cc: loongarch@lists.linux.dev
----------------------------------------------------------------
Arnd Bergmann (3):
check-uapi: link into shared objects
check-uapi: honor ${CROSS_COMPILE} setting
check-uapi: use dummy libc includes
Justin Stitt (1):
kbuild: expand inlining hints with -fdiagnostics-show-inlining-chain
Masahiro Yamada (1):
kconfig: forbid multiple entries with the same symbol in a choice
Nathan Chancellor (3):
kbuild: Consolidate C dialect options
kbuild: Use '-fms-anonymous-structs' if it is available
Documentation: kbuild: Update the debug information notes in reproducible-builds.rst
Nicolas Schier (1):
kconfig: Error out on duplicated kconfig inclusion
Thomas Weißschuh (25):
Documentation/llvm: drop note about LLVM=0
tools/build: Reject unexpected values for LLVM=
hexagon: uapi: Fix structure alignment attribute
kbuild: uapi: test linux/bpf_perf_event.h on powerpc
kbuild: uapi: deduplicate linux/bpf_perf_event.h exclusions
kbuild: uapi: completely exclude linux/bpf_perf_event.h on nios2
kbuild: uapi: only use dummy-include for headers which use libc
kbuild: uapi: provide stub includes for some libc headers
kbuild: uapi: use custom stub headers instead of libc ones
kbuild: uapi: simplify libc dependency logic
kbuild: uapi: remove now unneeded guard headers
kbuild: reduce output spam when building out of tree
kbuild: uapi: move some compiler arguments out of the command definition
kbuild: uapi: move all include path flags together
kbuild: uapi: handle UML in architecture-specific exclusion lists
kbuild: uapi: provide a C++ compatible dummy definition of NULL
kbuild: uapi: also test UAPI headers against C++ compilers
kbuild: vdso_install: split out the readelf invocation
kbuild: vdso_install: hide readelf warnings
kbuild: vdso_install: gracefully handle images without build ID
kbuild: vdso_install: drop build ID architecture allow-list
checksyscalls: move path to reference table to a variable
checksyscalls: fail on all intermediate errors
checksyscalls: only run when necessary
checksyscalls: move instance functionality into generic code
Yonghong Song (1):
kbuild: Reduce the number of compiler-generated suffixes for clang thin-lto build
Documentation/kbuild/llvm.rst | 4 --
Documentation/kbuild/reproducible-builds.rst | 7 ++-
Kbuild | 14 +++--
Makefile | 35 +++++++++---
arch/arm64/kernel/vdso32/Makefile | 3 +-
arch/hexagon/include/uapi/asm/sigcontext.h | 2 +-
arch/loongarch/vdso/Makefile | 2 +-
arch/mips/Makefile | 6 +-
arch/parisc/boot/compressed/Makefile | 2 +-
arch/powerpc/boot/Makefile | 3 +-
arch/s390/Makefile | 3 +-
arch/s390/purgatory/Makefile | 3 +-
arch/x86/Makefile | 6 +-
arch/x86/boot/compressed/Makefile | 6 +-
drivers/firmware/efi/libstub/Makefile | 3 +-
init/Kconfig | 5 ++
scripts/Makefile.vdsoinst | 7 ++-
scripts/Makefile.warn | 5 --
scripts/check-uapi.sh | 19 ++++---
scripts/checksyscalls.sh | 11 +++-
scripts/kconfig/lexer.l | 4 +-
scripts/kconfig/lkc.h | 3 +-
scripts/kconfig/parser.y | 15 ++---
scripts/kconfig/tests/err_repeated_inc/Kconfig | 3 +
.../kconfig/tests/err_repeated_inc/Kconfig.inc1 | 4 ++
.../kconfig/tests/err_repeated_inc/Kconfig.inc2 | 3 +
.../kconfig/tests/err_repeated_inc/Kconfig.inc3 | 1 +
scripts/kconfig/tests/err_repeated_inc/__init__.py | 10 ++++
.../kconfig/tests/err_repeated_inc/expected_stderr | 2 +
scripts/kconfig/util.c | 31 ++++++++++-
tools/scripts/Makefile.include | 2 +
usr/dummy-include/endian.h | 0
usr/dummy-include/limits.h | 8 +++
usr/dummy-include/netinet/if_ether.h | 0
usr/dummy-include/netinet/in.h | 0
usr/dummy-include/stdbool.h | 7 ---
usr/dummy-include/stddef.h | 13 +++++
usr/dummy-include/stdint.h | 17 ++++++
usr/dummy-include/stdlib.h | 7 ---
usr/dummy-include/string.h | 12 ++++
usr/dummy-include/sys/ioctl.h | 0
usr/dummy-include/sys/socket.h | 12 ++++
usr/dummy-include/sys/time.h | 3 +
usr/dummy-include/sys/types.h | 0
usr/dummy-include/time.h | 0
usr/dummy-include/unistd.h | 0
usr/include/Makefile | 65 ++++++++++++++--------
47 files changed, 251 insertions(+), 117 deletions(-)
create mode 100644 scripts/kconfig/tests/err_repeated_inc/Kconfig
create mode 100644 scripts/kconfig/tests/err_repeated_inc/Kconfig.inc1
create mode 100644 scripts/kconfig/tests/err_repeated_inc/Kconfig.inc2
create mode 100644 scripts/kconfig/tests/err_repeated_inc/Kconfig.inc3
create mode 100644 scripts/kconfig/tests/err_repeated_inc/__init__.py
create mode 100644 scripts/kconfig/tests/err_repeated_inc/expected_stderr
create mode 100644 usr/dummy-include/endian.h
create mode 100644 usr/dummy-include/limits.h
create mode 100644 usr/dummy-include/netinet/if_ether.h
create mode 100644 usr/dummy-include/netinet/in.h
delete mode 100644 usr/dummy-include/stdbool.h
create mode 100644 usr/dummy-include/stddef.h
create mode 100644 usr/dummy-include/stdint.h
delete mode 100644 usr/dummy-include/stdlib.h
create mode 100644 usr/dummy-include/string.h
create mode 100644 usr/dummy-include/sys/ioctl.h
create mode 100644 usr/dummy-include/sys/socket.h
create mode 100644 usr/dummy-include/sys/time.h
create mode 100644 usr/dummy-include/sys/types.h
create mode 100644 usr/dummy-include/time.h
create mode 100644 usr/dummy-include/unistd.h
--
Nicolas
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v2 2/5] coresight: etm4x: exclude ss_status from drvdata->config
From: Yeoreum Yun @ 2026-04-12 15:48 UTC (permalink / raw)
To: Jie Gan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, leo.yan
In-Reply-To: <a8d11f92-2af8-46e7-9098-18a835c6ec8a@oss.qualcomm.com>
Hi Jie,
>
>
> On 4/10/2026 3:43 PM, Yeoreum Yun wrote:
> > The purpose of TRCSSCSRn register is to show status of
> > the corresponding Single-shot Comparator Control and input supports.
> > That means writable field's purpose for reset or restore from idle status
> > not for configuration.
> >
> > Therefore, exclude ss_status from drvdata->config, move it to etm4x_caps.
> > This includes remove TRCSSCRn from configurable item and
> > remove saving in etm4_disable_hw().
> >
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > ---
> > .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 -
> > .../hwtracing/coresight/coresight-etm4x-core.c | 18 +++++-------------
> > .../coresight/coresight-etm4x-sysfs.c | 7 ++-----
> > drivers/hwtracing/coresight/coresight-etm4x.h | 3 ++-
> > 4 files changed, 9 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > index c302072b293a..d14d7c8a23e5 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > off_mask = (offset & GENMASK(11, 5));
> > do {
> > CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
> > - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask);
> > CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);
> > } while (0);
> > } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) {
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 6443f3717b37..b7abb171f523 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -91,7 +91,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
> > const struct etmv4_caps *caps = &drvdata->caps;
> > return (n < caps->nr_ss_cmp) && caps->nr_pe &&
> > - (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
> > + (caps->ss_status[n] & TRCSSCSRn_PC);
> > }
> > u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> > @@ -571,11 +571,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - /* always clear status bit on restart if using single-shot */
> > - if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > - config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
> > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
> > + /* always clear status bit on restart if using single-shot */
>
> the clear step for the status bit has been removed. but the comment still
> here.
>
> I think we cannot remove the clear step. The hardware requires the STATUS
> bit to be cleared before re-arming a single-shot comparator; failing to do
> so means the comparator will not fire on the next trace session
This one is intended. if you see the patch:
+ /* always clear status bit on restart if using single-shot */
+ etm4x_relaxed_write32(csa, caps->ss_status[i], TRCSSCSRn(i));
cap->ss_status[i] is initialised by etm4_init_arch_data() cleared
STATUS & PENDING bit. so the comment is still valid.
Thanks.
[...]
--
Sincerely,
Yeoreum Yun
^ permalink raw reply
* Re: [PATCH net-next v4 1/2] dt-bindings: net: ti: k3-am654-cpsw-nuss: Add ti,j722s-cpsw-nuss compatible
From: patchwork-bot+netdevbpf @ 2026-04-12 15:50 UTC (permalink / raw)
To: Nora Schiffer
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, nm, vigneshr,
kristo, s-vadapalli, rogerq, robh, krzk+dt, conor+dt, netdev,
devicetree, linux-kernel, linux-arm-kernel, linux
In-Reply-To: <191e9f7e3a6c14eabe891a98c5fb646766479c0a.1775558273.git.nora.schiffer@ew.tq-group.com>
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Tue, 7 Apr 2026 12:48:01 +0200 you wrote:
> The J722S CPSW3G is mostly identical to the AM64's, but additionally
> supports SGMII. The AM64 compatible ti,am642-cpsw-nuss is used as a
> fallback.
>
> Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
> ---
>
> [...]
Here is the summary with links:
- [net-next,v4,1/2] dt-bindings: net: ti: k3-am654-cpsw-nuss: Add ti,j722s-cpsw-nuss compatible
https://git.kernel.org/netdev/net-next/c/f757a2da6df5
- [net-next,v4,2/2] net: ethernet: ti: am65-cpsw: add support for J722S SoC family
https://git.kernel.org/netdev/net-next/c/436e9e48ca51
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH v2 1/5] coresight: etm4x: introduce struct etm4_caps
From: Yeoreum Yun @ 2026-04-12 15:51 UTC (permalink / raw)
To: Jie Gan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, leo.yan
In-Reply-To: <46776f5b-7167-4e99-ad8d-abb221f02aee@oss.qualcomm.com>
Hi Jie,
>
> On 4/10/2026 3:43 PM, Yeoreum Yun wrote:
> > introduce struct etm4_caps to describe ETMv4 capabilities
> > and move capabilities information into it.
> >
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > ---
> > .../coresight/coresight-etm4x-core.c | 234 +++++++++---------
> > .../coresight/coresight-etm4x-sysfs.c | 185 ++++++++------
> > drivers/hwtracing/coresight/coresight-etm4x.h | 175 ++++++-------
> > 3 files changed, 327 insertions(+), 267 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index d565a73f0042..6443f3717b37 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -88,8 +88,9 @@ static int etm4_probe_cpu(unsigned int cpu);
> > */
> > static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
> > {
> > - return (n < drvdata->nr_ss_cmp) &&
> > - drvdata->nr_pe &&
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > +
> > + return (n < caps->nr_ss_cmp) && caps->nr_pe &&
> > (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
> > }
> > @@ -160,17 +161,20 @@ static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> > static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
> > struct csdev_access *csa)
> > {
> > + struct etmv4_caps *caps = &drvdata->caps;
> > u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
> > - drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
> > + caps->os_lock_model = ETM_OSLSR_OSLM(oslsr);
> > }
> > static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
> > struct csdev_access *csa, u32 val)
> > {
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > +
> > val = !!val;
> > - switch (drvdata->os_lock_model) {
> > + switch (caps->os_lock_model) {
> > case ETM_OSLOCK_PRESENT:
> > etm4x_relaxed_write32(csa, val, TRCOSLAR);
> > break;
> > @@ -179,7 +183,7 @@ static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
> > break;
> > default:
> > pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
> > - smp_processor_id(), drvdata->os_lock_model);
> > + smp_processor_id(), caps->os_lock_model);
> > fallthrough;
> > case ETM_OSLOCK_NI:
> > return;
> > @@ -494,6 +498,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata)
> > static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > {
> > int i, rc;
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > struct etmv4_config *config = &drvdata->config;
> > struct coresight_device *csdev = drvdata->csdev;
> > struct device *etm_dev = &csdev->dev;
> > @@ -525,14 +530,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1))
> > dev_err(etm_dev,
> > "timeout while waiting for Idle Trace Status\n");
> > - if (drvdata->nr_pe)
> > + if (caps->nr_pe)
> > etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
> > etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
> > /* nothing specific implemented */
> > etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
> > etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
> > etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
> > - if (drvdata->stallctl)
> > + if (caps->stallctl)
> > etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
> > etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
> > etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
> > @@ -542,17 +547,17 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
> > etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
> > etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
> > - if (drvdata->nr_pe_cmp)
> > + if (caps->nr_pe_cmp)
> > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + for (i = 0; i < caps->nrseqstate - 1; i++)
> > etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> > - if (drvdata->nrseqstate) {
> > + if (caps->nrseqstate) {
> > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> > }
> > - if (drvdata->numextinsel)
> > + if (caps->numextinsel)
> > etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
> > - for (i = 0; i < drvdata->nr_cntr; i++) {
> > + for (i = 0; i < caps->nr_cntr; i++) {
> > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
> > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
> > etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
> > @@ -562,10 +567,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > * Resource selector pair 0 is always implemented and reserved. As
> > * such start at 2.
> > */
> > - for (i = 2; i < drvdata->nr_resource * 2; i++)
> > + for (i = 2; i < caps->nr_resource * 2; i++)
> > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
> > - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + for (i = 0; i < caps->nr_ss_cmp; i++) {
> > /* always clear status bit on restart if using single-shot */
> > if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> > @@ -574,23 +579,23 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > if (etm4x_sspcicrn_present(drvdata, i))
> > etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
> > }
> > - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> > + for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
> > etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
> > etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
> > }
> > - for (i = 0; i < drvdata->numcidc; i++)
> > + for (i = 0; i < caps->numcidc; i++)
> > etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
> > etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
> > - if (drvdata->numcidc > 4)
> > + if (caps->numcidc > 4)
> > etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
> > - for (i = 0; i < drvdata->numvmidc; i++)
> > + for (i = 0; i < caps->numvmidc; i++)
> > etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
> > etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
> > - if (drvdata->numvmidc > 4)
> > + if (caps->numvmidc > 4)
> > etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
> > - if (!drvdata->skip_power_up) {
> > + if (!caps->skip_power_up) {
> > u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
> > /*
> > @@ -666,19 +671,20 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
> > {
> > int ctridx;
> > int rselector;
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > struct etmv4_config *config = &drvdata->config;
> > /* No point in trying if we don't have at least one counter */
> > - if (!drvdata->nr_cntr)
> > + if (!caps->nr_cntr)
> > return -EINVAL;
> > /* Find a counter that hasn't been initialised */
> > - for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
> > + for (ctridx = 0; ctridx < caps->nr_cntr; ctridx++)
> > if (config->cntr_val[ctridx] == 0)
> > break;
> > /* All the counters have been configured already, bail out */
> > - if (ctridx == drvdata->nr_cntr) {
> > + if (ctridx == caps->nr_cntr) {
> > pr_debug("%s: no available counter found\n", __func__);
> > return -ENOSPC;
> > }
> > @@ -694,11 +700,11 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
> > * ETMIDR4 gives the number of resource selector _pairs_, hence multiply
> > * by 2.
> > */
> > - for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
> > + for (rselector = 2; rselector < caps->nr_resource * 2; rselector++)
> > if (!config->res_ctrl[rselector])
> > break;
> > - if (rselector == drvdata->nr_resource * 2) {
> > + if (rselector == caps->nr_resource * 2) {
> > pr_debug("%s: no available resource selector found\n",
> > __func__);
> > return -ENOSPC;
> > @@ -749,6 +755,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> > {
> > int ret = 0;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > struct etmv4_config *config = &drvdata->config;
> > struct perf_event_attr max_timestamp = {
> > .ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
> > @@ -788,8 +795,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> > cc_threshold = ATTR_CFG_GET_FLD(attr, cc_threshold);
> > if (!cc_threshold)
> > cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
> > - if (cc_threshold < drvdata->ccitmin)
> > - cc_threshold = drvdata->ccitmin;
> > + if (cc_threshold < caps->ccitmin)
> > + cc_threshold = caps->ccitmin;
> > config->ccctlr = cc_threshold;
> > }
> > @@ -837,7 +844,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> > }
> > /* return stack - enable if selected and supported */
> > - if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack)
> > + if (ATTR_CFG_GET_FLD(attr, retstack) && caps->retstack)
> > /* bit[12], Return stack enable bit */
> > config->cfg |= TRCCONFIGR_RS;
> > @@ -853,7 +860,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> > /* branch broadcast - enable if selected and supported */
> > if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
> > - if (!drvdata->trcbb) {
> > + if (!caps->trcbb) {
> > /*
> > * Missing BB support could cause silent decode errors
> > * so fail to open if it's not supported.
> > @@ -1028,6 +1035,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata)
> > static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> > {
> > u32 control;
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > struct etmv4_config *config = &drvdata->config;
> > struct coresight_device *csdev = drvdata->csdev;
> > struct csdev_access *csa = &csdev->access;
> > @@ -1036,7 +1044,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> > etm4_cs_unlock(drvdata, csa);
> > etm4_disable_arch_specific(drvdata);
> > - if (!drvdata->skip_power_up) {
> > + if (!caps->skip_power_up) {
> > /* power can be removed from the trace unit now */
> > control = etm4x_relaxed_read32(csa, TRCPDCR);
> > control &= ~TRCPDCR_PU;
> > @@ -1046,13 +1054,13 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> > etm4_disable_trace_unit(drvdata);
> > /* read the status of the single shot comparators */
> > - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + for (i = 0; i < caps->nr_ss_cmp; i++) {
> > config->ss_status[i] =
> > etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > }
> > /* read back the current counter values */
> > - for (i = 0; i < drvdata->nr_cntr; i++) {
> > + for (i = 0; i < caps->nr_cntr; i++) {
> > config->cntr_val[i] =
> > etm4x_relaxed_read32(csa, TRCCNTVRn(i));
> > }
> > @@ -1350,7 +1358,7 @@ static struct midr_range etm_wrong_ccitmin_cpus[] = {
> > {},
> > };
> > -static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
> > +static void etm4_fixup_wrong_ccitmin(struct etmv4_caps *caps)
> > {
> > /*
> > * Erratum affected cpus will read 256 as the minimum
> > @@ -1360,8 +1368,8 @@ static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
> > * this problem.
> > */
> > if (is_midr_in_range_list(etm_wrong_ccitmin_cpus)) {
> > - if (drvdata->ccitmin == 256)
> > - drvdata->ccitmin = 4;
> > + if (caps->ccitmin == 256)
> > + caps->ccitmin = 4;
> > }
> > }
> > @@ -1374,11 +1382,13 @@ static void etm4_init_arch_data(void *info)
> > u32 etmidr5;
> > struct etm4_init_arg *init_arg = info;
> > struct etmv4_drvdata *drvdata;
> > + struct etmv4_caps *caps;
> > struct csdev_access *csa;
> > struct device *dev = init_arg->dev;
> > int i;
> > drvdata = dev_get_drvdata(init_arg->dev);
> > + caps = &drvdata->caps;
> > csa = init_arg->csa;
> > /*
> > @@ -1391,7 +1401,7 @@ static void etm4_init_arch_data(void *info)
> > if (!csa->io_mem ||
> > fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
> > - drvdata->skip_power_up = true;
> > + caps->skip_power_up = true;
> > /* Detect the support for OS Lock before we actually use it */
> > etm_detect_os_lock(drvdata, csa);
> > @@ -1406,71 +1416,71 @@ static void etm4_init_arch_data(void *info)
> > etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
> > /* INSTP0, bits[2:1] P0 tracing support field */
> > - drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
> > + caps->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
> > /* TRCBB, bit[5] Branch broadcast tracing support bit */
> > - drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
> > + caps->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
> > /* TRCCOND, bit[6] Conditional instruction tracing support bit */
> > - drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
> > + caps->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
> > /* TRCCCI, bit[7] Cycle counting instruction bit */
> > - drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
> > + caps->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
> > /* RETSTACK, bit[9] Return stack bit */
> > - drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
> > + caps->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
> > /* NUMEVENT, bits[11:10] Number of events field */
> > - drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
> > + caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
> > /* QSUPP, bits[16:15] Q element support field */
> > - drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
> > - if (drvdata->q_support)
> > - drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
> > + caps->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
> > + if (caps->q_support)
> > + caps->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
> > /* TSSIZE, bits[28:24] Global timestamp size field */
> > - drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
> > + caps->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
> > /* maximum size of resources */
> > etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
> > /* CIDSIZE, bits[9:5] Indicates the Context ID size */
> > - drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
> > + caps->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
> > /* VMIDSIZE, bits[14:10] Indicates the VMID size */
> > - drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
> > + caps->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
> > /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
> > - drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
> > + caps->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
> > etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
> > /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
> > - drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
> > - etm4_fixup_wrong_ccitmin(drvdata);
> > + caps->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
> > + etm4_fixup_wrong_ccitmin(caps);
> > /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
> > - drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
> > - drvdata->config.s_ex_level = drvdata->s_ex_level;
> > + caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
> > + drvdata->config.s_ex_level = caps->s_ex_level;
> > /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
> > - drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
> > + caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
> > /*
> > * TRCERR, bit[24] whether a trace unit can trace a
> > * system error exception.
> > */
> > - drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
> > + caps->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
> > /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
> > - drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
> > + caps->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
> > /* STALLCTL, bit[26] is stall control implemented? */
> > - drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
> > + caps->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
> > /* SYSSTALL, bit[27] implementation can support stall control? */
> > - drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
> > + caps->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
> > /*
> > * NUMPROC - the number of PEs available for tracing, 5bits
> > * = TRCIDR3.bits[13:12]bits[30:28]
> > * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
> > * bits[3:0] = TRCIDR3.bits[30:28]
> > */
> > - drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
> > - FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
> > + caps->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
> > + FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
> > /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
> > - drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
> > + caps->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
> > /* number of resources trace unit supports */
> > etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
> > /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
> > - drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
> > + caps->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
> > /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
> > - drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
> > + caps->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
> > /*
> > * NUMRSPAIR, bits[19:16]
> > * The number of resource pairs conveyed by the HW starts at 0, i.e a
> > @@ -1481,41 +1491,41 @@ static void etm4_init_arch_data(void *info)
> > * the default TRUE and FALSE resource selectors are omitted.
> > * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
> > */
> > - drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
> > - if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
> > - drvdata->nr_resource += 1;
> > + caps->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
> > + if ((drvdata->arch < ETM_ARCH_V4_3) || (caps->nr_resource > 0))
> > + caps->nr_resource += 1;
> > /*
> > * NUMSSCC, bits[23:20] the number of single-shot
> > * comparator control for tracing. Read any status regs as these
> > * also contain RO capability data.
> > */
> > - drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> > - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> > + for (i = 0; i < caps->nr_ss_cmp; i++) {
> > drvdata->config.ss_status[i] =
> > etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > }
> > /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> > - drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
> > + caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
> > /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> > - drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
> > + caps->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
> > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
> > /* NUMEXTIN, bits[8:0] number of external inputs implemented */
> > - drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
> > - drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
> > + caps->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
> > + caps->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
> > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
> > - drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
> > + caps->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
> > /* ATBTRIG, bit[22] implementation can support ATB triggers? */
> > - drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
> > + caps->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
> > /*
> > * LPOVERRIDE, bit[23] implementation supports
> > * low-power state override
> > */
> > - drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
> > + caps->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!caps->skip_power_up);
> > /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
> > - drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
> > + caps->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
> > /* NUMCNTR, bits[30:28] number of counters available for tracing */
> > - drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
> > + caps->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
> > coresight_clear_self_claim_tag_unlocked(csa);
> > etm4_cs_lock(drvdata, csa);
> > @@ -1691,7 +1701,7 @@ static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
> > * nr_addr_cmp holds the number of comparator _pair_, so time 2
> > * for the total number of comparators.
> > */
> > - nr_comparator = drvdata->nr_addr_cmp * 2;
> > + nr_comparator = drvdata->caps.nr_addr_cmp * 2;
> > /* Go through the tally of comparators looking for a free one. */
> > while (index < nr_comparator) {
> > @@ -1869,6 +1879,7 @@ static int etm4_dying_cpu(unsigned int cpu)
> > static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
> > {
> > int i, ret = 0;
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > struct etmv4_save_state *state;
> > struct coresight_device *csdev = drvdata->csdev;
> > struct csdev_access *csa;
> > @@ -1905,57 +1916,57 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
> > state = drvdata->save_state;
> > - if (drvdata->nr_pe)
> > + if (caps->nr_pe)
> > state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
> > state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
> > state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
> > state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
> > state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
> > - if (drvdata->stallctl)
> > + if (caps->stallctl)
> > state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
> > state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
> > state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
> > state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
> > state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
> > state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
> > - if (drvdata->q_filt)
> > + if (caps->q_filt)
> > state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
> > state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
> > state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
> > state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
> > - if (drvdata->nr_pe_cmp)
> > + if (caps->nr_pe_cmp)
> > state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + for (i = 0; i < caps->nrseqstate - 1; i++)
> > state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> > - if (drvdata->nrseqstate) {
> > + if (caps->nrseqstate) {
> > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> > }
> > - if (drvdata->numextinsel)
> > + if (caps->numextinsel)
> > state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
> > - for (i = 0; i < drvdata->nr_cntr; i++) {
> > + for (i = 0; i < caps->nr_cntr; i++) {
> > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
> > state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
> > state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
> > }
> > /* Resource selector pair 0 is reserved */
> > - for (i = 2; i < drvdata->nr_resource * 2; i++)
> > + for (i = 2; i < caps->nr_resource * 2; i++)
> > state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
> > - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + for (i = 0; i < caps->nr_ss_cmp; i++) {
> > state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
> > state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
> > if (etm4x_sspcicrn_present(drvdata, i))
> > state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
> > }
> > - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> > + for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
> > state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
> > state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
> > }
> > @@ -1967,23 +1978,23 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
> > * unit") of ARM IHI 0064D.
> > */
> > - for (i = 0; i < drvdata->numcidc; i++)
> > + for (i = 0; i < caps->numcidc; i++)
> > state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
> > - for (i = 0; i < drvdata->numvmidc; i++)
> > + for (i = 0; i < caps->numvmidc; i++)
> > state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
> > state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
> > - if (drvdata->numcidc > 4)
> > + if (caps->numcidc > 4)
> > state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
> > state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
> > - if (drvdata->numvmidc > 4)
> > + if (caps->numvmidc > 4)
> > state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
> > state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
> > - if (!drvdata->skip_power_up)
> > + if (!caps->skip_power_up)
> > state->trcpdcr = etm4x_read32(csa, TRCPDCR);
> > /* wait for TRCSTATR.IDLE to go up */
> > @@ -2000,7 +2011,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
> > * potentially save power on systems that respect the TRCPDCR_PU
> > * despite requesting software to save/restore state.
> > */
> > - if (!drvdata->skip_power_up)
> > + if (!caps->skip_power_up)
> > etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
> > TRCPDCR);
> > out:
> > @@ -2027,6 +2038,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> > static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> > {
> > int i;
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > struct etmv4_save_state *state = drvdata->save_state;
> > struct csdev_access *csa = &drvdata->csdev->access;
> > @@ -2036,77 +2048,77 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> > etm4_cs_unlock(drvdata, csa);
> > etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
> > - if (drvdata->nr_pe)
> > + if (caps->nr_pe)
> > etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
> > etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
> > etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
> > etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
> > etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
> > - if (drvdata->stallctl)
> > + if (caps->stallctl)
> > etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
> > etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
> > etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
> > etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
> > etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
> > etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
> > - if (drvdata->q_filt)
> > + if (caps->q_filt)
> > etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
> > etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
> > etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
> > etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
> > - if (drvdata->nr_pe_cmp)
> > + if (caps->nr_pe_cmp)
> > etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + for (i = 0; i < caps->nrseqstate - 1; i++)
> > etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> > - if (drvdata->nrseqstate) {
> > + if (caps->nrseqstate) {
> > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> > }
> > - if (drvdata->numextinsel)
> > + if (caps->numextinsel)
> > etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
> > - for (i = 0; i < drvdata->nr_cntr; i++) {
> > + for (i = 0; i < caps->nr_cntr; i++) {
> > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
> > etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
> > etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
> > }
> > /* Resource selector pair 0 is reserved */
> > - for (i = 2; i < drvdata->nr_resource * 2; i++)
> > + for (i = 2; i < caps->nr_resource * 2; i++)
> > etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
> > - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + for (i = 0; i < caps->nr_ss_cmp; i++) {
> > etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
> > etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
> > if (etm4x_sspcicrn_present(drvdata, i))
> > etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
> > }
> > - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> > + for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
> > etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
> > etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
> > }
> > - for (i = 0; i < drvdata->numcidc; i++)
> > + for (i = 0; i < caps->numcidc; i++)
> > etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
> > - for (i = 0; i < drvdata->numvmidc; i++)
> > + for (i = 0; i < caps->numvmidc; i++)
> > etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
> > etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
> > - if (drvdata->numcidc > 4)
> > + if (caps->numcidc > 4)
> > etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
> > etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
> > - if (drvdata->numvmidc > 4)
> > + if (caps->numvmidc > 4)
> > etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
> > etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
> > - if (!drvdata->skip_power_up)
> > + if (!caps->skip_power_up)
> > etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
> > /*
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index e9eeea6240d5..3d5f343130bd 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -62,8 +62,9 @@ static ssize_t nr_pe_cmp_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->nr_pe_cmp;
> > + val = caps->nr_pe_cmp;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(nr_pe_cmp);
> > @@ -74,8 +75,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->nr_addr_cmp;
> > + val = caps->nr_addr_cmp;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(nr_addr_cmp);
> > @@ -86,8 +88,9 @@ static ssize_t nr_cntr_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->nr_cntr;
> > + val = caps->nr_cntr;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(nr_cntr);
> > @@ -98,8 +101,9 @@ static ssize_t nr_ext_inp_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->nr_ext_inp;
> > + val = caps->nr_ext_inp;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(nr_ext_inp);
> > @@ -110,8 +114,9 @@ static ssize_t numcidc_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->numcidc;
> > + val = caps->numcidc;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(numcidc);
> > @@ -122,8 +127,9 @@ static ssize_t numvmidc_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->numvmidc;
> > + val = caps->numvmidc;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(numvmidc);
> > @@ -134,8 +140,9 @@ static ssize_t nrseqstate_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->nrseqstate;
> > + val = caps->nrseqstate;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(nrseqstate);
> > @@ -146,8 +153,9 @@ static ssize_t nr_resource_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->nr_resource;
> > + val = caps->nr_resource;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(nr_resource);
> > @@ -158,8 +166,9 @@ static ssize_t nr_ss_cmp_show(struct device *dev,
> > {
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > - val = drvdata->nr_ss_cmp;
> > + val = caps->nr_ss_cmp;
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > static DEVICE_ATTR_RO(nr_ss_cmp);
> > @@ -171,6 +180,7 @@ static ssize_t reset_store(struct device *dev,
> > int i;
> > unsigned long val;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > struct etmv4_config *config = &drvdata->config;
> > if (kstrtoul(buf, 16, &val))
> > @@ -200,7 +210,7 @@ static ssize_t reset_store(struct device *dev,
> > config->stall_ctrl = 0x0;
> > /* Reset trace synchronization period to 2^8 = 256 bytes*/
> > - if (drvdata->syncpr == false)
> > + if (caps->syncpr == false)
> > config->syncfreq = 0x8;
> > /*
> > @@ -209,7 +219,7 @@ static ssize_t reset_store(struct device *dev,
> > * each trace run.
> > */
> > config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
> > - if (drvdata->nr_addr_cmp > 0) {
> > + if (caps->nr_addr_cmp > 0) {
> > config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
> > /* SSSTATUS, bit[9] */
> > config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
> > @@ -223,7 +233,7 @@ static ssize_t reset_store(struct device *dev,
> > config->vipcssctlr = 0x0;
> > /* Disable seq events */
> > - for (i = 0; i < drvdata->nrseqstate-1; i++)
> > + for (i = 0; i < caps->nrseqstate-1; i++)
>
> from checkpatch:
> CHECK: spaces preferred around '-'
> coresight-etm4x-sysfs.c:236: caps->nrseqstate-1
Okay I'll change it.
>
> > config->seq_ctrl[i] = 0x0;
> > config->seq_rst = 0x0;
> > config->seq_state = 0x0;
> > @@ -232,38 +242,38 @@ static ssize_t reset_store(struct device *dev,
> > config->ext_inp = 0x0;
> > config->cntr_idx = 0x0;
> > - for (i = 0; i < drvdata->nr_cntr; i++) {
> > + for (i = 0; i < caps->nr_cntr; i++) {
> > config->cntrldvr[i] = 0x0;
> > config->cntr_ctrl[i] = 0x0;
> > config->cntr_val[i] = 0x0;
> > }
> > config->res_idx = 0x0;
> > - for (i = 2; i < 2 * drvdata->nr_resource; i++)
> > + for (i = 2; i < 2 * caps->nr_resource; i++)
> > config->res_ctrl[i] = 0x0;
> > config->ss_idx = 0x0;
> > - for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + for (i = 0; i < caps->nr_ss_cmp; i++) {
> > config->ss_ctrl[i] = 0x0;
> > config->ss_pe_cmp[i] = 0x0;
> > }
> > config->addr_idx = 0x0;
> > - for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> > + for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
> > config->addr_val[i] = 0x0;
> > config->addr_acc[i] = 0x0;
> > config->addr_type[i] = ETM_ADDR_TYPE_NONE;
> > }
> > config->ctxid_idx = 0x0;
> > - for (i = 0; i < drvdata->numcidc; i++)
> > + for (i = 0; i < caps->numcidc; i++)
> > config->ctxid_pid[i] = 0x0;
> > config->ctxid_mask0 = 0x0;
> > config->ctxid_mask1 = 0x0;
> > config->vmid_idx = 0x0;
> > - for (i = 0; i < drvdata->numvmidc; i++)
> > + for (i = 0; i < caps->numvmidc; i++)
> > config->vmid_val[i] = 0x0;
> > config->vmid_mask0 = 0x0;
> > config->vmid_mask1 = 0x0;
> > @@ -297,6 +307,7 @@ static ssize_t mode_store(struct device *dev,
> > {
> > unsigned long val, mode;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + const struct etmv4_caps *caps = &drvdata->caps;
> > struct etmv4_config *config = &drvdata->config;
> > if (kstrtoul(buf, 16, &val))
> > @@ -305,7 +316,7 @@ static ssize_t mode_store(struct device *dev,
> > raw_spin_lock(&drvdata->spinlock);
> > config->mode = val & ETMv4_MODE_ALL;
> > - if (drvdata->instrp0 == true) {
> > + if (caps->instrp0 == true) {
>
> find so many foo == true && foo == false formats from legacy codes.
> I think it's worth to change all to if (foo) && if (!foo) ?
>
> example here,
>
> if (caps->instrp0)
Agree. This is good chance to remove some legacy formats.
>
> > /* start by clearing instruction P0 field */
> > config->cfg &= ~TRCCONFIGR_INSTP0_LOAD_STORE;
> > if (config->mode & ETM_MODE_LOAD)
> > @@ -323,45 +334,45 @@ static ssize_t mode_store(struct device *dev,
> > }
> > /* bit[3], Branch broadcast mode */
> > - if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
> > + if ((config->mode & ETM_MODE_BB) && (caps->trcbb == true))
> > config->cfg |= TRCCONFIGR_BB;
>
> <...>
>
> > @@ -1037,46 +1081,11 @@ struct etmv4_drvdata {
> > raw_spinlock_t spinlock;
> > int cpu;
> > u8 arch;
> > - u8 nr_pe;
> > - u8 nr_pe_cmp;
> > - u8 nr_addr_cmp;
> > - u8 nr_cntr;
> > - u8 nr_ext_inp;
> > - u8 numcidc;
> > - u8 numextinsel;
> > - u8 numvmidc;
> > - u8 nrseqstate;
> > - u8 nr_event;
> > - u8 nr_resource;
> > - u8 nr_ss_cmp;
> > + struct etmv4_caps caps;
>
> reported by checkpatch:
> WARNING: please, no space before tabs
Thanks.
>
> > u8 trcid;
> > - u8 trcid_size;
> > - u8 ts_size;
> > - u8 ctxid_size;
> > - u8 vmid_size;
> > - u8 ccsize;
> > - u16 ccitmin;
> > - u8 s_ex_level;
> > - u8 ns_ex_level;
> > - u8 q_support;
> > - u8 os_lock_model;
> > bool sticky_enable : 1;
> > bool boot_enable : 1;
> > bool os_unlock : 1;
> > - bool instrp0 : 1;
> > - bool q_filt : 1;
> > - bool trcbb : 1;
> > - bool trccond : 1;
> > - bool retstack : 1;
> > - bool trccci : 1;
> > - bool trc_error : 1;
> > - bool syncpr : 1;
> > - bool stallctl : 1;
> > - bool sysstall : 1;
> > - bool nooverflow : 1;
> > - bool atbtrig : 1;
> > - bool lpoverride : 1;
> > - bool skip_power_up : 1;
> > bool paused : 1;
> > u64 trfcr;
> > struct etmv4_config config;
>
--
Sincerely,
Yeoreum Yun
^ permalink raw reply
* [PATCH 0/6] arm64: defconfig: Cleanup and change Ethernet drivers
From: Krzysztof Kozlowski @ 2026-04-12 16:21 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
Several first commits have no functional impact. The last two might
have.
Best regards,
Krzysztof
---
Krzysztof Kozlowski (6):
arm64: defconfig: Move entries to match savedefconfig
arm64: defconfig: Drop unused legacy netfilter options
arm64: defconfig: Drop default or selected drivers
arm64: defconfig: Drop unused Ethernet vendors
arm64: defconfig: Drop AMD XGBE Ethernet driver
arm64: defconfig: Switch Ethernet drivers to modules
arch/arm64/configs/defconfig | 371 +++++++++++++++++++++++--------------------
1 file changed, 195 insertions(+), 176 deletions(-)
---
base-commit: 66672af7a095d89f082c5327f3b15bc2f93d558e
change-id: 20260412-defconfig-b57e7f9b5394
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
^ permalink raw reply
* [PATCH 1/6] arm64: defconfig: Move entries to match savedefconfig
From: Krzysztof Kozlowski @ 2026-04-12 16:21 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260412-defconfig-v1-0-a46918286451@oss.qualcomm.com>
Only re-shuffle entries to match savedefconfig, without removing any
symbols. This helps in reviewing defconfig when comparing with
savedefconfig and looking for obsolete symbols. No impact on
include/generated/autoconf.h.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 218 +++++++++++++++++++++----------------------
1 file changed, 109 insertions(+), 109 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index dd1ac01ee29b..9c03ae2c767e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -50,7 +50,6 @@ CONFIG_ARCH_BLAIZE=y
CONFIG_ARCH_BST=y
CONFIG_ARCH_CIX=y
CONFIG_ARCH_EXYNOS=y
-CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
CONFIG_ARCH_LG1K=y
CONFIG_ARCH_HISI=y
@@ -58,6 +57,7 @@ CONFIG_ARCH_KEEMBAY=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MICROCHIP=y
+CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_NXP=y
CONFIG_ARCH_LAYERSCAPE=y
@@ -99,7 +99,6 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPUFREQ_DT=y
-CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
CONFIG_ARM_APPLE_SOC_CPUFREQ=m
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
@@ -112,6 +111,7 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
CONFIG_ARM_SCMI_CPUFREQ=y
CONFIG_ARM_TEGRA186_CPUFREQ=y
CONFIG_QORIQ_CPUFREQ=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_ACPI=y
CONFIG_ACPI_HOTPLUG_MEMORY=y
CONFIG_ACPI_HMAT=y
@@ -126,6 +126,7 @@ CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_IOSCHED_BFQ=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MEMORY_HOTPLUG=y
@@ -182,8 +183,8 @@ CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_GACT=m
CONFIG_NET_ACT_MIRRED=m
-CONFIG_HSR=m
CONFIG_NET_ACT_GATE=m
+CONFIG_HSR=m
CONFIG_QRTR_SMD=m
CONFIG_QRTR_TUN=m
CONFIG_CAN=m
@@ -241,8 +242,8 @@ CONFIG_PCIE_XILINX=y
CONFIG_PCIE_XILINX_DMA_PL=y
CONFIG_PCIE_XILINX_NWL=y
CONFIG_PCIE_XILINX_CPM=y
-CONFIG_PCI_J721E_HOST=m
CONFIG_PCI_SKY1_HOST=m
+CONFIG_PCI_J721E_HOST=m
CONFIG_PCI_IMX6_HOST=y
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y
@@ -265,6 +266,7 @@ CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_HISILICON_LPC=y
+CONFIG_IMX_AIPSTZ=m
CONFIG_TEGRA_ACONNECT=m
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_ARM_SCMI_PROTOCOL=y
@@ -277,7 +279,6 @@ CONFIG_GOOGLE_FIRMWARE=y
CONFIG_GOOGLE_CBMEM=m
CONFIG_GOOGLE_COREBOOT_TABLE=m
CONFIG_EFI_CAPSULE_LOADER=y
-CONFIG_IMX_AIPSTZ=m
CONFIG_IMX_SCU=y
CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE=y
CONFIG_QCOM_QSEECOM=y
@@ -304,11 +305,12 @@ CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_NAND_BRCMNAND=m
CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NAND=m
+CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=m
CONFIG_MTD_HYPERBUS=m
CONFIG_HBMC_AM654=m
+CONFIG_OF_OVERLAY=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=m
CONFIG_VIRTIO_BLK=y
@@ -322,6 +324,7 @@ CONFIG_XILINX_SDFEC=m
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_AT25=m
CONFIG_UACCE=m
+CONFIG_MISC_RP1=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SAS_ATA=y
@@ -424,8 +427,8 @@ CONFIG_REALTEK_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_DP83867_PHY=y
CONFIG_DP83869_PHY=m
-CONFIG_DP83TG720_PHY=m
CONFIG_DP83TD510_PHY=y
+CONFIG_DP83TG720_PHY=m
CONFIG_VITESSE_PHY=y
CONFIG_XILINX_GMII2RGMII=m
CONFIG_CAN_FLEXCAN=m
@@ -631,8 +634,6 @@ CONFIG_SPMI=y
CONFIG_SPMI_APPLE=m
CONFIG_SPMI_MTK_PMIF=m
CONFIG_PINCTRL_APPLE_GPIO=m
-CONFIG_PINCTRL_BRCMSTB=y
-CONFIG_PINCTRL_BCM2712=y
CONFIG_PINCTRL_DA9062=m
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_RK805=m
@@ -649,9 +650,12 @@ CONFIG_PINCTRL_IMX8QM=y
CONFIG_PINCTRL_IMX8QXP=y
CONFIG_PINCTRL_IMX8DXL=y
CONFIG_PINCTRL_IMX8ULP=y
-CONFIG_PINCTRL_IMX91=y
CONFIG_PINCTRL_IMX93=y
+CONFIG_PINCTRL_BRCMSTB=y
+CONFIG_PINCTRL_BCM2712=y
+CONFIG_PINCTRL_SKY1=y
CONFIG_PINCTRL_IMX_SCMI=y
+CONFIG_PINCTRL_IMX91=y
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_ELIZA=y
CONFIG_PINCTRL_GLYMUR=y
@@ -685,7 +689,6 @@ CONFIG_PINCTRL_SDM660=y
CONFIG_PINCTRL_SDM670=y
CONFIG_PINCTRL_SDM845=y
CONFIG_PINCTRL_SDX75=y
-CONFIG_PINCTRL_SKY1=y
CONFIG_PINCTRL_SM4450=y
CONFIG_PINCTRL_SM6115=y
CONFIG_PINCTRL_SM6125=y
@@ -722,9 +725,9 @@ CONFIG_GPIO_PL061=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_UNIPHIER=y
+CONFIG_GPIO_VF610=y
CONFIG_GPIO_VISCONTI=y
CONFIG_GPIO_WCD934X=m
-CONFIG_GPIO_VF610=y
CONFIG_GPIO_XGENE=y
CONFIG_GPIO_XGENE_SB=y
CONFIG_GPIO_XILINX=m
@@ -732,9 +735,9 @@ CONFIG_GPIO_ZYNQ=m
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GPIO_ADP5585=m
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
+CONFIG_GPIO_ADP5585=m
CONFIG_GPIO_BD9571MWV=m
CONFIG_GPIO_MACSMC=m
CONFIG_GPIO_MAX77620=y
@@ -773,7 +776,6 @@ CONFIG_SENSORS_AMC6821=m
CONFIG_SENSORS_INA2XX=m
CONFIG_SENSORS_INA3221=m
CONFIG_SENSORS_TMP102=m
-CONFIG_MISC_RP1=m
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
@@ -784,11 +786,6 @@ CONFIG_K3_THERMAL=m
CONFIG_QORIQ_THERMAL=m
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=m
-CONFIG_RCAR_THERMAL=y
-CONFIG_RCAR_GEN3_THERMAL=y
-CONFIG_RZG2L_THERMAL=y
-CONFIG_RZG3E_THERMAL=y
-CONFIG_RZG3S_THERMAL=m
CONFIG_ARMADA_THERMAL=y
CONFIG_MTK_THERMAL=m
CONFIG_MTK_LVTS_THERMAL=m
@@ -796,6 +793,11 @@ CONFIG_BCM2711_THERMAL=m
CONFIG_BCM2835_THERMAL=m
CONFIG_BRCMSTB_THERMAL=m
CONFIG_EXYNOS_THERMAL=y
+CONFIG_RCAR_THERMAL=y
+CONFIG_RCAR_GEN3_THERMAL=y
+CONFIG_RZG2L_THERMAL=y
+CONFIG_RZG3E_THERMAL=y
+CONFIG_RZG3S_THERMAL=m
CONFIG_TEGRA_SOCTHERM=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_GENERIC_ADC_THERMAL=m
@@ -921,10 +923,10 @@ CONFIG_SDR_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_AMPHION_VPU=m
CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_MEDIATEK_JPEG=m
-CONFIG_VIDEO_MEDIATEK_VCODEC=m
CONFIG_VIDEO_WAVE_VPU=m
CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_MEDIATEK_JPEG=m
+CONFIG_VIDEO_MEDIATEK_VCODEC=m
CONFIG_VIDEO_MEDIATEK_MDP3=m
CONFIG_VIDEO_IMX7_CSI=m
CONFIG_VIDEO_IMX_MIPI_CSIS=m
@@ -934,8 +936,8 @@ CONFIG_VIDEO_IMX8_JPEG=m
CONFIG_VIDEO_QCOM_CAMSS=m
CONFIG_VIDEO_QCOM_IRIS=m
CONFIG_VIDEO_QCOM_VENUS=m
-CONFIG_VIDEO_RCAR_ISP=m
CONFIG_VIDEO_RCAR_CSI2=m
+CONFIG_VIDEO_RCAR_ISP=m
CONFIG_VIDEO_RCAR_VIN=m
CONFIG_VIDEO_RZG2L_CSI2=m
CONFIG_VIDEO_RZG2L_CRU=m
@@ -943,8 +945,8 @@ CONFIG_VIDEO_RENESAS_FCP=m
CONFIG_VIDEO_RENESAS_FDP1=m
CONFIG_VIDEO_RENESAS_VSP1=m
CONFIG_VIDEO_RCAR_DRIF=m
-CONFIG_VIDEO_ROCKCHIP_CIF=m
CONFIG_VIDEO_ROCKCHIP_RGA=m
+CONFIG_VIDEO_ROCKCHIP_CIF=m
CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
@@ -959,64 +961,17 @@ CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_S5KJN1=m
CONFIG_DRM=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
CONFIG_DRM_HDLCD=m
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
-CONFIG_DRM_NOUVEAU=m
-CONFIG_DRM_EXYNOS=m
-CONFIG_DRM_EXYNOS5433_DECON=y
-CONFIG_DRM_EXYNOS7_DECON=y
-CONFIG_DRM_EXYNOS_DSI=y
-# CONFIG_DRM_EXYNOS_DP is not set
-CONFIG_DRM_EXYNOS_HDMI=y
-CONFIG_DRM_EXYNOS_MIC=y
-CONFIG_DRM_ROCKCHIP=m
-CONFIG_ROCKCHIP_VOP2=y
-CONFIG_ROCKCHIP_ANALOGIX_DP=y
-CONFIG_ROCKCHIP_CDN_DP=y
-CONFIG_ROCKCHIP_DW_DP=y
-CONFIG_ROCKCHIP_DW_HDMI=y
-CONFIG_ROCKCHIP_DW_HDMI_QP=y
-CONFIG_ROCKCHIP_DW_MIPI_DSI=y
-CONFIG_ROCKCHIP_INNO_HDMI=y
-CONFIG_ROCKCHIP_LVDS=y
-CONFIG_DRM_RCAR_DU=m
-CONFIG_DRM_RCAR_DW_HDMI=m
CONFIG_DRM_RCAR_MIPI_DSI=m
CONFIG_DRM_RZG2L_MIPI_DSI=m
-CONFIG_DRM_RZG2L_DU=m
-CONFIG_DRM_SUN4I=m
CONFIG_DRM_SUN6I_DSI=m
CONFIG_DRM_SUN8I_DW_HDMI=m
CONFIG_DRM_SUN8I_MIXER=m
-CONFIG_DRM_MSM=m
-CONFIG_DRM_TEGRA=m
-CONFIG_DRM_STM=m
-CONFIG_DRM_STM_LVDS=m
-CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
-CONFIG_DRM_PANEL_LVDS=m
-CONFIG_DRM_PANEL_SIMPLE=m
-CONFIG_DRM_PANEL_SUMMIT=m
-CONFIG_DRM_PANEL_EDP=m
-CONFIG_DRM_PANEL_HIMAX_HX8279=m
-CONFIG_DRM_PANEL_HIMAX_HX83112A=m
-CONFIG_DRM_PANEL_HIMAX_HX83112B=m
-CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
-CONFIG_DRM_PANEL_KHADAS_TS050=m
-CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
-CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
-CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
-CONFIG_DRM_PANEL_NOVATEK_NT37801=m
-CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
-CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m
-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
-CONFIG_DRM_PANEL_SITRONIX_ST7703=m
-CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
-CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
-CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_DRM_FSL_LDB=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
CONFIG_DRM_ITE_IT6263=m
CONFIG_DRM_LONTIUM_LT8912B=m
CONFIG_DRM_LONTIUM_LT9611=m
@@ -1043,27 +998,74 @@ CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_HDMI_QP_CEC=y
-CONFIG_DRM_IMX_DCSS=m
-CONFIG_DRM_V3D=m
-CONFIG_DRM_VC4=m
CONFIG_DRM_ETNAVIV=m
+CONFIG_DRM_EXYNOS=m
+CONFIG_DRM_EXYNOS5433_DECON=y
+CONFIG_DRM_EXYNOS7_DECON=y
+CONFIG_DRM_EXYNOS_DSI=y
+# CONFIG_DRM_EXYNOS_DP is not set
+CONFIG_DRM_EXYNOS_HDMI=y
+CONFIG_DRM_EXYNOS_MIC=y
CONFIG_DRM_HISI_HIBMC=m
CONFIG_DRM_HISI_KIRIN=m
+CONFIG_DRM_POWERVR=m
+CONFIG_DRM_IMX_DCSS=m
+CONFIG_DRM_LIMA=m
CONFIG_DRM_MEDIATEK=m
CONFIG_DRM_MEDIATEK_DP=m
CONFIG_DRM_MEDIATEK_HDMI=m
CONFIG_DRM_MEDIATEK_HDMI_V2=m
+CONFIG_DRM_MESON=m
+CONFIG_DRM_MSM=m
CONFIG_DRM_MXSFB=m
CONFIG_DRM_IMX_LCDIF=m
-CONFIG_DRM_MESON=m
-CONFIG_DRM_PL111=m
-CONFIG_DRM_LIMA=m
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+CONFIG_DRM_PANEL_LVDS=m
+CONFIG_DRM_PANEL_HIMAX_HX8279=m
+CONFIG_DRM_PANEL_HIMAX_HX83112A=m
+CONFIG_DRM_PANEL_HIMAX_HX83112B=m
+CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
+CONFIG_DRM_PANEL_KHADAS_TS050=m
+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
+CONFIG_DRM_PANEL_NOVATEK_NT37801=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m
+CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
+CONFIG_DRM_PANEL_EDP=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_SUMMIT=m
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
CONFIG_DRM_PANFROST=m
CONFIG_DRM_PANTHOR=m
+CONFIG_DRM_PL111=m
+CONFIG_DRM_RCAR_DU=m
+CONFIG_DRM_RCAR_DW_HDMI=m
+CONFIG_DRM_RZG2L_DU=m
+CONFIG_DRM_ROCKCHIP=m
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_CDN_DP=y
+CONFIG_ROCKCHIP_DW_DP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_HDMI_QP=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_LVDS=y
+CONFIG_DRM_STM=m
+CONFIG_DRM_STM_LVDS=m
+CONFIG_DRM_SUN4I=m
+CONFIG_DRM_TEGRA=m
CONFIG_DRM_TIDSS=m
+CONFIG_DRM_V3D=m
+CONFIG_DRM_VC4=m
CONFIG_DRM_ZYNQMP_DPSUB=m
CONFIG_DRM_ZYNQMP_DPSUB_AUDIO=y
-CONFIG_DRM_POWERVR=m
CONFIG_FB=y
CONFIG_FB_EFI=y
CONFIG_FB_MODE_HELPERS=y
@@ -1117,20 +1119,15 @@ CONFIG_SND_SOC_SC7180=m
CONFIG_SND_SOC_SC7280=m
CONFIG_SND_SOC_X1E80100=m
CONFIG_SND_SOC_ROCKCHIP=m
+CONFIG_SND_SOC_RCAR=m
+CONFIG_SND_SOC_MSIOF=m
+CONFIG_SND_SOC_RZ=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_ROCKCHIP_SAI=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
-CONFIG_SND_SOC_RCAR=m
-CONFIG_SND_SOC_MSIOF=m
-CONFIG_SND_SOC_RZ=m
CONFIG_SND_SOC_SAMSUNG=m
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_OF=m
-CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_MT8186=m
-CONFIG_SND_SOC_SOF_MT8195=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
@@ -1155,6 +1152,11 @@ CONFIG_SND_SOC_J721E_EVM=m
CONFIG_SND_SOC_XILINX_I2S=m
CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
CONFIG_SND_SOC_XILINX_SPDIF=m
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_OF=m
+CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_MT8186=m
+CONFIG_SND_SOC_SOF_MT8195=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_AK4619=m
CONFIG_SND_SOC_DA7213=m
@@ -1228,7 +1230,6 @@ CONFIG_USB_MTU3=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB_DWC3=y
-CONFIG_OMAP_USB2=m
CONFIG_USB_DWC2=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
@@ -1314,6 +1315,7 @@ CONFIG_MMC_SDHCI_AM654=y
CONFIG_MMC_OWL=y
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFS_BSG=y
+CONFIG_SCSI_UFS_CRYPTO=y
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_CDNS_PLATFORM=m
CONFIG_SCSI_UFS_QCOM=m
@@ -1323,8 +1325,6 @@ CONFIG_SCSI_UFS_RENESAS=m
CONFIG_SCSI_UFS_TI_J721E=m
CONFIG_SCSI_UFS_EXYNOS=y
CONFIG_SCSI_UFS_ROCKCHIP=y
-CONFIG_BLK_INLINE_ENCRYPTION=y
-CONFIG_SCSI_UFS_CRYPTO=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
@@ -1351,9 +1351,9 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_HYM8563=m
CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_NVIDIA_VRS10=m
CONFIG_RTC_DRV_RK808=m
CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_M41T80=m
@@ -1361,10 +1361,10 @@ CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RV3028=m
CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_S32G=m
CONFIG_RTC_DRV_S5M=y
CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_DA9063=m
CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_ZYNQMP=m
@@ -1383,8 +1383,8 @@ CONFIG_RTC_DRV_MT6397=m
CONFIG_RTC_DRV_XGENE=y
CONFIG_RTC_DRV_TI_K3=m
CONFIG_RTC_DRV_RENESAS_RTCA3=m
-CONFIG_RTC_DRV_NVIDIA_VRS10=m
CONFIG_RTC_DRV_MACSMC=m
+CONFIG_RTC_DRV_S32G=m
CONFIG_DMADEVICES=y
CONFIG_APPLE_ADMAC=m
CONFIG_DMA_BCM2835=y
@@ -1435,11 +1435,11 @@ CONFIG_CROS_EC_RPMSG=m
CONFIG_CROS_EC_SPI=y
CONFIG_CROS_KBD_LED_BACKLIGHT=m
CONFIG_CROS_EC_CHARDEV=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
CONFIG_EC_ACER_ASPIRE1=m
CONFIG_EC_HUAWEI_GAOKUN=m
CONFIG_EC_LENOVO_YOGA_C630=m
CONFIG_EC_LENOVO_THINKPAD_T14S=m
+CONFIG_COMMON_CLK_APPLE_NCO=m
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
@@ -1524,17 +1524,16 @@ CONFIG_QCM_DISPCC_2290=m
CONFIG_QCS_DISPCC_615=m
CONFIG_QCS_CAMCC_615=m
CONFIG_QCS_GCC_404=y
-CONFIG_QCS_GCC_615=y
-CONFIG_QCS_GCC_8300=y
-CONFIG_SC_CAMCC_7280=m
CONFIG_SA_CAMCC_8775P=m
+CONFIG_QCS_GCC_8300=y
+CONFIG_QCS_GCC_615=y
CONFIG_QCS_GPUCC_615=m
CONFIG_QCS_VIDEOCC_615=m
-CONFIG_QDU_GCC_1000=y
+CONFIG_SC_CAMCC_7280=m
CONFIG_SC_CAMCC_8280XP=m
+CONFIG_SA_DISPCC_8775P=m
CONFIG_SC_DISPCC_7280=m
CONFIG_SC_DISPCC_8280XP=m
-CONFIG_SA_DISPCC_8775P=m
CONFIG_SA_GCC_8775P=y
CONFIG_SA_GPUCC_8775P=m
CONFIG_SC_GCC_7180=y
@@ -1547,6 +1546,7 @@ CONFIG_SC_LPASSCC_8280XP=m
CONFIG_SC_LPASS_CORECC_7280=m
CONFIG_SC_VIDEOCC_7280=m
CONFIG_SDM_CAMCC_845=m
+CONFIG_QDU_GCC_1000=y
CONFIG_SDM_GPUCC_845=y
CONFIG_SDM_VIDEOCC_845=y
CONFIG_SDM_DISPCC_845=y
@@ -1611,22 +1611,22 @@ CONFIG_RENESAS_OSTM=y
CONFIG_ARM_MHU=y
CONFIG_EXYNOS_MBOX=m
CONFIG_IMX_MBOX=y
-CONFIG_OMAP2PLUS_MBOX=m
CONFIG_PLATFORM_MHU=y
+CONFIG_OMAP2PLUS_MBOX=m
CONFIG_BCM2835_MBOX=y
CONFIG_QCOM_APCS_IPC=y
+CONFIG_TEGRA_HSP_MBOX=y
CONFIG_MTK_ADSP_MBOX=m
CONFIG_QCOM_CPUCP_MBOX=m
-CONFIG_TEGRA_HSP_MBOX=y
CONFIG_QCOM_IPCC=y
CONFIG_CIX_MBOX=y
-CONFIG_ROCKCHIP_IOMMU=y
-CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_V3=y
-CONFIG_MTK_IOMMU=y
CONFIG_QCOM_IOMMU=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_APPLE_DART=m
+CONFIG_MTK_IOMMU=y
CONFIG_REMOTEPROC=y
CONFIG_IMX_REMOTEPROC=y
CONFIG_MTK_SCP=m
@@ -1730,9 +1730,9 @@ CONFIG_PWM_BCM2835=m
CONFIG_PWM_BRCMSTB=m
CONFIG_PWM_CROS_EC=m
CONFIG_PWM_IMX27=m
+CONFIG_PWM_MEDIATEK=m
CONFIG_PWM_MESON=m
CONFIG_PWM_MTK_DISP=m
-CONFIG_PWM_MEDIATEK=m
CONFIG_PWM_RENESAS_RCAR=m
CONFIG_PWM_RENESAS_RZG2L_GPT=m
CONFIG_PWM_RENESAS_RZ_MTU3=m
@@ -1760,10 +1760,10 @@ CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_RESET_RZV2H_USB2PHY=m
CONFIG_RESET_TI_SCI=y
-CONFIG_PHY_SNPS_EUSB2=m
-CONFIG_PHY_XGENE=y
CONFIG_PHY_CAN_TRANSCEIVER=m
CONFIG_PHY_NXP_PTN3222=m
+CONFIG_PHY_SNPS_EUSB2=m
+CONFIG_PHY_XGENE=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_CADENCE_TORRENT=m
CONFIG_PHY_CADENCE_DPHY=m
@@ -1814,6 +1814,7 @@ CONFIG_PHY_UNIPHIER_USB3=y
CONFIG_PHY_TEGRA_XUSB=y
CONFIG_PHY_AM654_SERDES=m
CONFIG_PHY_J721E_WIZ=m
+CONFIG_OMAP_USB2=m
CONFIG_PHY_XILINX_ZYNQMP=m
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCN=m
@@ -1857,7 +1858,6 @@ CONFIG_ALTERA_FREEZE_BRIDGE=m
CONFIG_XILINX_PR_DECOUPLER=m
CONFIG_FPGA_REGION=m
CONFIG_OF_FPGA_REGION=m
-CONFIG_OF_OVERLAY=y
CONFIG_FPGA_MGR_ZYNQMP_FPGA=m
CONFIG_FPGA_MGR_VERSAL_FPGA=m
CONFIG_TEE=y
@@ -1906,9 +1906,9 @@ CONFIG_INTERCONNECT_QCOM_SM8650=y
CONFIG_INTERCONNECT_QCOM_SM8750=y
CONFIG_INTERCONNECT_QCOM_X1E80100=y
CONFIG_COUNTER=m
-CONFIG_TI_EQEP=m
CONFIG_RZ_MTU3_CNT=m
CONFIG_STM32_TIMER_CNT=m
+CONFIG_TI_EQEP=m
CONFIG_HTE=y
CONFIG_HTE_TEGRA194=y
CONFIG_HTE_TEGRA194_TEST=m
@@ -1942,8 +1942,8 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_USER=y
-CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_BENCHMARK=m
+CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_SHA3=m
CONFIG_CRYPTO_SM3=m
--
2.51.0
^ permalink raw reply related
* [PATCH 2/6] arm64: defconfig: Drop unused legacy netfilter options
From: Krzysztof Kozlowski @ 2026-04-12 16:21 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260412-defconfig-v1-0-a46918286451@oss.qualcomm.com>
Drop all options which are ineffective now, because they depend on
disabled IP_NF_IPTABLES_LEGACY or IP6_NF_IPTABLES_LEGACY. No impact on
include/generated/autoconf.h.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 9c03ae2c767e..9a31b258a56e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -155,17 +155,7 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_IP_VS=m
CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_MANGLE=m
CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_NET_DSA=m
--
2.51.0
^ permalink raw reply related
* [PATCH 3/6] arm64: defconfig: Drop default or selected drivers
From: Krzysztof Kozlowski @ 2026-04-12 16:21 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260412-defconfig-v1-0-a46918286451@oss.qualcomm.com>
Drop all options which are either defaults or selected by other drivers:
1. IMX Pinctrl drivers are defaults for this ARCH.
2. RP1 is selected by MISC_RP1.
3. I2C_DESIGNWARE_PLATFORM is default with I2C_DESIGNWARE_CORE.
4. DRM_SAMSUNG_DSIM is selected by DRM_EXYNOS_DSI.
5. SUN6I, SUN8I and Renesas DRM drivers have defaults.
6. SND_SOC_ROCKCHIP does not exist.
7. Several ASoC drivers are selected by other main sound switches.
8. USB_CDNS3_IMX is default with USB_CDNS3.
9. IPQ_APSS_5018 never existed.
No impact on include/generated/autoconf.h.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 23 -----------------------
1 file changed, 23 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 9a31b258a56e..c9f6d5d6ef69 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -557,7 +557,6 @@ CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_BCM2835=m
CONFIG_I2C_CADENCE=m
CONFIG_I2C_DESIGNWARE_CORE=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_GPIO=m
CONFIG_I2C_IMX=y
CONFIG_I2C_IMX_LPI2C=y
@@ -632,15 +631,6 @@ CONFIG_PINCTRL_SX150X=m
CONFIG_PINCTRL_OWL=y
CONFIG_PINCTRL_S700=y
CONFIG_PINCTRL_S900=y
-CONFIG_PINCTRL_IMX8MM=y
-CONFIG_PINCTRL_IMX8MN=y
-CONFIG_PINCTRL_IMX8MP=y
-CONFIG_PINCTRL_IMX8MQ=y
-CONFIG_PINCTRL_IMX8QM=y
-CONFIG_PINCTRL_IMX8QXP=y
-CONFIG_PINCTRL_IMX8DXL=y
-CONFIG_PINCTRL_IMX8ULP=y
-CONFIG_PINCTRL_IMX93=y
CONFIG_PINCTRL_BRCMSTB=y
CONFIG_PINCTRL_BCM2712=y
CONFIG_PINCTRL_SKY1=y
@@ -669,7 +659,6 @@ CONFIG_PINCTRL_QCS615=y
CONFIG_PINCTRL_QCS8300=y
CONFIG_PINCTRL_QDF2XXX=y
CONFIG_PINCTRL_QDU1000=y
-CONFIG_PINCTRL_RP1=m
CONFIG_PINCTRL_SA8775P=y
CONFIG_PINCTRL_SC7180=y
CONFIG_PINCTRL_SC7280=y
@@ -954,11 +943,6 @@ CONFIG_DRM=m
CONFIG_DRM_HDLCD=m
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_RZG2L_MIPI_DSI=m
-CONFIG_DRM_SUN6I_DSI=m
-CONFIG_DRM_SUN8I_DW_HDMI=m
-CONFIG_DRM_SUN8I_MIXER=m
CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_DRM_FSL_LDB=m
CONFIG_DRM_I2C_NXP_TDA998X=m
@@ -970,7 +954,6 @@ CONFIG_DRM_LONTIUM_LT8713SX=m
CONFIG_DRM_ITE_IT66121=m
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_PARADE_PS8640=m
-CONFIG_DRM_SAMSUNG_DSIM=m
CONFIG_DRM_SII902X=m
CONFIG_DRM_SIMPLE_BRIDGE=m
CONFIG_DRM_THINE_THC63LVD1024=m
@@ -1108,7 +1091,6 @@ CONFIG_SND_SOC_SC8280XP=m
CONFIG_SND_SOC_SC7180=m
CONFIG_SND_SOC_SC7280=m
CONFIG_SND_SOC_X1E80100=m
-CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_RCAR=m
CONFIG_SND_SOC_MSIOF=m
CONFIG_SND_SOC_RZ=m
@@ -1137,7 +1119,6 @@ CONFIG_SND_SOC_TEGRA210_AMX=m
CONFIG_SND_SOC_TEGRA210_ADX=m
CONFIG_SND_SOC_TEGRA210_MIXER=m
CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
-CONFIG_SND_SOC_DAVINCI_MCASP=m
CONFIG_SND_SOC_J721E_EVM=m
CONFIG_SND_SOC_XILINX_I2S=m
CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
@@ -1158,7 +1139,6 @@ CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
CONFIG_SND_SOC_RK3308=m
CONFIG_SND_SOC_RK817=m
CONFIG_SND_SOC_RT5640=m
@@ -1215,7 +1195,6 @@ CONFIG_USB_CDNS_SUPPORT=m
CONFIG_USB_CDNS3=m
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_IMX=m
CONFIG_USB_MTU3=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_SUNXI=y
@@ -1437,7 +1416,6 @@ CONFIG_COMMON_CLK_CS2000_CP=y
CONFIG_COMMON_CLK_FSL_SAI=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_COMMON_CLK_PWM=y
-CONFIG_COMMON_CLK_RP1=m
CONFIG_COMMON_CLK_RS9_PCIE=y
CONFIG_COMMON_CLK_VC3=y
CONFIG_COMMON_CLK_VC5=y
@@ -1490,7 +1468,6 @@ CONFIG_QCOM_CLK_APCC_MSM8996=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_APSS_6018=y
-CONFIG_IPQ_APSS_5018=y
CONFIG_IPQ_CMN_PLL=m
CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_5210=y
--
2.51.0
^ permalink raw reply related
* [PATCH 4/6] arm64: defconfig: Drop unused Ethernet vendors
From: Krzysztof Kozlowski @ 2026-04-12 16:21 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260412-defconfig-v1-0-a46918286451@oss.qualcomm.com>
Make going through `make menuconfig` easier by disabling the unused
Ethernet vendor menu options, where no actual driver for given vendor is
selected.
Impact checked with comparing old and new autoconf.h:
diff ... | grep '^-' | grep -v CONFIG_NET_VENDOR
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 51 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9f6d5d6ef69..79f6294fffdf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -349,15 +349,33 @@ CONFIG_VIRTIO_NET=y
CONFIG_MHI_NET=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_MSCC_FELIX=m
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ACTIONS is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_ALLWINNER is not set
CONFIG_ENA_ETHERNET=m
CONFIG_AMD_XGBE=y
CONFIG_NET_XGENE=y
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ASIX is not set
CONFIG_ATL1C=m
CONFIG_BCMGENET=m
CONFIG_BNX2X=m
CONFIG_SYSTEMPORT=m
CONFIG_MACB=y
CONFIG_THUNDER_NIC_PF=y
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_DAVICOM is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
CONFIG_FEC=y
CONFIG_FSL_FMAN=y
CONFIG_FSL_DPAA_ETH=y
@@ -367,16 +385,21 @@ CONFIG_NXP_ENETC4=m
CONFIG_FSL_ENETC_VF=y
CONFIG_FSL_ENETC_QOS=y
CONFIG_NXP_NETC_BLK_CTRL=m
+# CONFIG_NET_VENDOR_FUNGIBLE is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
CONFIG_HIX5HD2_GMAC=y
CONFIG_HNS_DSAF=y
CONFIG_HNS_ENET=y
CONFIG_HNS3=y
CONFIG_HNS3_HCLGE=y
CONFIG_HNS3_ENET=y
+# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_IGB=y
CONFIG_IGBVF=y
+# CONFIG_NET_VENDOR_ADI is not set
+# CONFIG_NET_VENDOR_LITEX is not set
CONFIG_MVNETA=y
CONFIG_MVPP2=y
CONFIG_SKY2=y
@@ -385,13 +408,34 @@ CONFIG_NET_MEDIATEK_STAR_EMAC=m
CONFIG_MLX4_EN=m
CONFIG_MLX5_CORE=m
CONFIG_MLX5_CORE_EN=y
+# CONFIG_NET_VENDOR_META is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_MUCSE is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_QCOM_EMAC=m
CONFIG_RMNET=m
+# CONFIG_NET_VENDOR_RDC is not set
CONFIG_R8169=m
CONFIG_SH_ETH=y
CONFIG_RAVB=y
CONFIG_RENESAS_ETHER_SWITCH=y
CONFIG_RTSN=y
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
CONFIG_SNI_AVE=y
@@ -399,8 +443,15 @@ CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_MEDIATEK=m
CONFIG_DWMAC_TEGRA=m
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
CONFIG_TI_K3_AM65_CPSW_NUSS=y
CONFIG_TI_ICSSG_PRUETH=m
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WANGXUN is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_XILINX_AXI_EMAC=m
CONFIG_QCOM_IPA=m
CONFIG_MESON_GXL_PHY=m
--
2.51.0
^ permalink raw reply related
* [PATCH 5/6] arm64: defconfig: Drop AMD XGBE Ethernet driver
From: Krzysztof Kozlowski @ 2026-04-12 16:21 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260412-defconfig-v1-0-a46918286451@oss.qualcomm.com>
AMD XGBE Ethernet driver was enabled for KVM/QEMU, but QEMU dropped
support for it in v10.2. Driver probably is not used on any other
arm64 platforms, at least ones not being used for development with
defconfig.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 79f6294fffdf..63d4a0f2e388 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -356,7 +356,7 @@ CONFIG_NET_DSA_MSCC_FELIX=m
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALLWINNER is not set
CONFIG_ENA_ETHERNET=m
-CONFIG_AMD_XGBE=y
+# CONFIG_NET_VENDOR_AMD is not set
CONFIG_NET_XGENE=y
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
--
2.51.0
^ permalink raw reply related
* [PATCH 6/6] arm64: defconfig: Switch Ethernet drivers to modules
From: Krzysztof Kozlowski @ 2026-04-12 16:21 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260412-defconfig-v1-0-a46918286451@oss.qualcomm.com>
Development of Linux kernel progressed over last 10 years and it is easy
to generate now initramfs for building own kernel, e.g. with Yocto or
mkosi. Therefore for a few years of reviews on mailing lists, all new
options enabled in arm64 defconfig were with assumption of having
initramfs which can load bare minimum of modules to mount filesystem
from network or disk. Basically network driver as built-in is not
anymore essential to boot the system, so switch almost all Ethernet
drivers to modules to save on kernel image size.
Similarly 9P network filesystem for QEMU, especially that testing kernel
unuder QEMU does not have any size or build process constraints and can
use initramfs with -initrd argument.
Notable exceptions / diff explanations:
1. Intel CONFIG_IGB stays as built-in, because of dependency on I2C
which is also built-in.
2. CONFIG_BCM4908_ENET and CONFIG_BCMASP appear in the diff, because
they were default=y (via ARCH_BCMBCA or ARCH_BCM_IPROC).
3. CONFIG_HNS3_HCLGE and CONFIG_HNS3_ENET are removed, because they are
default=m.
Moving code to modules has positive impact on kernel image size, thus
boot time of all users not using above drivers and ability to flash
fixed-size boot partitions.
Old Image size: 41.11 MiB (Image.gz: 14.69 MiB)
New Image size: 39.14 MiB (Image.gz: 13.82 MiB)
bloat-o-meter of vmlinux:
add/remove: 4/6139 grow/shrink: 3/51 up/down: 34547/-2046619 (-2012072)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 67 ++++++++++++++++++++++----------------------
1 file changed, 34 insertions(+), 33 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 63d4a0f2e388..7d82e90b0405 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -199,8 +199,8 @@ CONFIG_MAC80211=m
CONFIG_MAC80211_LEDS=y
CONFIG_RFKILL=m
CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=y
-CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_9P=m
+CONFIG_NET_9P_VIRTIO=m
CONFIG_NFC=m
CONFIG_NFC_NCI=m
CONFIG_NFC_NXP_NCI=m
@@ -362,11 +362,14 @@ CONFIG_NET_XGENE=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ASIX is not set
CONFIG_ATL1C=m
+CONFIG_BCM4908_ENET=m
CONFIG_BCMGENET=m
CONFIG_BNX2X=m
+CONFIG_BGMAC_PLATFORM=m
CONFIG_SYSTEMPORT=m
-CONFIG_MACB=y
-CONFIG_THUNDER_NIC_PF=y
+CONFIG_BCMASP=m
+CONFIG_MACB=m
+CONFIG_THUNDER_NIC_PF=m
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
@@ -376,33 +379,31 @@ CONFIG_THUNDER_NIC_PF=y
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_ENGLEDER is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
-CONFIG_FEC=y
-CONFIG_FSL_FMAN=y
-CONFIG_FSL_DPAA_ETH=y
-CONFIG_FSL_DPAA2_ETH=y
-CONFIG_FSL_ENETC=y
+CONFIG_FEC=m
+CONFIG_FSL_FMAN=m
+CONFIG_FSL_DPAA_ETH=m
+CONFIG_FSL_DPAA2_ETH=m
+CONFIG_FSL_ENETC=m
CONFIG_NXP_ENETC4=m
-CONFIG_FSL_ENETC_VF=y
+CONFIG_FSL_ENETC_VF=m
CONFIG_FSL_ENETC_QOS=y
CONFIG_NXP_NETC_BLK_CTRL=m
# CONFIG_NET_VENDOR_FUNGIBLE is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
-CONFIG_HIX5HD2_GMAC=y
-CONFIG_HNS_DSAF=y
-CONFIG_HNS_ENET=y
-CONFIG_HNS3=y
-CONFIG_HNS3_HCLGE=y
-CONFIG_HNS3_ENET=y
+CONFIG_HIX5HD2_GMAC=m
+CONFIG_HNS_DSAF=m
+CONFIG_HNS_ENET=m
+CONFIG_HNS3=m
# CONFIG_NET_VENDOR_HUAWEI is not set
-CONFIG_E1000=y
-CONFIG_E1000E=y
+CONFIG_E1000=m
+CONFIG_E1000E=m
CONFIG_IGB=y
-CONFIG_IGBVF=y
+CONFIG_IGBVF=m
# CONFIG_NET_VENDOR_ADI is not set
# CONFIG_NET_VENDOR_LITEX is not set
-CONFIG_MVNETA=y
-CONFIG_MVPP2=y
-CONFIG_SKY2=y
+CONFIG_MVNETA=m
+CONFIG_MVPP2=m
+CONFIG_SKY2=m
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_MEDIATEK_STAR_EMAC=m
CONFIG_MLX4_EN=m
@@ -426,27 +427,27 @@ CONFIG_QCOM_EMAC=m
CONFIG_RMNET=m
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_R8169=m
-CONFIG_SH_ETH=y
-CONFIG_RAVB=y
-CONFIG_RENESAS_ETHER_SWITCH=y
-CONFIG_RTSN=y
+CONFIG_SH_ETH=m
+CONFIG_RAVB=m
+CONFIG_RENESAS_ETHER_SWITCH=m
+CONFIG_RTSN=m
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
-CONFIG_SMC91X=y
-CONFIG_SMSC911X=y
-CONFIG_SNI_AVE=y
-CONFIG_SNI_NETSEC=y
+CONFIG_SMC91X=m
+CONFIG_SMSC911X=m
+CONFIG_SNI_AVE=m
+CONFIG_SNI_NETSEC=m
CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_MEDIATEK=m
CONFIG_DWMAC_TEGRA=m
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
-CONFIG_TI_K3_AM65_CPSW_NUSS=y
+CONFIG_TI_K3_AM65_CPSW_NUSS=m
CONFIG_TI_ICSSG_PRUETH=m
# CONFIG_NET_VENDOR_VERTEXCOM is not set
# CONFIG_NET_VENDOR_VIA is not set
@@ -479,7 +480,7 @@ CONFIG_CAN_M_CAN_PLATFORM=m
CONFIG_CAN_RCAR=m
CONFIG_CAN_RCAR_CANFD=m
CONFIG_CAN_MCP251XFD=m
-CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_GPIO=m
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_USB_PEGASUS=m
@@ -1955,7 +1956,7 @@ CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
-CONFIG_9P_FS=y
+CONFIG_9P_FS=m
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
--
2.51.0
^ permalink raw reply related
* [PATCH 1/5] dt-bindings: interrupt-controller: Add support for secure donated SGIs
From: Sudeep Holla @ 2026-04-12 17:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Marc Zyngier,
devicetree, linux-kernel, linux-arm-kernel, Sudeep Holla
In-Reply-To: <20260412-b4-ffa_ns_sgi_gicv3-v1-0-af61243eb405@kernel.org>
In GICv3, SGI security is defined by interrupt grouping and configuration
rather than by SGI number alone. Linux conventionally reserves SGIs 0-7
for non-secure internal kernel IPIs, while higher SGIs is assumed to be
owned/stolen by the Secure world unless explicitly made available.
Document secure donated SGI interrupt specifiers for the GICv3 binding.
It describes "arm,secure-donated-ns-sgi-ranges" for SGIs donated by the
secure world to non-secure software. It excludes SGIs 0-7, which are
already used by the kernel for internal IPI purposes.
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
---
.../bindings/interrupt-controller/arm,gic-v3.yaml | 27 +++++++++++++++++++++-
include/dt-bindings/interrupt-controller/arm-gic.h | 1 +
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
index bfd30aae682b..664727d071c9 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -45,17 +45,24 @@ description: |
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
interrupts, 2 for interrupts in the Extended SPI range, 3 for the
- Extended PPI range. Other values are reserved for future use.
+ Extended PPI range, and 4 for SGI interrupts. Other values are
+ reserved for future use.
The 2nd cell contains the interrupt number for the interrupt type.
SPI interrupts are in the range [0-987]. PPI interrupts are in the
range [0-15]. Extended SPI interrupts are in the range [0-1023].
Extended PPI interrupts are in the range [0-127].
+ SGI interrupts are in the range [8-15] which overlaps with the SGIs
+ assigned to/reserved for the secure world but donated to the non
+ secure world to use. Refer "arm,secure-donated-ns-sgi-ranges" for
+ more details.
+
The 3rd cell is the flags, encoded as follows:
bits[3:0] trigger type and level flags.
1 = edge triggered
4 = level triggered
+ SGIs are edge triggered and must be described as such.
The 4th cell is a phandle to a node describing a set of CPUs this
interrupt is affine to. The interrupt must be a PPI, and the node
@@ -136,6 +143,24 @@ description: |
- $ref: /schemas/types.yaml#/definitions/uint32
- $ref: /schemas/types.yaml#/definitions/uint64
+ arm,secure-donated-ns-sgi-ranges:
+ description:
+ A list of pairs <sgi span>, where "sgi" is the first SGI INTID of a
+ range donated by the secure side to non-secure software, and "span" is
+ the size of that range. Multiple ranges can be provided.
+
+ SGIs described by interrupt specifiers with type 4 (SGI) must fall
+ within one of these ranges. SGIs(0-7) reserved by non-secure world
+ for internal IPIs must not be listed here. "sgi" must be in the
+ range [8-15], "span" must be in the range [1-8], and the range must
+ not extend past SGI 15.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ - minimum: 8
+ maximum: 15
+ - minimum: 1
+ maximum: 8
+
ppi-partitions:
type: object
additionalProperties: false
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index 887f53363e8a..52c2f3f090c5 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -14,6 +14,7 @@
#define GIC_PPI 1
#define GIC_ESPI 2
#define GIC_EPPI 3
+#define GIC_SGI 4
/*
* Interrupt specifier cell 2.
--
2.43.0
^ permalink raw reply related
* [PATCH 0/5] firmware/irqchip: Add FF-A DT interrupt support for donated NS SGIs
From: Sudeep Holla @ 2026-04-12 17:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Marc Zyngier,
devicetree, linux-kernel, linux-arm-kernel, Sudeep Holla
Hi all,
This series wires FF-A notification interrupts up through DT using the
standard interrupts property on the arm,ffa node and adds the
required GICv3 and binding support for secure-donated non-secure SGIs.
This has been long pending after the discussions here[1][2]. I have been
waiting for some ACPI story to shape up for almost an year now, but no
progress there. So posting this for now to start discussion on the approach
taken here instead of waiting for another year to sort out ACPI 😉.
It:
- documents secure-donated NS SGIs in the GIC DT binding
- teaches the GICv3 driver to accept and map those SGIs
- adds a DT binding for the arm,ffa firmware node
- updates the FF-A driver to use the arm,ffa node interrupt instead of
synthesizing its own GIC mapping
- adds an FVP DT node using SGI 8 as the FF-A notification interrupt
The FF-A DT lookup expects a single interrupt entry, verifies that it is
a per-CPU interrupt via the reported affinity mask, and cross-checks the
resolved Linux IRQ hwirq against the interrupt ID returned by
FFA_FEATURES.
[1] https://lore.kernel.org/all/86plqayvu6.wl-maz@kernel.org/
[2] https://lore.kernel.org/all/86zfpgztmt.wl-maz@kernel.org/
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
---
Sudeep Holla (5):
dt-bindings: interrupt-controller: Add support for secure donated SGIs
irqchip/gic-v3: Support secure-donated non-secure SGIs
dt-bindings: firmware: Add Arm FF-A binding
firmware: arm_ffa: Use device node interrupts property for IRQ lookup
arm64: dts: arm: fvp-base-revc: Add FF-A notification interrupt
.../devicetree/bindings/firmware/arm,ffa.yaml | 42 +++++++++++
.../bindings/interrupt-controller/arm,gic-v3.yaml | 27 ++++++-
arch/arm64/boot/dts/arm/fvp-base-revc.dts | 6 ++
drivers/firmware/arm_ffa/driver.c | 53 +++++++++----
drivers/irqchip/irq-gic-v3.c | 86 ++++++++++++++++++++++
include/dt-bindings/interrupt-controller/arm-gic.h | 1 +
6 files changed, 201 insertions(+), 14 deletions(-)
---
base-commit: f5459048c38a00fc583658d6dcd0f894aff6df8f
change-id: 20260412-b4-ffa_ns_sgi_gicv3-ede4dfe9d76e
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH 2/5] irqchip/gic-v3: Support secure-donated non-secure SGIs
From: Sudeep Holla @ 2026-04-12 17:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Marc Zyngier,
devicetree, linux-kernel, linux-arm-kernel, Sudeep Holla
In-Reply-To: <20260412-b4-ffa_ns_sgi_gicv3-v1-0-af61243eb405@kernel.org>
Parse secure-donated SGI ranges from the firmware, reject invalid
interrupt specifiers, and allow devicetree consumers to map only the
SGIs explicitly donated by the secure side to non-secure software.
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
---
drivers/irqchip/irq-gic-v3.c | 86 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 20f13b686ab2..cc7720d9fb0e 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -35,6 +35,8 @@
#include <asm/smp_plat.h>
#include <asm/virt.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
#include "irq-gic-common.h"
static u8 dist_prio_irq __ro_after_init = GICV3_PRIO_IRQ;
@@ -65,6 +67,7 @@ struct gic_chip_data {
u64 flags;
bool has_rss;
unsigned int ppi_nr;
+ u16 donated_sgi_mask;
struct partition_affinity *parts;
unsigned int nr_parts;
};
@@ -95,6 +98,7 @@ static bool nmi_support_forbidden;
* with hwirq IDs, is simplified by accounting for all 16.
*/
#define SGI_NR 16
+#define GIC_SGI_IPI_NR 8
/*
* The behaviours of RPR and PMR registers differ depending on the value of
@@ -119,6 +123,74 @@ static bool nmi_support_forbidden;
*/
static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
+static bool gic_sgi_is_donated_to_ns(unsigned int sgi)
+{
+ return sgi < SGI_NR && (gic_data.donated_sgi_mask & BIT(sgi));
+}
+
+static int __init gic_of_init_donated_sgi_ranges(struct device_node *node)
+{
+ const char *propname = "arm,secure-donated-ns-sgi-ranges";
+ int count, i;
+ u32 *ranges;
+ u16 mask = 0;
+
+ count = of_property_count_u32_elems(node, propname);
+ if (count < 0) {
+ if (count == -EINVAL)
+ return 0;
+
+ pr_err("%pOF: unable to read %s\n", node, propname);
+ return count;
+ }
+
+ if (!count)
+ return 0;
+
+ if (count % 2) {
+ pr_err("%pOF: %s must contain <sgi span> pairs\n",
+ node, propname);
+ return -EINVAL;
+ }
+
+ ranges = kcalloc(count, sizeof(*ranges), GFP_KERNEL);
+ if (!ranges)
+ return -ENOMEM;
+
+ if (of_property_read_u32_array(node, propname, ranges, count)) {
+ pr_err("%pOF: unable to read %s\n", node, propname);
+ kfree(ranges);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < count; i += 2) {
+ u32 sgi = ranges[i];
+ u32 span = ranges[i + 1];
+ u32 end;
+
+ if (sgi < GIC_SGI_IPI_NR || sgi >= SGI_NR || !span || span > 8) {
+ pr_err("%pOF: invalid SGI range <%u %u> in %s\n",
+ node, sgi, span, propname);
+ kfree(ranges);
+ return -EINVAL;
+ }
+
+ end = sgi + span;
+ if (end > SGI_NR) {
+ pr_err("%pOF: SGI range <%u %u> exceeds SGI space in %s\n",
+ node, sgi, span, propname);
+ kfree(ranges);
+ return -EINVAL;
+ }
+
+ mask |= GENMASK(end - 1, sgi);
+ }
+
+ kfree(ranges);
+ gic_data.donated_sgi_mask = mask;
+ return 0;
+}
+
static u32 gic_get_pribits(void)
{
u32 pribits;
@@ -1614,6 +1686,12 @@ static int gic_irq_domain_translate(struct irq_domain *d,
case 3: /* EPPI */
*hwirq = fwspec->param[1] + EPPI_BASE_INTID;
break;
+ case GIC_SGI: /* SGI */
+ if (!gic_sgi_is_donated_to_ns(fwspec->param[1]))
+ return -EINVAL;
+
+ *hwirq = fwspec->param[1];
+ break;
case GIC_IRQ_TYPE_LPI: /* LPI */
*hwirq = fwspec->param[1];
break;
@@ -1623,6 +1701,10 @@ static int gic_irq_domain_translate(struct irq_domain *d,
*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
+ if (fwspec->param[0] == GIC_SGI &&
+ *type != IRQ_TYPE_EDGE_RISING)
+ return -EINVAL;
+
/*
* Make it clear that broken DTs are... broken.
*/
@@ -2239,6 +2321,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
gic_enable_of_quirks(node, gic_quirks, &gic_data);
+ err = gic_of_init_donated_sgi_ranges(node);
+ if (err)
+ goto out_unmap_rdist;
+
err = gic_init_bases(dist_phys_base, dist_base, rdist_regs,
nr_redist_regions, redist_stride, &node->fwnode);
if (err)
--
2.43.0
^ permalink raw reply related
* [PATCH 3/5] dt-bindings: firmware: Add Arm FF-A binding
From: Sudeep Holla @ 2026-04-12 17:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Marc Zyngier,
devicetree, linux-kernel, linux-arm-kernel, Sudeep Holla
In-Reply-To: <20260412-b4-ffa_ns_sgi_gicv3-v1-0-af61243eb405@kernel.org>
Document the FF-A firmware device node.
Describes the "arm,ffa" compatible and requires the standard interrupts
property.
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
---
.../devicetree/bindings/firmware/arm,ffa.yaml | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/arm,ffa.yaml b/Documentation/devicetree/bindings/firmware/arm,ffa.yaml
new file mode 100644
index 000000000000..150f394b3327
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/arm,ffa.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/arm,ffa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm Firmware Framework for A-profile
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@kernel.org>
+
+description: |
+ Arm Firmware Framework for A-profile (FF-A) firmware device node
+ describing the notification interrupt exposed to the normal world.
+
+properties:
+ $nodename:
+ const: ffa
+
+ compatible:
+ const: arm,ffa
+
+ interrupts:
+ description:
+ Per-CPU notification interrupt used by the normal world FF-A partition.
+ maxItems: 1
+
+required:
+ - compatible
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ ffa {
+ compatible = "arm,ffa";
+ interrupts = <GIC_SGI 8 IRQ_TYPE_EDGE_RISING>;
+ };
--
2.43.0
^ permalink raw reply related
* [PATCH 4/5] firmware: arm_ffa: Use device node interrupts property for IRQ lookup
From: Sudeep Holla @ 2026-04-12 17:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Marc Zyngier,
devicetree, linux-kernel, linux-arm-kernel, Sudeep Holla
In-Reply-To: <20260412-b4-ffa_ns_sgi_gicv3-v1-0-af61243eb405@kernel.org>
Use the standard interrupts property from the arm,ffa node instead of
synthesizing a GIC mapping directly.
Requires the "arm,ffa" device node to describe exactly one interrupt,
validate that its affinity spans cpu_possible_mask so the interrupt is
per-CPU, and then cross-check the mapped hwirq against the interrupt
ID returned by FFA_FEATURES.
This removes the FF-A driver's direct arm,gic-v3 lookup and raw
irq_create_of_mapping() usage while still keeping the DT description in
sync with the firmware-reported interrupt.
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
---
drivers/firmware/arm_ffa/driver.c | 53 +++++++++++++++++++++++++++++----------
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c
index f2f94d4d533e..7a3800a55dc1 100644
--- a/drivers/firmware/arm_ffa/driver.c
+++ b/drivers/firmware/arm_ffa/driver.c
@@ -1821,6 +1821,45 @@ static void ffa_sched_recv_irq_work_fn(struct work_struct *work)
ffa_notification_info_get();
}
+static int ffa_dt_map_irq(int intid)
+{
+ struct device_node *ffa __free(device_node) = NULL;
+ const struct cpumask *affinity;
+ struct irq_data *irqd;
+ int count, irq;
+
+ ffa = of_find_compatible_node(NULL, NULL, "arm,ffa");
+ if (!ffa)
+ return -ENXIO;
+
+ count = of_irq_count(ffa);
+ if (count <= 0)
+ return count ? count : -ENXIO;
+
+ if (count != 1) {
+ pr_err("FF-A currently supports exactly one interrupt\n");
+ return -EINVAL;
+ }
+
+ affinity = of_irq_get_affinity(ffa, 0);
+ if (!affinity || !cpumask_equal(affinity, cpu_possible_mask)) {
+ pr_err("FF-A currently supports only SGIs/PPIs\n");
+ return -EINVAL;
+ }
+
+ irq = of_irq_get(ffa, 0);
+ if (irq <= 0)
+ return irq ? irq : -ENXIO;
+
+ irqd = irq_get_irq_data(irq);
+ if (!irqd || irqd_to_hwirq(irqd) != intid) {
+ irq_dispose_mapping(irq);
+ return -EINVAL;
+ }
+
+ return irq;
+}
+
static int ffa_irq_map(u32 id)
{
char *err_str;
@@ -1842,19 +1881,7 @@ static int ffa_irq_map(u32 id)
}
if (acpi_disabled) {
- struct of_phandle_args oirq = {};
- struct device_node *gic;
-
- /* Only GICv3 supported currently with the device tree */
- gic = of_find_compatible_node(NULL, NULL, "arm,gic-v3");
- if (!gic)
- return -ENXIO;
-
- oirq.np = gic;
- oirq.args_count = 1;
- oirq.args[0] = intid;
- irq = irq_create_of_mapping(&oirq);
- of_node_put(gic);
+ irq = ffa_dt_map_irq(intid);
#ifdef CONFIG_ACPI
} else {
irq = acpi_register_gsi(NULL, intid, ACPI_EDGE_SENSITIVE,
--
2.43.0
^ permalink raw reply related
* [PATCH 5/5] arm64: dts: arm: fvp-base-revc: Add FF-A notification interrupt
From: Sudeep Holla @ 2026-04-12 17:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Marc Zyngier,
devicetree, linux-kernel, linux-arm-kernel, Sudeep Holla
In-Reply-To: <20260412-b4-ffa_ns_sgi_gicv3-v1-0-af61243eb405@kernel.org>
Add an arm,ffa firmware node describing the FF-A notification
interrupt on SGI 8.
Also mark SGI 8 as donated to the non-secure world in the GICv3
node so the interrupt specifier is accepted by the donated-SGI DT
support.
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
---
arch/arm64/boot/dts/arm/fvp-base-revc.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
index 68a69f17e93d..87189b32e38d 100644
--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -40,6 +40,11 @@ psci {
method = "smc";
};
+ ffa {
+ compatible = "arm,ffa";
+ interrupts = <GIC_SGI 8 IRQ_TYPE_EDGE_RISING>;
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -224,6 +229,7 @@ gic: interrupt-controller@2f000000 {
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
+ arm,secure-donated-ns-sgi-ranges = <8 1>;
ranges;
interrupt-controller;
reg = <0x0 0x2f000000 0 0x10000>, // GICD
--
2.43.0
^ permalink raw reply related
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