* [PATCH v6 10/19] dmaengine: ti: k3-udma: refactor resource setup functions
From: Sai Sree Kartheek Adivi @ 2026-04-28 8:51 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, vigneshr,
Frank.li, s-adivi
Cc: r-sharma3, gehariprasath
In-Reply-To: <20260428085202.1724548-1-s-adivi@ti.com>
The implementation of setup_resources, bcdma_setup_resources and
pktdma_setup_resources is largely shared between all K3 UDMA variants
with the only major difference being SCI resources setup. So,
- Move the functions to k3-udma-common.c.
- Split SCI resource setup for bcdma and pktdma into separate functions
in variant specific driver (k3-udma.c).
- Add function pointers for setup_sci_resources in udma_dev and call
them as part of the actual resource setup implementations in
k3-udma-common.c to retain the existing functionality.
- Also since setup_resources call udma_setup_resources which is not
required for all K3 UDMA variants, Add a function pointer in udma_dev
and use that to call udma_setup_resources.
This refactor improves code reuse and maintainability across multiple
variants.
No functional changes intended.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/k3-udma-common.c | 204 ++++++++++++++++++++++++++++++++
drivers/dma/ti/k3-udma.c | 182 +---------------------------
drivers/dma/ti/k3-udma.h | 8 ++
3 files changed, 218 insertions(+), 176 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index 882d27b3c9ee5..b419b23c401a1 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -8,7 +8,9 @@
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/soc/ti/ti_sci_inta_msi.h>
#include <linux/soc/ti/k3-ringacc.h>
#include "k3-udma.h"
@@ -2333,5 +2335,207 @@ void bcdma_free_bchan_resources(struct udma_chan *uc)
}
EXPORT_SYMBOL_GPL(bcdma_free_bchan_resources);
+int bcdma_setup_resources(struct udma_dev *ud)
+{
+ int ret;
+ struct device *dev = ud->dev;
+ u32 cap;
+
+ /* Set up the throughput level start indexes */
+ cap = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+ if (BCDMA_CAP3_UBCHAN_CNT(cap)) {
+ ud->bchan_tpl.levels = 3;
+ ud->bchan_tpl.start_idx[1] = BCDMA_CAP3_UBCHAN_CNT(cap);
+ ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap);
+ } else if (BCDMA_CAP3_HBCHAN_CNT(cap)) {
+ ud->bchan_tpl.levels = 2;
+ ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap);
+ } else {
+ ud->bchan_tpl.levels = 1;
+ }
+
+ cap = udma_read(ud->mmrs[MMR_GCFG], 0x30);
+ if (BCDMA_CAP4_URCHAN_CNT(cap)) {
+ ud->rchan_tpl.levels = 3;
+ ud->rchan_tpl.start_idx[1] = BCDMA_CAP4_URCHAN_CNT(cap);
+ ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap);
+ } else if (BCDMA_CAP4_HRCHAN_CNT(cap)) {
+ ud->rchan_tpl.levels = 2;
+ ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap);
+ } else {
+ ud->rchan_tpl.levels = 1;
+ }
+
+ if (BCDMA_CAP4_UTCHAN_CNT(cap)) {
+ ud->tchan_tpl.levels = 3;
+ ud->tchan_tpl.start_idx[1] = BCDMA_CAP4_UTCHAN_CNT(cap);
+ ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap);
+ } else if (BCDMA_CAP4_HTCHAN_CNT(cap)) {
+ ud->tchan_tpl.levels = 2;
+ ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap);
+ } else {
+ ud->tchan_tpl.levels = 1;
+ }
+
+ ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
+ GFP_KERNEL);
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ /* BCDMA do not really have flows, but the driver expect it */
+ ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+
+ if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
+ !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans ||
+ !ud->rflows)
+ return -ENOMEM;
+
+ if (ud->bcdma_setup_sci_resources) {
+ ret = ud->bcdma_setup_sci_resources(ud);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int pktdma_setup_resources(struct udma_dev *ud)
+{
+ int ret;
+ struct device *dev = ud->dev;
+ u32 cap3;
+
+ /* Set up the throughput level start indexes */
+ cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+ if (UDMA_CAP3_UCHAN_CNT(cap3)) {
+ ud->tchan_tpl.levels = 3;
+ ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3);
+ ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
+ } else if (UDMA_CAP3_HCHAN_CNT(cap3)) {
+ ud->tchan_tpl.levels = 2;
+ ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
+ } else {
+ ud->tchan_tpl.levels = 1;
+ }
+
+ ud->rchan_tpl.levels = ud->tchan_tpl.levels;
+ ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0];
+ ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1];
+
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
+ sizeof(unsigned long),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+ ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+
+ if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
+ !ud->rchans || !ud->rflows || !ud->rflow_in_use)
+ return -ENOMEM;
+
+ if (ud->pktdma_setup_sci_resources) {
+ ret = ud->pktdma_setup_sci_resources(ud);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int setup_resources(struct udma_dev *ud)
+{
+ struct device *dev = ud->dev;
+ int ch_count, ret;
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ret = ud->udma_setup_resources(ud);
+ break;
+ case DMA_TYPE_BCDMA:
+ ret = bcdma_setup_resources(ud);
+ break;
+ case DMA_TYPE_PKTDMA:
+ ret = pktdma_setup_resources(ud);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (ret)
+ return ret;
+
+ ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
+ if (ud->bchan_cnt)
+ ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
+ ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
+ ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
+ if (!ch_count)
+ return -ENODEV;
+
+ ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
+ GFP_KERNEL);
+ if (!ud->channels)
+ return -ENOMEM;
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ dev_info(dev,
+ "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
+ ch_count,
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt),
+ ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map,
+ ud->rflow_cnt));
+ break;
+ case DMA_TYPE_BCDMA:
+ dev_info(dev,
+ "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
+ ch_count,
+ ud->bchan_cnt - bitmap_weight(ud->bchan_map,
+ ud->bchan_cnt),
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt));
+ break;
+ case DMA_TYPE_PKTDMA:
+ dev_info(dev,
+ "Channels: %d (tchan: %u, rchan: %u)\n",
+ ch_count,
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt));
+ break;
+ default:
+ break;
+ }
+
+ return ch_count;
+}
+EXPORT_SYMBOL_GPL(setup_resources);
+
MODULE_DESCRIPTION("Texas Instruments K3 UDMA Common Library");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 753acf1e13fa2..d9d6cbda46b2c 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -2083,7 +2083,7 @@ static const char * const range_names[] = {
[RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow",
};
-static int udma_setup_resources(struct udma_dev *ud)
+int udma_setup_resources(struct udma_dev *ud)
{
int ret, i, j;
struct device *dev = ud->dev;
@@ -2245,74 +2245,13 @@ static int udma_setup_resources(struct udma_dev *ud)
return 0;
}
-static int bcdma_setup_resources(struct udma_dev *ud)
+static int bcdma_setup_sci_resources(struct udma_dev *ud)
{
int ret, i, j;
struct device *dev = ud->dev;
struct ti_sci_resource *rm_res, irq_res;
struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
const struct udma_oes_offsets *oes = &ud->soc_data->oes;
- u32 cap;
-
- /* Set up the throughput level start indexes */
- cap = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
- if (BCDMA_CAP3_UBCHAN_CNT(cap)) {
- ud->bchan_tpl.levels = 3;
- ud->bchan_tpl.start_idx[1] = BCDMA_CAP3_UBCHAN_CNT(cap);
- ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap);
- } else if (BCDMA_CAP3_HBCHAN_CNT(cap)) {
- ud->bchan_tpl.levels = 2;
- ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap);
- } else {
- ud->bchan_tpl.levels = 1;
- }
-
- cap = udma_read(ud->mmrs[MMR_GCFG], 0x30);
- if (BCDMA_CAP4_URCHAN_CNT(cap)) {
- ud->rchan_tpl.levels = 3;
- ud->rchan_tpl.start_idx[1] = BCDMA_CAP4_URCHAN_CNT(cap);
- ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap);
- } else if (BCDMA_CAP4_HRCHAN_CNT(cap)) {
- ud->rchan_tpl.levels = 2;
- ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap);
- } else {
- ud->rchan_tpl.levels = 1;
- }
-
- if (BCDMA_CAP4_UTCHAN_CNT(cap)) {
- ud->tchan_tpl.levels = 3;
- ud->tchan_tpl.start_idx[1] = BCDMA_CAP4_UTCHAN_CNT(cap);
- ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap);
- } else if (BCDMA_CAP4_HTCHAN_CNT(cap)) {
- ud->tchan_tpl.levels = 2;
- ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap);
- } else {
- ud->tchan_tpl.levels = 1;
- }
-
- ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
- GFP_KERNEL);
- ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
- GFP_KERNEL);
- ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
- GFP_KERNEL);
- /* BCDMA do not really have flows, but the driver expect it */
- ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
- sizeof(unsigned long),
- GFP_KERNEL);
- ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
- GFP_KERNEL);
-
- if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
- !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans ||
- !ud->rflows)
- return -ENOMEM;
/* Get resource ranges from tisci */
for (i = 0; i < RM_RANGE_LAST; i++) {
@@ -2476,51 +2415,13 @@ static int bcdma_setup_resources(struct udma_dev *ud)
return 0;
}
-static int pktdma_setup_resources(struct udma_dev *ud)
+static int pktdma_setup_sci_resources(struct udma_dev *ud)
{
int ret, i, j;
struct device *dev = ud->dev;
struct ti_sci_resource *rm_res, irq_res;
struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
const struct udma_oes_offsets *oes = &ud->soc_data->oes;
- u32 cap3;
-
- /* Set up the throughput level start indexes */
- cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
- if (UDMA_CAP3_UCHAN_CNT(cap3)) {
- ud->tchan_tpl.levels = 3;
- ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3);
- ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
- } else if (UDMA_CAP3_HCHAN_CNT(cap3)) {
- ud->tchan_tpl.levels = 2;
- ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
- } else {
- ud->tchan_tpl.levels = 1;
- }
-
- ud->rchan_tpl.levels = ud->tchan_tpl.levels;
- ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0];
- ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1];
-
- ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
- GFP_KERNEL);
- ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
- GFP_KERNEL);
- ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
- sizeof(unsigned long),
- GFP_KERNEL);
- ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
- GFP_KERNEL);
- ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
- sizeof(unsigned long), GFP_KERNEL);
-
- if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
- !ud->rchans || !ud->rflows || !ud->rflow_in_use)
- return -ENOMEM;
/* Get resource ranges from tisci */
for (i = 0; i < RM_RANGE_LAST; i++) {
@@ -2631,80 +2532,6 @@ static int pktdma_setup_resources(struct udma_dev *ud)
return 0;
}
-static int setup_resources(struct udma_dev *ud)
-{
- struct device *dev = ud->dev;
- int ch_count, ret;
-
- switch (ud->match_data->type) {
- case DMA_TYPE_UDMA:
- ret = udma_setup_resources(ud);
- break;
- case DMA_TYPE_BCDMA:
- ret = bcdma_setup_resources(ud);
- break;
- case DMA_TYPE_PKTDMA:
- ret = pktdma_setup_resources(ud);
- break;
- default:
- return -EINVAL;
- }
-
- if (ret)
- return ret;
-
- ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
- if (ud->bchan_cnt)
- ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
- ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
- ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
- if (!ch_count)
- return -ENODEV;
-
- ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
- GFP_KERNEL);
- if (!ud->channels)
- return -ENOMEM;
-
- switch (ud->match_data->type) {
- case DMA_TYPE_UDMA:
- dev_info(dev,
- "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
- ch_count,
- ud->tchan_cnt - bitmap_weight(ud->tchan_map,
- ud->tchan_cnt),
- ud->rchan_cnt - bitmap_weight(ud->rchan_map,
- ud->rchan_cnt),
- ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map,
- ud->rflow_cnt));
- break;
- case DMA_TYPE_BCDMA:
- dev_info(dev,
- "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
- ch_count,
- ud->bchan_cnt - bitmap_weight(ud->bchan_map,
- ud->bchan_cnt),
- ud->tchan_cnt - bitmap_weight(ud->tchan_map,
- ud->tchan_cnt),
- ud->rchan_cnt - bitmap_weight(ud->rchan_map,
- ud->rchan_cnt));
- break;
- case DMA_TYPE_PKTDMA:
- dev_info(dev,
- "Channels: %d (tchan: %u, rchan: %u)\n",
- ch_count,
- ud->tchan_cnt - bitmap_weight(ud->tchan_map,
- ud->tchan_cnt),
- ud->rchan_cnt - bitmap_weight(ud->rchan_map,
- ud->rchan_cnt));
- break;
- default:
- break;
- }
-
- return ch_count;
-}
-
static int udma_probe(struct platform_device *pdev)
{
struct device_node *navss_node = pdev->dev.parent->of_node;
@@ -2747,6 +2574,9 @@ static int udma_probe(struct platform_device *pdev)
ud->decrement_byte_counters = udma_decrement_byte_counters;
ud->psil_pair = navss_psil_pair;
ud->psil_unpair = navss_psil_unpair;
+ ud->udma_setup_resources = udma_setup_resources;
+ ud->bcdma_setup_sci_resources = bcdma_setup_sci_resources;
+ ud->pktdma_setup_sci_resources = pktdma_setup_sci_resources;
ret = udma_get_mmrs(pdev, ud);
if (ret)
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index e4b512d9ffb2e..6a95eb1ece064 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -353,6 +353,9 @@ struct udma_dev {
u32 dst_thread);
int (*psil_unpair)(struct udma_dev *ud, u32 src_thread,
u32 dst_thread);
+ int (*udma_setup_resources)(struct udma_dev *ud);
+ int (*bcdma_setup_sci_resources)(struct udma_dev *ud);
+ int (*pktdma_setup_sci_resources)(struct udma_dev *ud);
};
struct udma_desc {
@@ -675,6 +678,11 @@ struct udma_bchan *__udma_reserve_bchan(struct udma_dev *ud, enum udma_tp_level
struct udma_tchan *__udma_reserve_tchan(struct udma_dev *ud, enum udma_tp_level tpl, int id);
struct udma_rchan *__udma_reserve_rchan(struct udma_dev *ud, enum udma_tp_level tpl, int id);
+int udma_setup_resources(struct udma_dev *ud);
+int bcdma_setup_resources(struct udma_dev *ud);
+int pktdma_setup_resources(struct udma_dev *ud);
+int setup_resources(struct udma_dev *ud);
+
/* Direct access to UDMA low lever resources for the glue layer */
int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread);
int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
--
2.53.0
^ permalink raw reply related
* [PATCH v6 15/19] dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data
From: Sai Sree Kartheek Adivi @ 2026-04-28 8:51 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, vigneshr,
Frank.li, s-adivi
Cc: r-sharma3, gehariprasath
In-Reply-To: <20260428085202.1724548-1-s-adivi@ti.com>
Add PSIL and PDMA data for AM62Lx SoC.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/Makefile | 3 +-
drivers/dma/ti/k3-psil-am62l.c | 132 +++++++++++++++++++++++++++++++++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 1 +
4 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/ti/k3-psil-am62l.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 3b91c02e55eaf..41bfba944dc6c 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -14,6 +14,7 @@ k3-psil-lib-objs := k3-psil.o \
k3-psil-am62.o \
k3-psil-am62a.o \
k3-psil-j784s4.o \
- k3-psil-am62p.o
+ k3-psil-am62p.o \
+ k3-psil-am62l.o
obj-$(CONFIG_TI_K3_PSIL) += k3-psil-lib.o
obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o
diff --git a/drivers/dma/ti/k3-psil-am62l.c b/drivers/dma/ti/k3-psil-am62l.c
new file mode 100644
index 0000000000000..45f5aac32f6a0
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am62l.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x, ch) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = ch, \
+ .default_flow_id = -1, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x, ch) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = ch, \
+ .pkt_mode = 1, \
+ .default_flow_id = -1 \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x, ch) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1, \
+ .pdma_burst = 1, \
+ .mapped_channel_id = ch, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am62l_src_ep_map[] = {
+ /* PDMA_MAIN1 - UART0-6 */
+ PSIL_PDMA_XY_PKT(0x4400, 0),
+ PSIL_PDMA_XY_PKT(0x4401, 2),
+ PSIL_PDMA_XY_PKT(0x4402, 4),
+ PSIL_PDMA_XY_PKT(0x4403, 6),
+ PSIL_PDMA_XY_PKT(0x4404, 8),
+ PSIL_PDMA_XY_PKT(0x4405, 10),
+ PSIL_PDMA_XY_PKT(0x4406, 12),
+ /* PDMA_MAIN0 - SPI0 - CH0-3 */
+ PSIL_PDMA_XY_TR(0x4300, 16),
+ /* PDMA_MAIN0 - SPI1 - CH0-3 */
+ PSIL_PDMA_XY_TR(0x4301, 24),
+ /* PDMA_MAIN0 - SPI2 - CH0-3 */
+ PSIL_PDMA_XY_TR(0x4302, 32),
+ /* PDMA_MAIN0 - SPI3 - CH0-3 */
+ PSIL_PDMA_XY_TR(0x4303, 40),
+ /* PDMA_MAIN2 - MCASP0-2 */
+ PSIL_PDMA_MCASP(0x4500, 48),
+ PSIL_PDMA_MCASP(0x4501, 50),
+ PSIL_PDMA_MCASP(0x4502, 52),
+ /* PDMA_MAIN0 - AES */
+ PSIL_PDMA_XY_TR(0x4700, 65),
+ /* PDMA_MAIN0 - ADC */
+ PSIL_PDMA_XY_TR(0x4503, 80),
+ PSIL_PDMA_XY_TR(0x4504, 81),
+ PSIL_ETHERNET(0x4600, 96, 96, 16),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am62l_dst_ep_map[] = {
+ /* PDMA_MAIN1 - UART0-6 */
+ PSIL_PDMA_XY_PKT(0xC400, 1),
+ PSIL_PDMA_XY_PKT(0xC401, 3),
+ PSIL_PDMA_XY_PKT(0xC402, 5),
+ PSIL_PDMA_XY_PKT(0xC403, 7),
+ PSIL_PDMA_XY_PKT(0xC404, 9),
+ PSIL_PDMA_XY_PKT(0xC405, 11),
+ PSIL_PDMA_XY_PKT(0xC406, 13),
+ /* PDMA_MAIN0 - SPI0 - CH0-3 */
+ PSIL_PDMA_XY_TR(0xC300, 17),
+ /* PDMA_MAIN0 - SPI1 - CH0-3 */
+ PSIL_PDMA_XY_TR(0xC301, 25),
+ /* PDMA_MAIN0 - SPI2 - CH0-3 */
+ PSIL_PDMA_XY_TR(0xC302, 33),
+ /* PDMA_MAIN0 - SPI3 - CH0-3 */
+ PSIL_PDMA_XY_TR(0xC303, 41),
+ /* PDMA_MAIN2 - MCASP0-2 */
+ PSIL_PDMA_MCASP(0xC500, 49),
+ PSIL_PDMA_MCASP(0xC501, 51),
+ PSIL_PDMA_MCASP(0xC502, 53),
+ /* PDMA_MAIN0 - SHA */
+ PSIL_PDMA_XY_TR(0xC700, 64),
+ /* PDMA_MAIN0 - AES */
+ PSIL_PDMA_XY_TR(0xC701, 66),
+ /* PDMA_MAIN0 - CRC32 - CH0-1 */
+ PSIL_PDMA_XY_TR(0xC702, 67),
+ /* CPSW3G */
+ PSIL_ETHERNET(0xc600, 64, 64, 2),
+ PSIL_ETHERNET(0xc601, 66, 66, 2),
+ PSIL_ETHERNET(0xc602, 68, 68, 2),
+ PSIL_ETHERNET(0xc603, 70, 70, 2),
+ PSIL_ETHERNET(0xc604, 72, 72, 2),
+ PSIL_ETHERNET(0xc605, 74, 74, 2),
+ PSIL_ETHERNET(0xc606, 76, 76, 2),
+ PSIL_ETHERNET(0xc607, 78, 78, 2),
+};
+
+struct psil_ep_map am62l_ep_map = {
+ .name = "am62l",
+ .src = am62l_src_ep_map,
+ .src_count = ARRAY_SIZE(am62l_src_ep_map),
+ .dst = am62l_dst_ep_map,
+ .dst_count = ARRAY_SIZE(am62l_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index a577be97e3447..961b73df7a6bb 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -46,5 +46,6 @@ extern struct psil_ep_map am62_ep_map;
extern struct psil_ep_map am62a_ep_map;
extern struct psil_ep_map j784s4_ep_map;
extern struct psil_ep_map am62p_ep_map;
+extern struct psil_ep_map am62l_ep_map;
#endif /* K3_PSIL_PRIV_H_ */
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index c4b6f0df46861..2a843f36261bc 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -28,6 +28,7 @@ static const struct soc_device_attribute k3_soc_devices[] = {
{ .family = "J784S4", .data = &j784s4_ep_map },
{ .family = "AM62PX", .data = &am62p_ep_map },
{ .family = "J722S", .data = &am62p_ep_map },
+ { .family = "AM62LX", .data = &am62l_ep_map },
{ /* sentinel */ }
};
--
2.53.0
^ permalink raw reply related
* [PATCH v6 08/19] dmaengine: ti: k3-udma: move udma utility functions to k3-udma-common.c
From: Sai Sree Kartheek Adivi @ 2026-04-28 8:51 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, vigneshr,
Frank.li, s-adivi
Cc: r-sharma3, gehariprasath
In-Reply-To: <20260428085202.1724548-1-s-adivi@ti.com>
Relocate udma utility functions from k3-udma.c to k3-udma-common.c file.
The implementation of these functions is largely shared between K3 UDMA
and K3 UDMA v2. This refactor improves code reuse and maintainability
across multiple variants.
No functional changes intended.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/k3-udma-common.c | 549 ++++++++++++++++++++++++++++++++
drivers/dma/ti/k3-udma.c | 531 ------------------------------
drivers/dma/ti/k3-udma.h | 28 ++
3 files changed, 577 insertions(+), 531 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index 4dcf986f84d87..472eedc4663a9 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -4,6 +4,7 @@
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
+#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
@@ -46,6 +47,28 @@ struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc,
}
EXPORT_SYMBOL_GPL(udma_udma_desc_from_paddr);
+void udma_start_desc(struct udma_chan *uc)
+{
+ struct udma_chan_config *ucc = &uc->config;
+
+ if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode &&
+ (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) {
+ int i;
+
+ /*
+ * UDMA only: Push all descriptors to ring for packet mode
+ * cyclic or RX
+ * PKTDMA supports pre-linked descriptor and cyclic is not
+ * supported
+ */
+ for (i = 0; i < uc->desc->sglen; i++)
+ udma_push_to_ring(uc, i);
+ } else {
+ udma_push_to_ring(uc, 0);
+ }
+}
+EXPORT_SYMBOL_GPL(udma_start_desc);
+
void udma_free_hwdesc(struct udma_chan *uc, struct udma_desc *d)
{
if (uc->use_dma_pool) {
@@ -1342,5 +1365,531 @@ void udma_reset_rings(struct udma_chan *uc)
}
EXPORT_SYMBOL_GPL(udma_reset_rings);
+u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id)
+{
+ int i;
+
+ for (i = 0; i < tpl_map->levels; i++) {
+ if (chan_id >= tpl_map->start_idx[i])
+ return i;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(udma_get_chan_tpl_index);
+
+void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel)
+{
+ struct device *chan_dev = &chan->dev->device;
+
+ if (asel == 0) {
+ /* No special handling for the channel */
+ chan->dev->chan_dma_dev = false;
+
+ chan_dev->dma_coherent = false;
+ chan_dev->dma_parms = NULL;
+ } else if (asel == 14 || asel == 15) {
+ chan->dev->chan_dma_dev = true;
+
+ chan_dev->dma_coherent = true;
+ dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48));
+ chan_dev->dma_parms = chan_dev->parent->dma_parms;
+ } else {
+ dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel);
+
+ chan_dev->dma_coherent = false;
+ chan_dev->dma_parms = NULL;
+ }
+}
+EXPORT_SYMBOL_GPL(k3_configure_chan_coherency);
+
+void udma_reset_uchan(struct udma_chan *uc)
+{
+ memset(&uc->config, 0, sizeof(uc->config));
+ uc->config.remote_thread_id = -1;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+ uc->state = UDMA_CHAN_IS_IDLE;
+}
+EXPORT_SYMBOL_GPL(udma_reset_uchan);
+
+void udma_dump_chan_stdata(struct udma_chan *uc)
+{
+ struct device *dev = uc->ud->dev;
+ u32 offset;
+ int i;
+
+ if (uc->config.dir == DMA_MEM_TO_DEV || uc->config.dir == DMA_MEM_TO_MEM) {
+ dev_dbg(dev, "TCHAN State data:\n");
+ for (i = 0; i < 32; i++) {
+ offset = UDMA_CHAN_RT_STDATA_REG + i * 4;
+ dev_dbg(dev, "TRT_STDATA[%02d]: 0x%08x\n", i,
+ udma_tchanrt_read(uc, offset));
+ }
+ }
+
+ if (uc->config.dir == DMA_DEV_TO_MEM || uc->config.dir == DMA_MEM_TO_MEM) {
+ dev_dbg(dev, "RCHAN State data:\n");
+ for (i = 0; i < 32; i++) {
+ offset = UDMA_CHAN_RT_STDATA_REG + i * 4;
+ dev_dbg(dev, "RRT_STDATA[%02d]: 0x%08x\n", i,
+ udma_rchanrt_read(uc, offset));
+ }
+ }
+}
+
+bool udma_is_chan_running(struct udma_chan *uc)
+{
+ u32 trt_ctl = 0;
+ u32 rrt_ctl = 0;
+
+ if (uc->tchan)
+ trt_ctl = udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
+ if (uc->rchan)
+ rrt_ctl = udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
+
+ if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL_GPL(udma_is_chan_running);
+
+bool udma_chan_needs_reconfiguration(struct udma_chan *uc)
+{
+ /* Only PDMAs have staticTR */
+ if (uc->config.ep_type == PSIL_EP_NATIVE)
+ return false;
+
+ /* Check if the staticTR configuration has changed for TX */
+ if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr)))
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL_GPL(udma_chan_needs_reconfiguration);
+
+void udma_cyclic_packet_elapsed(struct udma_chan *uc)
+{
+ struct udma_desc *d = uc->desc;
+ struct cppi5_host_desc_t *h_desc;
+
+ h_desc = d->hwdesc[d->desc_idx].cppi5_desc_vaddr;
+ cppi5_hdesc_reset_to_original(h_desc);
+ udma_push_to_ring(uc, d->desc_idx);
+ d->desc_idx = (d->desc_idx + 1) % d->sglen;
+}
+EXPORT_SYMBOL_GPL(udma_cyclic_packet_elapsed);
+
+void udma_check_tx_completion(struct work_struct *work)
+{
+ struct udma_chan *uc = container_of(work, typeof(*uc),
+ tx_drain.work.work);
+ bool desc_done = true;
+ u32 residue_diff;
+ ktime_t time_diff;
+ unsigned long delay;
+ unsigned long flags;
+
+ while (1) {
+ spin_lock_irqsave(&uc->vc.lock, flags);
+
+ if (uc->desc) {
+ /* Get previous residue and time stamp */
+ residue_diff = uc->tx_drain.residue;
+ time_diff = uc->tx_drain.tstamp;
+ /*
+ * Get current residue and time stamp or see if
+ * transfer is complete
+ */
+ desc_done = udma_is_desc_really_done(uc, uc->desc);
+ }
+
+ if (!desc_done) {
+ /*
+ * Find the time delta and residue delta w.r.t
+ * previous poll
+ */
+ time_diff = ktime_sub(uc->tx_drain.tstamp,
+ time_diff) + 1;
+ residue_diff -= uc->tx_drain.residue;
+ if (residue_diff) {
+ /*
+ * Try to guess when we should check
+ * next time by calculating rate at
+ * which data is being drained at the
+ * peer device
+ */
+ delay = (time_diff / residue_diff) *
+ uc->tx_drain.residue;
+ } else {
+ /* No progress, check again in 1 second */
+ schedule_delayed_work(&uc->tx_drain.work, HZ);
+ break;
+ }
+
+ spin_unlock_irqrestore(&uc->vc.lock, flags);
+
+ usleep_range(ktime_to_us(delay),
+ ktime_to_us(delay) + 10);
+ continue;
+ }
+
+ if (uc->desc) {
+ struct udma_desc *d = uc->desc;
+
+ uc->ud->decrement_byte_counters(uc, d->residue);
+ uc->ud->start(uc);
+ vchan_cookie_complete(&d->vd);
+ break;
+ }
+
+ break;
+ }
+
+ spin_unlock_irqrestore(&uc->vc.lock, flags);
+}
+EXPORT_SYMBOL_GPL(udma_check_tx_completion);
+
+int udma_slave_config(struct dma_chan *chan,
+ struct dma_slave_config *cfg)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+
+ memcpy(&uc->cfg, cfg, sizeof(uc->cfg));
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(udma_slave_config);
+
+void udma_issue_pending(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ unsigned long flags;
+
+ spin_lock_irqsave(&uc->vc.lock, flags);
+
+ /* If we have something pending and no active descriptor, then */
+ if (vchan_issue_pending(&uc->vc) && !uc->desc) {
+ /*
+ * start a descriptor if the channel is NOT [marked as
+ * terminating _and_ it is still running (teardown has not
+ * completed yet)].
+ */
+ if (!(uc->state == UDMA_CHAN_IS_TERMINATING &&
+ udma_is_chan_running(uc)))
+ uc->ud->start(uc);
+ }
+
+ spin_unlock_irqrestore(&uc->vc.lock, flags);
+}
+EXPORT_SYMBOL_GPL(udma_issue_pending);
+
+int udma_terminate_all(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(&uc->vc.lock, flags);
+
+ if (udma_is_chan_running(uc))
+ uc->ud->stop(uc);
+
+ if (uc->desc) {
+ uc->terminated_desc = uc->desc;
+ uc->desc = NULL;
+ uc->terminated_desc->terminated = true;
+ cancel_delayed_work(&uc->tx_drain.work);
+ }
+
+ uc->paused = false;
+
+ vchan_get_all_descriptors(&uc->vc, &head);
+ spin_unlock_irqrestore(&uc->vc.lock, flags);
+ vchan_dma_desc_free_list(&uc->vc, &head);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(udma_terminate_all);
+
+void udma_synchronize(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ unsigned long timeout = msecs_to_jiffies(1000);
+
+ vchan_synchronize(&uc->vc);
+
+ if (uc->state == UDMA_CHAN_IS_TERMINATING) {
+ timeout = wait_for_completion_timeout(&uc->teardown_completed,
+ timeout);
+ if (!timeout) {
+ dev_warn(uc->ud->dev, "chan%d teardown timeout!\n",
+ uc->id);
+ udma_dump_chan_stdata(uc);
+ uc->ud->reset_chan(uc, true);
+ }
+ }
+
+ uc->ud->reset_chan(uc, false);
+ if (udma_is_chan_running(uc))
+ dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id);
+
+ cancel_delayed_work_sync(&uc->tx_drain.work);
+ udma_reset_rings(uc);
+}
+EXPORT_SYMBOL_GPL(udma_synchronize);
+
+/*
+ * This tasklet handles the completion of a DMA descriptor by
+ * calling its callback and freeing it.
+ */
+void udma_vchan_complete(struct tasklet_struct *t)
+{
+ struct virt_dma_chan *vc = from_tasklet(vc, t, task);
+ struct virt_dma_desc *vd, *_vd;
+ struct dmaengine_desc_callback cb;
+ LIST_HEAD(head);
+
+ spin_lock_irq(&vc->lock);
+ list_splice_tail_init(&vc->desc_completed, &head);
+ vd = vc->cyclic;
+ if (vd) {
+ vc->cyclic = NULL;
+ dmaengine_desc_get_callback(&vd->tx, &cb);
+ } else {
+ memset(&cb, 0, sizeof(cb));
+ }
+ spin_unlock_irq(&vc->lock);
+
+ udma_desc_pre_callback(vc, vd, NULL);
+ dmaengine_desc_callback_invoke(&cb, NULL);
+
+ list_for_each_entry_safe(vd, _vd, &head, node) {
+ struct dmaengine_result result;
+
+ dmaengine_desc_get_callback(&vd->tx, &cb);
+
+ list_del(&vd->node);
+
+ udma_desc_pre_callback(vc, vd, &result);
+ dmaengine_desc_callback_invoke(&cb, &result);
+
+ vchan_vdesc_fini(vd);
+ }
+}
+EXPORT_SYMBOL_GPL(udma_vchan_complete);
+
+void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map,
+ struct ti_sci_resource_desc *rm_desc,
+ char *name)
+{
+ bitmap_clear(map, rm_desc->start, rm_desc->num);
+ bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec);
+ dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name,
+ rm_desc->start, rm_desc->num, rm_desc->start_sec,
+ rm_desc->num_sec);
+}
+EXPORT_SYMBOL_GPL(udma_mark_resource_ranges);
+
+int udma_setup_rx_flush(struct udma_dev *ud)
+{
+ struct udma_rx_flush *rx_flush = &ud->rx_flush;
+ struct cppi5_desc_hdr_t *tr_desc;
+ struct cppi5_tr_type1_t *tr_req;
+ struct cppi5_host_desc_t *desc;
+ struct device *dev = ud->dev;
+ struct udma_hwdesc *hwdesc;
+ size_t tr_size;
+
+ /* Allocate 1K buffer for discarded data on RX channel teardown */
+ rx_flush->buffer_size = SZ_1K;
+ rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size,
+ GFP_KERNEL);
+ if (!rx_flush->buffer_vaddr)
+ return -ENOMEM;
+
+ rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr,
+ rx_flush->buffer_size,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, rx_flush->buffer_paddr))
+ return -ENOMEM;
+
+ /* Set up descriptor to be used for TR mode */
+ hwdesc = &rx_flush->hwdescs[0];
+ tr_size = sizeof(struct cppi5_tr_type1_t);
+ hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1);
+ hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size,
+ ud->desc_align);
+
+ hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
+ GFP_KERNEL);
+ if (!hwdesc->cppi5_desc_vaddr)
+ return -ENOMEM;
+
+ hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
+ hwdesc->cppi5_desc_size,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
+ return -ENOMEM;
+
+ /* Start of the TR req records */
+ hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size;
+ /* Start address of the TR response array */
+ hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size;
+
+ tr_desc = hwdesc->cppi5_desc_vaddr;
+ cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0);
+ cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
+ cppi5_desc_set_retpolicy(tr_desc, 0, 0);
+
+ tr_req = hwdesc->tr_req_base;
+ cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,
+ CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
+ cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);
+
+ tr_req->addr = rx_flush->buffer_paddr;
+ tr_req->icnt0 = rx_flush->buffer_size;
+ tr_req->icnt1 = 1;
+
+ dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
+ hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
+
+ /* Set up descriptor to be used for packet mode */
+ hwdesc = &rx_flush->hwdescs[1];
+ hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
+ CPPI5_INFO0_HDESC_EPIB_SIZE +
+ CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE,
+ ud->desc_align);
+
+ hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
+ GFP_KERNEL);
+ if (!hwdesc->cppi5_desc_vaddr)
+ return -ENOMEM;
+
+ hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
+ hwdesc->cppi5_desc_size,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
+ return -ENOMEM;
+
+ desc = hwdesc->cppi5_desc_vaddr;
+ cppi5_hdesc_init(desc, 0, 0);
+ cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
+ cppi5_desc_set_retpolicy(&desc->hdr, 0, 0);
+
+ cppi5_hdesc_attach_buf(desc,
+ rx_flush->buffer_paddr, rx_flush->buffer_size,
+ rx_flush->buffer_paddr, rx_flush->buffer_size);
+
+ dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
+ hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(udma_setup_rx_flush);
+
+#ifdef CONFIG_DEBUG_FS
+void udma_dbg_summary_show_chan(struct seq_file *s,
+ struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ struct udma_chan_config *ucc = &uc->config;
+
+ seq_printf(s, " %-13s| %s", dma_chan_name(chan),
+ chan->dbg_client_name ?: "in-use");
+ if (ucc->tr_trigger_type)
+ seq_puts(s, " (triggered, ");
+ else
+ seq_printf(s, " (%s, ",
+ dmaengine_get_direction_text(uc->config.dir));
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_MEM:
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA) {
+ seq_printf(s, "bchan%d)\n", uc->bchan->id);
+ return;
+ }
+
+ seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id,
+ ucc->src_thread, ucc->dst_thread);
+ break;
+ case DMA_DEV_TO_MEM:
+ seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id,
+ ucc->src_thread, ucc->dst_thread);
+ if (uc->ud->match_data->type == DMA_TYPE_PKTDMA)
+ seq_printf(s, "rflow%d, ", uc->rflow->id);
+ break;
+ case DMA_MEM_TO_DEV:
+ seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id,
+ ucc->src_thread, ucc->dst_thread);
+ if (uc->ud->match_data->type == DMA_TYPE_PKTDMA)
+ seq_printf(s, "tflow%d, ", uc->tchan->tflow_id);
+ break;
+ default:
+ seq_puts(s, ")\n");
+ return;
+ }
+
+ if (ucc->ep_type == PSIL_EP_NATIVE) {
+ seq_puts(s, "PSI-L Native");
+ if (ucc->metadata_size) {
+ seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : "");
+ if (ucc->psd_size)
+ seq_printf(s, " PSDsize:%u", ucc->psd_size);
+ seq_puts(s, " ]");
+ }
+ } else {
+ seq_puts(s, "PDMA");
+ if (ucc->enable_acc32 || ucc->enable_burst)
+ seq_printf(s, "[%s%s ]",
+ ucc->enable_acc32 ? " ACC32" : "",
+ ucc->enable_burst ? " BURST" : "");
+ }
+
+ seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode");
+}
+
+void udma_dbg_summary_show(struct seq_file *s,
+ struct dma_device *dma_dev)
+{
+ struct dma_chan *chan;
+
+ list_for_each_entry(chan, &dma_dev->channels, device_node) {
+ if (chan->client_count)
+ udma_dbg_summary_show_chan(s, chan);
+ }
+}
+EXPORT_SYMBOL_GPL(udma_dbg_summary_show);
+#endif /* CONFIG_DEBUG_FS */
+
+enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud)
+{
+ const struct udma_match_data *match_data = ud->match_data;
+ u8 tpl;
+
+ if (!match_data->enable_memcpy_support)
+ return DMAENGINE_ALIGN_8_BYTES;
+
+ /* Get the highest TPL level the device supports for memcpy */
+ if (ud->bchan_cnt)
+ tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, 0);
+ else if (ud->tchan_cnt)
+ tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, 0);
+ else
+ return DMAENGINE_ALIGN_8_BYTES;
+
+ switch (match_data->burst_size[tpl]) {
+ case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES:
+ return DMAENGINE_ALIGN_256_BYTES;
+ case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES:
+ return DMAENGINE_ALIGN_128_BYTES;
+ case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES:
+ fallthrough;
+ default:
+ return DMAENGINE_ALIGN_64_BYTES;
+ }
+}
+EXPORT_SYMBOL_GPL(udma_get_copy_align);
+
MODULE_DESCRIPTION("Texas Instruments K3 UDMA Common Library");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 21b1e3908399d..89c887bc86a34 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -61,92 +61,6 @@ int navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
src_thread, dst_thread);
}
-static void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel)
-{
- struct device *chan_dev = &chan->dev->device;
-
- if (asel == 0) {
- /* No special handling for the channel */
- chan->dev->chan_dma_dev = false;
-
- chan_dev->dma_coherent = false;
- chan_dev->dma_parms = NULL;
- } else if (asel == 14 || asel == 15) {
- chan->dev->chan_dma_dev = true;
-
- chan_dev->dma_coherent = true;
- dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48));
- chan_dev->dma_parms = chan_dev->parent->dma_parms;
- } else {
- dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel);
-
- chan_dev->dma_coherent = false;
- chan_dev->dma_parms = NULL;
- }
-}
-
-static u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id)
-{
- int i;
-
- for (i = 0; i < tpl_map->levels; i++) {
- if (chan_id >= tpl_map->start_idx[i])
- return i;
- }
-
- return 0;
-}
-
-static void udma_reset_uchan(struct udma_chan *uc)
-{
- memset(&uc->config, 0, sizeof(uc->config));
- uc->config.remote_thread_id = -1;
- uc->config.mapped_channel_id = -1;
- uc->config.default_flow_id = -1;
- uc->state = UDMA_CHAN_IS_IDLE;
-}
-
-static void udma_dump_chan_stdata(struct udma_chan *uc)
-{
- struct device *dev = uc->ud->dev;
- u32 offset;
- int i;
-
- if (uc->config.dir == DMA_MEM_TO_DEV || uc->config.dir == DMA_MEM_TO_MEM) {
- dev_dbg(dev, "TCHAN State data:\n");
- for (i = 0; i < 32; i++) {
- offset = UDMA_CHAN_RT_STDATA_REG + i * 4;
- dev_dbg(dev, "TRT_STDATA[%02d]: 0x%08x\n", i,
- udma_tchanrt_read(uc, offset));
- }
- }
-
- if (uc->config.dir == DMA_DEV_TO_MEM || uc->config.dir == DMA_MEM_TO_MEM) {
- dev_dbg(dev, "RCHAN State data:\n");
- for (i = 0; i < 32; i++) {
- offset = UDMA_CHAN_RT_STDATA_REG + i * 4;
- dev_dbg(dev, "RRT_STDATA[%02d]: 0x%08x\n", i,
- udma_rchanrt_read(uc, offset));
- }
- }
-}
-
-static bool udma_is_chan_running(struct udma_chan *uc)
-{
- u32 trt_ctl = 0;
- u32 rrt_ctl = 0;
-
- if (uc->tchan)
- trt_ctl = udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
- if (uc->rchan)
- rrt_ctl = udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
-
- if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
- return true;
-
- return false;
-}
-
static bool udma_is_chan_paused(struct udma_chan *uc)
{
u32 val, pause_mask;
@@ -275,40 +189,6 @@ static int udma_reset_chan(struct udma_chan *uc, bool hard)
return 0;
}
-static void udma_start_desc(struct udma_chan *uc)
-{
- struct udma_chan_config *ucc = &uc->config;
-
- if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode &&
- (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) {
- int i;
-
- /*
- * UDMA only: Push all descriptors to ring for packet mode
- * cyclic or RX
- * PKTDMA supports pre-linked descriptor and cyclic is not
- * supported
- */
- for (i = 0; i < uc->desc->sglen; i++)
- udma_push_to_ring(uc, i);
- } else {
- udma_push_to_ring(uc, 0);
- }
-}
-
-static bool udma_chan_needs_reconfiguration(struct udma_chan *uc)
-{
- /* Only PDMAs have staticTR */
- if (uc->config.ep_type == PSIL_EP_NATIVE)
- return false;
-
- /* Check if the staticTR configuration has changed for TX */
- if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr)))
- return true;
-
- return false;
-}
-
static int udma_start(struct udma_chan *uc)
{
struct virt_dma_desc *vd = vchan_next_desc(&uc->vc);
@@ -453,86 +333,6 @@ static int udma_stop(struct udma_chan *uc)
return 0;
}
-static void udma_cyclic_packet_elapsed(struct udma_chan *uc)
-{
- struct udma_desc *d = uc->desc;
- struct cppi5_host_desc_t *h_desc;
-
- h_desc = d->hwdesc[d->desc_idx].cppi5_desc_vaddr;
- cppi5_hdesc_reset_to_original(h_desc);
- udma_push_to_ring(uc, d->desc_idx);
- d->desc_idx = (d->desc_idx + 1) % d->sglen;
-}
-
-static void udma_check_tx_completion(struct work_struct *work)
-{
- struct udma_chan *uc = container_of(work, typeof(*uc),
- tx_drain.work.work);
- bool desc_done = true;
- u32 residue_diff;
- ktime_t time_diff;
- unsigned long delay;
- unsigned long flags;
-
- while (1) {
- spin_lock_irqsave(&uc->vc.lock, flags);
-
- if (uc->desc) {
- /* Get previous residue and time stamp */
- residue_diff = uc->tx_drain.residue;
- time_diff = uc->tx_drain.tstamp;
- /*
- * Get current residue and time stamp or see if
- * transfer is complete
- */
- desc_done = udma_is_desc_really_done(uc, uc->desc);
- }
-
- if (!desc_done) {
- /*
- * Find the time delta and residue delta w.r.t
- * previous poll
- */
- time_diff = ktime_sub(uc->tx_drain.tstamp,
- time_diff) + 1;
- residue_diff -= uc->tx_drain.residue;
- if (residue_diff) {
- /*
- * Try to guess when we should check
- * next time by calculating rate at
- * which data is being drained at the
- * peer device
- */
- delay = (time_diff / residue_diff) *
- uc->tx_drain.residue;
- } else {
- /* No progress, check again in 1 second */
- schedule_delayed_work(&uc->tx_drain.work, HZ);
- break;
- }
-
- spin_unlock_irqrestore(&uc->vc.lock, flags);
-
- usleep_range(ktime_to_us(delay),
- ktime_to_us(delay) + 10);
- continue;
- }
-
- if (uc->desc) {
- struct udma_desc *d = uc->desc;
-
- uc->ud->decrement_byte_counters(uc, d->residue);
- uc->ud->start(uc);
- vchan_cookie_complete(&d->vd);
- break;
- }
-
- break;
- }
-
- spin_unlock_irqrestore(&uc->vc.lock, flags);
-}
-
static irqreturn_t udma_ring_irq_handler(int irq, void *data)
{
struct udma_chan *uc = data;
@@ -2097,38 +1897,6 @@ static int pktdma_alloc_chan_resources(struct dma_chan *chan)
return ret;
}
-static int udma_slave_config(struct dma_chan *chan,
- struct dma_slave_config *cfg)
-{
- struct udma_chan *uc = to_udma_chan(chan);
-
- memcpy(&uc->cfg, cfg, sizeof(uc->cfg));
-
- return 0;
-}
-
-static void udma_issue_pending(struct dma_chan *chan)
-{
- struct udma_chan *uc = to_udma_chan(chan);
- unsigned long flags;
-
- spin_lock_irqsave(&uc->vc.lock, flags);
-
- /* If we have something pending and no active descriptor, then */
- if (vchan_issue_pending(&uc->vc) && !uc->desc) {
- /*
- * start a descriptor if the channel is NOT [marked as
- * terminating _and_ it is still running (teardown has not
- * completed yet)].
- */
- if (!(uc->state == UDMA_CHAN_IS_TERMINATING &&
- udma_is_chan_running(uc)))
- uc->ud->start(uc);
- }
-
- spin_unlock_irqrestore(&uc->vc.lock, flags);
-}
-
static enum dma_status udma_tx_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
@@ -2256,98 +2024,6 @@ static int udma_resume(struct dma_chan *chan)
return 0;
}
-static int udma_terminate_all(struct dma_chan *chan)
-{
- struct udma_chan *uc = to_udma_chan(chan);
- unsigned long flags;
- LIST_HEAD(head);
-
- spin_lock_irqsave(&uc->vc.lock, flags);
-
- if (udma_is_chan_running(uc))
- uc->ud->stop(uc);
-
- if (uc->desc) {
- uc->terminated_desc = uc->desc;
- uc->desc = NULL;
- uc->terminated_desc->terminated = true;
- cancel_delayed_work(&uc->tx_drain.work);
- }
-
- uc->paused = false;
-
- vchan_get_all_descriptors(&uc->vc, &head);
- spin_unlock_irqrestore(&uc->vc.lock, flags);
- vchan_dma_desc_free_list(&uc->vc, &head);
-
- return 0;
-}
-
-static void udma_synchronize(struct dma_chan *chan)
-{
- struct udma_chan *uc = to_udma_chan(chan);
- unsigned long timeout = msecs_to_jiffies(1000);
-
- vchan_synchronize(&uc->vc);
-
- if (uc->state == UDMA_CHAN_IS_TERMINATING) {
- timeout = wait_for_completion_timeout(&uc->teardown_completed,
- timeout);
- if (!timeout) {
- dev_warn(uc->ud->dev, "chan%d teardown timeout!\n",
- uc->id);
- udma_dump_chan_stdata(uc);
- uc->ud->reset_chan(uc, true);
- }
- }
-
- uc->ud->reset_chan(uc, false);
- if (udma_is_chan_running(uc))
- dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id);
-
- cancel_delayed_work_sync(&uc->tx_drain.work);
- udma_reset_rings(uc);
-}
-
-/*
- * This tasklet handles the completion of a DMA descriptor by
- * calling its callback and freeing it.
- */
-static void udma_vchan_complete(struct tasklet_struct *t)
-{
- struct virt_dma_chan *vc = from_tasklet(vc, t, task);
- struct virt_dma_desc *vd, *_vd;
- struct dmaengine_desc_callback cb;
- LIST_HEAD(head);
-
- spin_lock_irq(&vc->lock);
- list_splice_tail_init(&vc->desc_completed, &head);
- vd = vc->cyclic;
- if (vd) {
- vc->cyclic = NULL;
- dmaengine_desc_get_callback(&vd->tx, &cb);
- } else {
- memset(&cb, 0, sizeof(cb));
- }
- spin_unlock_irq(&vc->lock);
-
- udma_desc_pre_callback(vc, vd, NULL);
- dmaengine_desc_callback_invoke(&cb, NULL);
-
- list_for_each_entry_safe(vd, _vd, &head, node) {
- struct dmaengine_result result;
-
- dmaengine_desc_get_callback(&vd->tx, &cb);
-
- list_del(&vd->node);
-
- udma_desc_pre_callback(vc, vd, &result);
- dmaengine_desc_callback_invoke(&cb, &result);
-
- vchan_vdesc_fini(vd);
- }
-}
-
static void udma_free_chan_resources(struct dma_chan *chan)
{
struct udma_chan *uc = to_udma_chan(chan);
@@ -2822,17 +2498,6 @@ static int udma_get_mmrs(struct platform_device *pdev, struct udma_dev *ud)
return 0;
}
-static void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map,
- struct ti_sci_resource_desc *rm_desc,
- char *name)
-{
- bitmap_clear(map, rm_desc->start, rm_desc->num);
- bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec);
- dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name,
- rm_desc->start, rm_desc->num, rm_desc->start_sec,
- rm_desc->num_sec);
-}
-
static const char * const range_names[] = {
[RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan",
[RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan",
@@ -3463,202 +3128,6 @@ static int setup_resources(struct udma_dev *ud)
return ch_count;
}
-static int udma_setup_rx_flush(struct udma_dev *ud)
-{
- struct udma_rx_flush *rx_flush = &ud->rx_flush;
- struct cppi5_desc_hdr_t *tr_desc;
- struct cppi5_tr_type1_t *tr_req;
- struct cppi5_host_desc_t *desc;
- struct device *dev = ud->dev;
- struct udma_hwdesc *hwdesc;
- size_t tr_size;
-
- /* Allocate 1K buffer for discarded data on RX channel teardown */
- rx_flush->buffer_size = SZ_1K;
- rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size,
- GFP_KERNEL);
- if (!rx_flush->buffer_vaddr)
- return -ENOMEM;
-
- rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr,
- rx_flush->buffer_size,
- DMA_TO_DEVICE);
- if (dma_mapping_error(dev, rx_flush->buffer_paddr))
- return -ENOMEM;
-
- /* Set up descriptor to be used for TR mode */
- hwdesc = &rx_flush->hwdescs[0];
- tr_size = sizeof(struct cppi5_tr_type1_t);
- hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1);
- hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size,
- ud->desc_align);
-
- hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
- GFP_KERNEL);
- if (!hwdesc->cppi5_desc_vaddr)
- return -ENOMEM;
-
- hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
- hwdesc->cppi5_desc_size,
- DMA_TO_DEVICE);
- if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
- return -ENOMEM;
-
- /* Start of the TR req records */
- hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size;
- /* Start address of the TR response array */
- hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size;
-
- tr_desc = hwdesc->cppi5_desc_vaddr;
- cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0);
- cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
- cppi5_desc_set_retpolicy(tr_desc, 0, 0);
-
- tr_req = hwdesc->tr_req_base;
- cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,
- CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
- cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);
-
- tr_req->addr = rx_flush->buffer_paddr;
- tr_req->icnt0 = rx_flush->buffer_size;
- tr_req->icnt1 = 1;
-
- dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
- hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
-
- /* Set up descriptor to be used for packet mode */
- hwdesc = &rx_flush->hwdescs[1];
- hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
- CPPI5_INFO0_HDESC_EPIB_SIZE +
- CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE,
- ud->desc_align);
-
- hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
- GFP_KERNEL);
- if (!hwdesc->cppi5_desc_vaddr)
- return -ENOMEM;
-
- hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
- hwdesc->cppi5_desc_size,
- DMA_TO_DEVICE);
- if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
- return -ENOMEM;
-
- desc = hwdesc->cppi5_desc_vaddr;
- cppi5_hdesc_init(desc, 0, 0);
- cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
- cppi5_desc_set_retpolicy(&desc->hdr, 0, 0);
-
- cppi5_hdesc_attach_buf(desc,
- rx_flush->buffer_paddr, rx_flush->buffer_size,
- rx_flush->buffer_paddr, rx_flush->buffer_size);
-
- dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
- hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void udma_dbg_summary_show_chan(struct seq_file *s,
- struct dma_chan *chan)
-{
- struct udma_chan *uc = to_udma_chan(chan);
- struct udma_chan_config *ucc = &uc->config;
-
- seq_printf(s, " %-13s| %s", dma_chan_name(chan),
- chan->dbg_client_name ?: "in-use");
- if (ucc->tr_trigger_type)
- seq_puts(s, " (triggered, ");
- else
- seq_printf(s, " (%s, ",
- dmaengine_get_direction_text(uc->config.dir));
-
- switch (uc->config.dir) {
- case DMA_MEM_TO_MEM:
- if (uc->ud->match_data->type == DMA_TYPE_BCDMA) {
- seq_printf(s, "bchan%d)\n", uc->bchan->id);
- return;
- }
-
- seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id,
- ucc->src_thread, ucc->dst_thread);
- break;
- case DMA_DEV_TO_MEM:
- seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id,
- ucc->src_thread, ucc->dst_thread);
- if (uc->ud->match_data->type == DMA_TYPE_PKTDMA)
- seq_printf(s, "rflow%d, ", uc->rflow->id);
- break;
- case DMA_MEM_TO_DEV:
- seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id,
- ucc->src_thread, ucc->dst_thread);
- if (uc->ud->match_data->type == DMA_TYPE_PKTDMA)
- seq_printf(s, "tflow%d, ", uc->tchan->tflow_id);
- break;
- default:
- seq_printf(s, ")\n");
- return;
- }
-
- if (ucc->ep_type == PSIL_EP_NATIVE) {
- seq_printf(s, "PSI-L Native");
- if (ucc->metadata_size) {
- seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : "");
- if (ucc->psd_size)
- seq_printf(s, " PSDsize:%u", ucc->psd_size);
- seq_printf(s, " ]");
- }
- } else {
- seq_printf(s, "PDMA");
- if (ucc->enable_acc32 || ucc->enable_burst)
- seq_printf(s, "[%s%s ]",
- ucc->enable_acc32 ? " ACC32" : "",
- ucc->enable_burst ? " BURST" : "");
- }
-
- seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode");
-}
-
-static void udma_dbg_summary_show(struct seq_file *s,
- struct dma_device *dma_dev)
-{
- struct dma_chan *chan;
-
- list_for_each_entry(chan, &dma_dev->channels, device_node) {
- if (chan->client_count)
- udma_dbg_summary_show_chan(s, chan);
- }
-}
-#endif /* CONFIG_DEBUG_FS */
-
-static enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud)
-{
- const struct udma_match_data *match_data = ud->match_data;
- u8 tpl;
-
- if (!match_data->enable_memcpy_support)
- return DMAENGINE_ALIGN_8_BYTES;
-
- /* Get the highest TPL level the device supports for memcpy */
- if (ud->bchan_cnt)
- tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, 0);
- else if (ud->tchan_cnt)
- tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, 0);
- else
- return DMAENGINE_ALIGN_8_BYTES;
-
- switch (match_data->burst_size[tpl]) {
- case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES:
- return DMAENGINE_ALIGN_256_BYTES;
- case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES:
- return DMAENGINE_ALIGN_128_BYTES;
- case TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES:
- fallthrough;
- default:
- return DMAENGINE_ALIGN_64_BYTES;
- }
-}
-
static int udma_probe(struct platform_device *pdev)
{
struct device_node *navss_node = pdev->dev.parent->of_node;
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index 2f5fbea446fed..797e8b0c5b85e 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -625,6 +625,34 @@ void udma_reset_rings(struct udma_chan *uc);
int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread);
int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread);
+void udma_start_desc(struct udma_chan *uc);
+u8 udma_get_chan_tpl_index(struct udma_tpl *tpl_map, int chan_id);
+void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel);
+void udma_reset_uchan(struct udma_chan *uc);
+void udma_dump_chan_stdata(struct udma_chan *uc);
+bool udma_is_chan_running(struct udma_chan *uc);
+
+bool udma_chan_needs_reconfiguration(struct udma_chan *uc);
+void udma_cyclic_packet_elapsed(struct udma_chan *uc);
+void udma_check_tx_completion(struct work_struct *work);
+int udma_slave_config(struct dma_chan *chan,
+ struct dma_slave_config *cfg);
+void udma_issue_pending(struct dma_chan *chan);
+int udma_terminate_all(struct dma_chan *chan);
+void udma_synchronize(struct dma_chan *chan);
+void udma_vchan_complete(struct tasklet_struct *t);
+void udma_mark_resource_ranges(struct udma_dev *ud, unsigned long *map,
+ struct ti_sci_resource_desc *rm_desc,
+ char *name);
+int udma_setup_rx_flush(struct udma_dev *ud);
+enum dmaengine_alignment udma_get_copy_align(struct udma_dev *ud);
+
+#ifdef CONFIG_DEBUG_FS
+void udma_dbg_summary_show_chan(struct seq_file *s,
+ struct dma_chan *chan);
+void udma_dbg_summary_show(struct seq_file *s,
+ struct dma_device *dma_dev);
+#endif /* CONFIG_DEBUG_FS */
/* Direct access to UDMA low lever resources for the glue layer */
int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread);
--
2.53.0
^ permalink raw reply related
* [PATCH v6 17/19] dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2
From: Sai Sree Kartheek Adivi @ 2026-04-28 8:51 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, vigneshr,
Frank.li, s-adivi
Cc: r-sharma3, gehariprasath
In-Reply-To: <20260428085202.1724548-1-s-adivi@ti.com>
The PKTDMA V2 is different than the existing PKTDMA supported by the
k3-udma driver.
The changes in PKTDMA V2 are:
- Autopair: There is no longer a need for PSIL pair and AUTOPAIR bit
needs to set in the RT_CTL register.
- Static channel mapping: Each channel is mapped to a single
peripheral.
- Direct IRQs: There is no INT-A and interrupt lines from DMA are
directly connected to GIC.
- Remote side configuration handled by DMA. So no need to write to
PEER registers to START / STOP / PAUSE / TEARDOWN.
- Unified Channel Space: Tx and Rx channels share a single register
space. Each channel index is specifically fixed in hardware as either
Tx or Rx in an interleaved manner.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/k3-udma-common.c | 41 ++++--
drivers/dma/ti/k3-udma-v2.c | 214 ++++++++++++++++++++++++++++++--
drivers/dma/ti/k3-udma.h | 3 +
3 files changed, 234 insertions(+), 24 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index df657c63cf02b..304dad59bf183 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -2460,12 +2460,21 @@ int pktdma_setup_resources(struct udma_dev *ud)
ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
GFP_KERNEL);
- ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
- GFP_KERNEL);
+ if (ud->match_data->version == K3_UDMA_V1) {
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ } else {
+ ud->rchan_map = ud->tchan_map;
+ ud->rchans = ud->tchans;
+ ud->chan_map = ud->tchan_map;
+ ud->chans = ud->tchans;
+ }
ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
sizeof(unsigned long),
GFP_KERNEL);
@@ -2473,6 +2482,8 @@ int pktdma_setup_resources(struct udma_dev *ud)
GFP_KERNEL);
ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->tflow_map, ud->tflow_cnt);
+
if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
!ud->rchans || !ud->rflows || !ud->rflow_in_use)
@@ -2563,13 +2574,21 @@ int setup_resources(struct udma_dev *ud)
}
break;
case DMA_TYPE_PKTDMA:
- dev_info(dev,
- "Channels: %d (tchan: %u, rchan: %u)\n",
- ch_count,
- ud->tchan_cnt - bitmap_weight(ud->tchan_map,
- ud->tchan_cnt),
- ud->rchan_cnt - bitmap_weight(ud->rchan_map,
- ud->rchan_cnt));
+ if (ud->match_data->version == K3_UDMA_V1) {
+ dev_info(dev,
+ "Channels: %d (tchan: %u, rchan: %u)\n",
+ ch_count,
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt));
+ } else {
+ dev_info(dev,
+ "Channels: %d (tchan + rchan: %u)\n",
+ ch_count,
+ ud->chan_cnt - bitmap_weight(ud->chan_map,
+ ud->chan_cnt));
+ }
break;
default:
break;
diff --git a/drivers/dma/ti/k3-udma-v2.c b/drivers/dma/ti/k3-udma-v2.c
index 4b77d6380b1e9..5a64d0ff2d85a 100644
--- a/drivers/dma/ti/k3-udma-v2.c
+++ b/drivers/dma/ti/k3-udma-v2.c
@@ -740,6 +740,142 @@ static int bcdma_v2_alloc_chan_resources(struct dma_chan *chan)
return ret;
}
+static int pktdma_v2_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ struct udma_dev *ud = to_udma_dev(chan->device);
+ struct platform_device *pdev = to_platform_device(ud->dev);
+ char irq_name[10];
+ u32 irq_ring_idx;
+ int ret;
+
+ /*
+ * Make sure that the completion is in a known state:
+ * No teardown, the channel is idle
+ */
+ reinit_completion(&uc->teardown_completed);
+ complete_all(&uc->teardown_completed);
+ uc->state = UDMA_CHAN_IS_IDLE;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_DEV:
+ /* Slave transfer synchronized - mem to dev (TX) transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
+ uc->id);
+
+ ret = udma_v2_alloc_tx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = ud->psil_base + uc->tchan->id;
+ uc->config.dst_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ irq_ring_idx = uc->config.mapped_channel_id;
+ break;
+ case DMA_DEV_TO_MEM:
+ /* Slave transfer synchronized - dev to mem (RX) transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
+ uc->id);
+
+ ret = udma_v2_alloc_rx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
+ K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ irq_ring_idx = uc->config.mapped_channel_id;
+ udma_write(uc->rflow->reg_rt, UDMA_RX_FLOWRT_RFA, BIT(28));
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+ ud->reset_chan(uc, false);
+ if (udma_is_chan_running(uc)) {
+ dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+ ret = -EBUSY;
+ goto err_res_free;
+ }
+ }
+
+ uc->dma_dev = dmaengine_get_dma_device(chan);
+ uc->hdesc_pool = dma_pool_create(uc->name, uc->dma_dev,
+ uc->config.hdesc_size, ud->desc_align,
+ 0);
+ if (!uc->hdesc_pool) {
+ dev_err(ud->ddev.dev,
+ "Descriptor pool allocation failed\n");
+ uc->use_dma_pool = false;
+ ret = -ENOMEM;
+ goto err_res_free;
+ }
+
+ uc->use_dma_pool = true;
+
+ uc->psil_paired = true;
+
+ snprintf(irq_name, sizeof(irq_name), "chan%u", irq_ring_idx);
+ uc->irq_num_ring = platform_get_irq_byname(pdev, irq_name);
+ if (uc->irq_num_ring < 0)
+ return uc->irq_num_ring;
+
+ ret = devm_request_irq(ud->dev, uc->irq_num_ring, udma_v2_ring_irq_handler,
+ IRQF_TRIGGER_HIGH, uc->name, uc);
+
+ if (ret) {
+ dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id);
+ goto err_irq_free;
+ }
+
+ uc->irq_num_udma = 0;
+
+ udma_reset_rings(uc);
+
+ INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work,
+ udma_check_tx_completion);
+
+ if (uc->tchan)
+ dev_dbg(ud->dev,
+ "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->tchan->id, uc->tchan->tflow_id,
+ uc->config.remote_thread_id);
+ else if (uc->rchan)
+ dev_dbg(ud->dev,
+ "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->rchan->id, uc->rflow->id,
+ uc->config.remote_thread_id);
+ return 0;
+
+err_irq_free:
+ uc->irq_num_ring = 0;
+err_res_free:
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ dma_pool_destroy(uc->hdesc_pool);
+ uc->use_dma_pool = false;
+
+ return ret;
+}
+
static enum dma_status udma_v2_tx_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
@@ -834,6 +970,7 @@ static int udma_v2_resume(struct dma_chan *chan)
}
static struct platform_driver bcdma_v2_driver;
+static struct platform_driver pktdma_v2_driver;
static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param)
{
@@ -843,7 +980,8 @@ static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param)
struct udma_chan *uc;
struct udma_dev *ud;
- if (chan->device->dev->driver != &bcdma_v2_driver.driver)
+ if (chan->device->dev->driver != &bcdma_v2_driver.driver &&
+ chan->device->dev->driver != &pktdma_v2_driver.driver)
return false;
uc = to_udma_chan(chan);
@@ -986,11 +1124,34 @@ static struct udma_match_data bcdma_v2_am62l_data = {
.rchan_cnt = 128,
};
+static struct udma_match_data pktdma_v2_am62l_data = {
+ .type = DMA_TYPE_PKTDMA,
+ .version = K3_UDMA_V2,
+ .psil_base = 0x1000,
+ .enable_memcpy_support = false, /* PKTDMA does not support MEM_TO_MEM */
+ .flags = UDMA_FLAGS_J7_CLASS,
+ .statictr_z_mask = GENMASK(23, 0),
+ .burst_size = {
+ TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */
+ 0, /* No H Channels */
+ 0, /* No UH Channels */
+ },
+ .tchan_cnt = 97,
+ .rchan_cnt = 97,
+ .chan_cnt = 97,
+ .tflow_cnt = 112,
+ .rflow_cnt = 112,
+};
+
static const struct of_device_id udma_of_match[] = {
{
.compatible = "ti,am62l-dmss-bcdma",
.data = &bcdma_v2_am62l_data,
},
+ {
+ .compatible = "ti,am62l-dmss-pktdma",
+ .data = &pktdma_v2_am62l_data,
+ },
{ /* Sentinel */ },
};
@@ -1009,15 +1170,22 @@ static int udma_v2_get_mmrs(struct platform_device *pdev, struct udma_dev *ud)
if (IS_ERR(ud->mmrs[V2_MMR_GCFG]))
return PTR_ERR(ud->mmrs[V2_MMR_GCFG]);
- ud->bchan_cnt = ud->match_data->bchan_cnt;
- /* There are no tchan and rchan in BCDMA_V2.
+ /* There are no tchan and rchan in BCDMA_V2 and PKTDMA_V2.
* Duplicate chan as tchan and rchan to keep the common code
- * in k3-udma-common.c functional for BCDMA_V2.
+ * in k3-udma-common.c functional.
*/
- ud->chan_cnt = ud->match_data->chan_cnt;
- ud->tchan_cnt = ud->match_data->chan_cnt;
- ud->rchan_cnt = ud->match_data->chan_cnt;
- ud->rflow_cnt = ud->chan_cnt;
+ if (ud->match_data->type == DMA_TYPE_BCDMA) {
+ ud->bchan_cnt = ud->match_data->bchan_cnt;
+ ud->chan_cnt = ud->match_data->chan_cnt;
+ ud->tchan_cnt = ud->match_data->chan_cnt;
+ ud->rchan_cnt = ud->match_data->chan_cnt;
+ ud->rflow_cnt = ud->chan_cnt;
+ } else if (ud->match_data->type == DMA_TYPE_PKTDMA) {
+ ud->chan_cnt = ud->match_data->chan_cnt;
+ ud->tchan_cnt = ud->match_data->tchan_cnt;
+ ud->rchan_cnt = ud->match_data->rchan_cnt;
+ ud->rflow_cnt = ud->match_data->rflow_cnt;
+ }
for (i = 1; i < V2_MMR_LAST; i++) {
if (i == V2_MMR_BCHANRT && ud->bchan_cnt == 0)
@@ -1071,6 +1239,7 @@ static int udma_v2_probe(struct platform_device *pdev)
ud->reset_chan = udma_v2_reset_chan;
ud->decrement_byte_counters = udma_v2_decrement_byte_counters;
ud->bcdma_setup_sci_resources = NULL;
+ ud->pktdma_setup_sci_resources = NULL;
ret = udma_v2_get_mmrs(pdev, ud);
if (ret)
@@ -1078,7 +1247,14 @@ static int udma_v2_probe(struct platform_device *pdev)
struct k3_ringacc_init_data ring_init_data = {0};
- ring_init_data.num_rings = ud->bchan_cnt + ud->chan_cnt;
+ if (ud->match_data->type == DMA_TYPE_BCDMA) {
+ ring_init_data.num_rings = ud->bchan_cnt + ud->chan_cnt;
+ } else if (ud->match_data->type == DMA_TYPE_PKTDMA) {
+ ring_init_data.num_rings = ud->rflow_cnt;
+
+ ud->rflow_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
+ ring_init_data.base_rt = ud->rflow_rt;
+ }
ud->ringacc = k3_ringacc_dmarings_init(pdev, &ring_init_data);
@@ -1087,8 +1263,10 @@ static int udma_v2_probe(struct platform_device *pdev)
dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask);
- dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask);
- ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic;
+ if (ud->match_data->type != DMA_TYPE_PKTDMA) {
+ dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask);
+ ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic;
+ }
ud->ddev.device_config = udma_slave_config;
ud->ddev.device_prep_slave_sg = udma_prep_slave_sg;
@@ -1102,8 +1280,18 @@ static int udma_v2_probe(struct platform_device *pdev)
ud->ddev.dbg_summary_show = udma_dbg_summary_show;
#endif
- ud->ddev.device_alloc_chan_resources =
- bcdma_v2_alloc_chan_resources;
+ switch (ud->match_data->type) {
+ case DMA_TYPE_BCDMA:
+ ud->ddev.device_alloc_chan_resources =
+ bcdma_v2_alloc_chan_resources;
+ break;
+ case DMA_TYPE_PKTDMA:
+ ud->ddev.device_alloc_chan_resources =
+ pktdma_v2_alloc_chan_resources;
+ break;
+ default:
+ return -EINVAL;
+ }
ud->ddev.device_free_chan_resources = udma_free_chan_resources;
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index 771088462f80d..642d8fc8f3175 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -23,8 +23,11 @@
#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
#define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
+#define UDMA_RX_FLOWRT_RFA 0x8
+
/* BCHANRT/TCHANRT/RCHANRT registers */
#define UDMA_CHAN_RT_CTL_REG 0x0
+#define UDMA_CHAN_RT_CFG_REG 0x4
#define UDMA_CHAN_RT_SWTRIG_REG 0x8
#define UDMA_CHAN_RT_STDATA_REG 0x80
--
2.53.0
^ permalink raw reply related
* [PATCH v6 16/19] dmaengine: ti: k3-udma-v2: New driver for K3 BCDMA_V2
From: Sai Sree Kartheek Adivi @ 2026-04-28 8:51 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, vigneshr,
Frank.li, s-adivi
Cc: r-sharma3, gehariprasath
In-Reply-To: <20260428085202.1724548-1-s-adivi@ti.com>
Add support for BCDMA_V2.
The BCDMA_V2 is different than the existing BCDMA supported by the
k3-udma driver.
The changes in BCDMA_V2 are:
- Autopair: There is no longer a need for PSIL pair and AUTOPAIR bit
needs to set in the RT_CTL register.
- Static channel mapping: Each channel is mapped to a single peripheral.
- Direct IRQs: There is no INT-A and interrupt lines from DMA are
directly connected to GIC.
- Remote side configuration handled by DMA. So no need to write to PEER
registers to START / STOP / PAUSE / TEARDOWN.
- Unified Channel Space: Tx and Rx channels share a single register
space. Each channel index is specifically fixed in hardware as either
Tx or Rx in an interleaved manner.
Also, since a version member is introduced in the match_data, Add
version v1 in match_data of SoCs using v1 DMA.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/Kconfig | 14 +-
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-udma-common.c | 86 +-
drivers/dma/ti/k3-udma-v2.c | 1279 +++++++++++++++++++++++++++++
drivers/dma/ti/k3-udma.c | 9 +
drivers/dma/ti/k3-udma.h | 121 +--
include/linux/soc/ti/k3-ringacc.h | 3 +
7 files changed, 1442 insertions(+), 71 deletions(-)
create mode 100644 drivers/dma/ti/k3-udma-v2.c
diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig
index 712e456015459..40713bd1e8e9b 100644
--- a/drivers/dma/ti/Kconfig
+++ b/drivers/dma/ti/Kconfig
@@ -49,6 +49,18 @@ config TI_K3_UDMA
Enable support for the TI UDMA (Unified DMA) controller. This
DMA engine is used in AM65x and j721e.
+config TI_K3_UDMA_V2
+ tristate "Texas Instruments K3 UDMA v2 support"
+ depends on ARCH_K3
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ select TI_K3_UDMA_COMMON
+ select TI_K3_RINGACC
+ select TI_K3_PSIL
+ help
+ Enable support for the TI UDMA (Unified DMA) v2 controller. This
+ DMA engine is used in AM62L.
+
config TI_K3_UDMA_COMMON
tristate
default n
@@ -63,7 +75,7 @@ config TI_K3_UDMA_GLUE_LAYER
config TI_K3_PSIL
tristate
- default TI_K3_UDMA
+ default TI_K3_UDMA || TI_K3_UDMA_V2
config TI_DMA_CROSSBAR
bool
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 41bfba944dc6c..296aa3421e71b 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o
obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_DMA_OMAP) += omap-dma.o
obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o
+obj-$(CONFIG_TI_K3_UDMA_V2) += k3-udma-v2.o
obj-$(CONFIG_TI_K3_UDMA_COMMON) += k3-udma-common.o
obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) += k3-udma-glue.o
k3-psil-lib-objs := k3-psil.o \
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index 0ffc6becc402e..df657c63cf02b 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -171,8 +171,13 @@ bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d)
uc->config.dir != DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PREP_INTERRUPT))
return true;
- peer_bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
- bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+ if (uc->ud->match_data->version == K3_UDMA_V1) {
+ peer_bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
+ bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+ } else {
+ peer_bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG);
+ bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+ }
/* Transfer is incomplete, store current residue and time stamp */
if (peer_bcnt < bcnt) {
@@ -319,6 +324,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
size_t tr_size;
int num_tr = 0;
int tr_idx = 0;
+ u32 extra_flags = 0;
u64 asel;
/* estimate the number of TRs we will need */
@@ -342,6 +348,11 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
else
asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA &&
+ uc->ud->match_data->version == K3_UDMA_V2 &&
+ dir == DMA_MEM_TO_DEV)
+ extra_flags = CPPI5_TR_CSF_EOP;
+
tr_req = d->hwdesc[0].tr_req_base;
for_each_sg(sgl, sgent, sglen, i) {
dma_addr_t sg_addr = sg_dma_address(sgent);
@@ -358,7 +369,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
- cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);
+ cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT | extra_flags);
sg_addr |= asel;
tr_req[tr_idx].addr = sg_addr;
@@ -372,7 +383,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
false, false,
CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
cppi5_tr_csf_set(&tr_req[tr_idx].flags,
- CPPI5_TR_CSF_SUPR_EVT);
+ CPPI5_TR_CSF_SUPR_EVT | extra_flags);
tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;
tr_req[tr_idx].icnt0 = tr1_cnt0;
@@ -2052,6 +2063,8 @@ int udma_get_tchan(struct udma_chan *uc)
uc->tchan = NULL;
return ret;
}
+ if (ud->match_data->version == K3_UDMA_V2)
+ uc->chan = uc->tchan;
if (ud->tflow_cnt) {
int tflow_id;
@@ -2102,6 +2115,8 @@ int udma_get_rchan(struct udma_chan *uc)
uc->rchan = NULL;
return ret;
}
+ if (ud->match_data->version == K3_UDMA_V2)
+ uc->chan = uc->rchan;
return 0;
}
@@ -2379,16 +2394,26 @@ int bcdma_setup_resources(struct udma_dev *ud)
ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->bchan_map, ud->bchan_cnt);
ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
GFP_KERNEL);
ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
GFP_KERNEL);
- ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
- GFP_KERNEL);
+ if (ud->match_data->version == K3_UDMA_V1) {
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ } else {
+ ud->rchan_map = ud->tchan_map;
+ ud->rchans = ud->tchans;
+ ud->chan_map = ud->tchan_map;
+ ud->chans = ud->tchans;
+ }
/* BCDMA do not really have flows, but the driver expect it */
ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
sizeof(unsigned long),
@@ -2484,11 +2509,18 @@ int setup_resources(struct udma_dev *ud)
if (ret)
return ret;
- ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
- if (ud->bchan_cnt)
- ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
- ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
- ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
+ if (ud->match_data->version == K3_UDMA_V1) {
+ ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
+ if (ud->bchan_cnt)
+ ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
+ ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
+ ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
+ } else {
+ ch_count = ud->bchan_cnt + ud->tchan_cnt;
+ if (ud->bchan_cnt)
+ ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
+ ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
+ }
if (!ch_count)
return -ENODEV;
@@ -2510,15 +2542,25 @@ int setup_resources(struct udma_dev *ud)
ud->rflow_cnt));
break;
case DMA_TYPE_BCDMA:
- dev_info(dev,
- "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
- ch_count,
- ud->bchan_cnt - bitmap_weight(ud->bchan_map,
- ud->bchan_cnt),
- ud->tchan_cnt - bitmap_weight(ud->tchan_map,
- ud->tchan_cnt),
- ud->rchan_cnt - bitmap_weight(ud->rchan_map,
- ud->rchan_cnt));
+ if (ud->match_data->version == K3_UDMA_V1) {
+ dev_info(dev,
+ "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
+ ch_count,
+ ud->bchan_cnt - bitmap_weight(ud->bchan_map,
+ ud->bchan_cnt),
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt));
+ } else {
+ dev_info(dev,
+ "Channels: %d (bchan: %u, chan: %u)\n",
+ ch_count,
+ ud->bchan_cnt - bitmap_weight(ud->bchan_map,
+ ud->bchan_cnt),
+ ud->chan_cnt - bitmap_weight(ud->chan_map,
+ ud->chan_cnt));
+ }
break;
case DMA_TYPE_PKTDMA:
dev_info(dev,
diff --git a/drivers/dma/ti/k3-udma-v2.c b/drivers/dma/ti/k3-udma-v2.c
new file mode 100644
index 0000000000000..4b77d6380b1e9
--- /dev/null
+++ b/drivers/dma/ti/k3-udma-v2.c
@@ -0,0 +1,1279 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Derived from K3 UDMA driver (k3-udma.c)
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ * Author: Sai Sree Kartheek Adivi <s-adivi@ti.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/sys_soc.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/workqueue.h>
+#include <linux/completion.h>
+#include <linux/iopoll.h>
+#include <linux/soc/ti/k3-ringacc.h>
+
+#include "../virt-dma.h"
+#include "k3-udma.h"
+#include "k3-psil-priv.h"
+
+static const char * const v2_mmr_names[] = {
+ [V2_MMR_GCFG] = "gcfg",
+ [V2_MMR_BCHANRT] = "bchanrt",
+ [V2_MMR_CHANRT] = "chanrt",
+};
+
+static int udma_v2_check_chan_autopair_completion(struct udma_chan *uc)
+{
+ u32 val;
+
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
+ if (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT)
+ return -ETIMEDOUT;
+ else if (val & UDMA_CHAN_RT_CTL_PAIR_COMPLETE)
+ return 1;
+
+ /* timeout didn't occur and also pairing didn't happen yet. */
+ return 0;
+}
+
+static bool udma_v2_is_chan_paused(struct udma_chan *uc)
+{
+ u32 val, pause_mask;
+
+ if (uc->config.dir == DMA_MEM_TO_MEM) {
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
+ pause_mask = UDMA_CHAN_RT_CTL_PAUSE;
+ } else {
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_PDMA_STATE_REG);
+ pause_mask = UDMA_CHAN_RT_PDMA_STATE_PAUSE;
+ }
+
+ if (val & pause_mask)
+ return true;
+
+ return false;
+}
+
+static void udma_v2_decrement_byte_counters(struct udma_chan *uc, u32 val)
+{
+ udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
+ if (uc->config.ep_type != PSIL_EP_NATIVE)
+ udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val);
+}
+
+static void udma_v2_reset_counters(struct udma_chan *uc)
+{
+ u32 val;
+
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
+
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
+
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_PCNT_REG);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_PCNT_REG, val);
+
+ if (!uc->bchan) {
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val);
+ }
+}
+
+static int udma_v2_reset_chan(struct udma_chan *uc, bool hard)
+{
+ udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0);
+
+ /* Reset all counters */
+ udma_v2_reset_counters(uc);
+
+ /* Hard reset: re-initialize the channel to reset */
+ if (hard) {
+ struct udma_chan_config ucc_backup;
+ int ret;
+
+ memcpy(&ucc_backup, &uc->config, sizeof(uc->config));
+ uc->ud->ddev.device_free_chan_resources(&uc->vc.chan);
+
+ /* restore the channel configuration */
+ memcpy(&uc->config, &ucc_backup, sizeof(uc->config));
+ ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan);
+ if (ret)
+ return ret;
+
+ /*
+ * Setting forced teardown after forced reset helps recovering
+ * the rchan.
+ */
+ if (uc->config.dir == DMA_DEV_TO_MEM)
+ udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN |
+ UDMA_CHAN_RT_CTL_FTDOWN,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN |
+ UDMA_CHAN_RT_CTL_FTDOWN);
+ }
+ uc->state = UDMA_CHAN_IS_IDLE;
+
+ return 0;
+}
+
+static int udma_v2_start(struct udma_chan *uc)
+{
+ struct virt_dma_desc *vd = vchan_next_desc(&uc->vc);
+ struct udma_dev *ud = uc->ud;
+ int status, ret;
+
+ if (!vd) {
+ uc->desc = NULL;
+ return -ENOENT;
+ }
+
+ list_del(&vd->node);
+
+ uc->desc = to_udma_desc(&vd->tx);
+
+ /* Channel is already running and does not need reconfiguration */
+ if (udma_is_chan_running(uc) && !udma_chan_needs_reconfiguration(uc)) {
+ udma_start_desc(uc);
+ goto out;
+ }
+
+ /* Make sure that we clear the teardown bit, if it is set */
+ ud->reset_chan(uc, false);
+
+ /* Push descriptors before we start the channel */
+ udma_start_desc(uc);
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ /* Config remote TR */
+ if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
+ u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
+ PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
+ const struct udma_match_data *match_data =
+ uc->ud->match_data;
+
+ if (uc->config.enable_acc32)
+ val |= PDMA_STATIC_TR_XY_ACC32;
+ if (uc->config.enable_burst)
+ val |= PDMA_STATIC_TR_XY_BURST;
+
+ udma_chanrt_write(uc,
+ UDMA_CHAN_RT_STATIC_TR_XY_REG,
+ val);
+
+ udma_chanrt_write(uc,
+ UDMA_CHAN_RT_STATIC_TR_Z_REG,
+ PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt,
+ match_data->statictr_z_mask));
+
+ /* save the current staticTR configuration */
+ memcpy(&uc->static_tr, &uc->desc->static_tr,
+ sizeof(uc->static_tr));
+ }
+
+ udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR);
+
+ /* Poll for autopair completion */
+ ret = read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion,
+ status, status != 0, 100, 500, false, uc);
+
+ if (status <= 0)
+ return ret;
+
+ break;
+ case DMA_MEM_TO_DEV:
+ /* Config remote TR */
+ if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
+ u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
+ PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
+
+ if (uc->config.enable_acc32)
+ val |= PDMA_STATIC_TR_XY_ACC32;
+ if (uc->config.enable_burst)
+ val |= PDMA_STATIC_TR_XY_BURST;
+
+ udma_chanrt_write(uc,
+ UDMA_CHAN_RT_STATIC_TR_XY_REG,
+ val);
+
+ /* save the current staticTR configuration */
+ memcpy(&uc->static_tr, &uc->desc->static_tr,
+ sizeof(uc->static_tr));
+ }
+
+ udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR);
+
+ /* Poll for autopair completion */
+ ret = read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion,
+ status, status != 0, 100, 500, false, uc);
+
+ if (status <= 0)
+ return -ETIMEDOUT;
+
+ break;
+ case DMA_MEM_TO_MEM:
+ udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+ udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ uc->state = UDMA_CHAN_IS_ACTIVE;
+out:
+
+ return 0;
+}
+
+static int udma_v2_stop(struct udma_chan *uc)
+{
+ uc->state = UDMA_CHAN_IS_TERMINATING;
+ reinit_completion(&uc->teardown_completed);
+
+ if (uc->config.dir == DMA_DEV_TO_MEM) {
+ if (!uc->cyclic && !uc->desc)
+ udma_push_to_ring(uc, -1);
+ }
+
+ udma_chanrt_write(uc, UDMA_CHAN_RT_PEER_REG(8), UDMA_CHAN_RT_PEER_REG8_FLUSH);
+ udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN);
+
+ return 0;
+}
+
+static irqreturn_t udma_v2_udma_irq_handler(int irq, void *data)
+{
+ struct udma_chan *uc = data;
+ struct udma_dev *ud = uc->ud;
+ struct udma_desc *d;
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ k3_ringacc_ring_clear_irq(uc->rflow->r_ring);
+ break;
+ case DMA_MEM_TO_DEV:
+ case DMA_MEM_TO_MEM:
+ k3_ringacc_ring_clear_irq(uc->tchan->tc_ring);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ spin_lock(&uc->vc.lock);
+ d = uc->desc;
+ if (d) {
+ d->tr_idx = (d->tr_idx + 1) % d->sglen;
+
+ if (uc->cyclic) {
+ vchan_cyclic_callback(&d->vd);
+ } else {
+ /* TODO: figure out the real amount of data */
+ ud->decrement_byte_counters(uc, d->residue);
+ ud->start(uc);
+ vchan_cookie_complete(&d->vd);
+ }
+ }
+
+ spin_unlock(&uc->vc.lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t udma_v2_ring_irq_handler(int irq, void *data)
+{
+ struct udma_chan *uc = data;
+ struct udma_dev *ud = uc->ud;
+ struct udma_desc *d;
+ dma_addr_t paddr = 0;
+ u32 intr_status, reg;
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ intr_status = k3_ringacc_ring_get_irq_status(uc->rflow->r_ring);
+ break;
+ case DMA_MEM_TO_DEV:
+ case DMA_MEM_TO_MEM:
+ intr_status = k3_ringacc_ring_get_irq_status(uc->tchan->tc_ring);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ reg = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
+
+ if (intr_status & K3_RINGACC_RT_INT_STATUS_TR) {
+ /* check teardown status */
+ if ((reg & UDMA_CHAN_RT_CTL_TDOWN) && !(reg & UDMA_CHAN_RT_CTL_EN))
+ complete_all(&uc->teardown_completed);
+ return udma_v2_udma_irq_handler(irq, data);
+ }
+
+ if (udma_pop_from_ring(uc, &paddr) || !paddr)
+ return IRQ_HANDLED;
+
+ spin_lock(&uc->vc.lock);
+
+ /* Teardown completion message */
+ if (cppi5_desc_is_tdcm(paddr)) {
+ complete_all(&uc->teardown_completed);
+
+ if (uc->terminated_desc) {
+ udma_desc_free(&uc->terminated_desc->vd);
+ uc->terminated_desc = NULL;
+ }
+
+ if (!uc->desc)
+ ud->start(uc);
+
+ goto out;
+ }
+
+ d = udma_udma_desc_from_paddr(uc, paddr);
+
+ if (d) {
+ dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d,
+ d->desc_idx);
+ if (desc_paddr != paddr) {
+ dev_err(uc->ud->dev, "not matching descriptors!\n");
+ goto out;
+ }
+
+ if (d == uc->desc) {
+ /* active descriptor */
+ if (uc->cyclic) {
+ udma_cyclic_packet_elapsed(uc);
+ vchan_cyclic_callback(&d->vd);
+ } else {
+ if (udma_is_desc_really_done(uc, d)) {
+ ud->decrement_byte_counters(uc, d->residue);
+ ud->start(uc);
+ vchan_cookie_complete(&d->vd);
+ } else {
+ schedule_delayed_work(&uc->tx_drain.work,
+ 0);
+ }
+ }
+ } else {
+ /*
+ * terminated descriptor, mark the descriptor as
+ * completed to update the channel's cookie marker
+ */
+ dma_cookie_complete(&d->vd.tx);
+ }
+ }
+out:
+ spin_unlock(&uc->vc.lock);
+
+ return IRQ_HANDLED;
+}
+
+static int bcdma_v2_get_bchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ enum udma_tp_level tpl;
+ int ret;
+
+ if (uc->bchan) {
+ dev_dbg(ud->dev, "chan%d: already have bchan%d allocated\n",
+ uc->id, uc->bchan->id);
+ return 0;
+ }
+
+ /*
+ * Use normal channels for peripherals, and highest TPL channel for
+ * mem2mem
+ */
+ if (uc->config.tr_trigger_type)
+ tpl = 0;
+ else
+ tpl = ud->bchan_tpl.levels - 1;
+
+ uc->bchan = __udma_reserve_bchan(ud, tpl, uc->id);
+ if (IS_ERR(uc->bchan)) {
+ ret = PTR_ERR(uc->bchan);
+ uc->bchan = NULL;
+ return ret;
+ }
+ uc->chan = uc->bchan;
+ uc->tchan = uc->bchan;
+
+ return 0;
+}
+
+static int bcdma_v2_alloc_bchan_resources(struct udma_chan *uc)
+{
+ struct k3_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ int ret;
+
+ ret = bcdma_v2_get_bchan(uc);
+ if (ret)
+ return ret;
+
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, ud->match_data->chan_cnt + uc->id, -1,
+ &uc->bchan->t_ring,
+ &uc->bchan->tc_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+
+ k3_configure_chan_coherency(&uc->vc.chan, ud->asel);
+ ring_cfg.asel = ud->asel;
+ ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
+
+ ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(uc->bchan->tc_ring);
+ uc->bchan->tc_ring = NULL;
+ k3_ringacc_ring_free(uc->bchan->t_ring);
+ uc->bchan->t_ring = NULL;
+ k3_configure_chan_coherency(&uc->vc.chan, 0);
+err_ring:
+ bcdma_put_bchan(uc);
+
+ return ret;
+}
+
+static int udma_v2_alloc_tx_resources(struct udma_chan *uc)
+{
+ struct k3_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ struct udma_tchan *tchan;
+ int ring_idx, ret;
+
+ ret = udma_get_tchan(uc);
+ if (ret)
+ return ret;
+
+ tchan = uc->tchan;
+ if (tchan->tflow_id >= 0)
+ ring_idx = tchan->tflow_id;
+ else
+ ring_idx = tchan->id;
+
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
+ &tchan->t_ring,
+ &tchan->tc_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+
+ k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel);
+ ring_cfg.asel = uc->config.asel;
+ ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
+
+ ret = k3_ringacc_ring_cfg(tchan->t_ring, &ring_cfg);
+ ret |= k3_ringacc_ring_cfg(tchan->tc_ring, &ring_cfg);
+
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(uc->tchan->tc_ring);
+ uc->tchan->tc_ring = NULL;
+ k3_ringacc_ring_free(uc->tchan->t_ring);
+ uc->tchan->t_ring = NULL;
+err_ring:
+ udma_put_tchan(uc);
+
+ return ret;
+}
+
+static int udma_v2_alloc_rx_resources(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ struct k3_ring_cfg ring_cfg;
+ struct udma_rflow *rflow;
+ int fd_ring_id;
+ int ret;
+
+ ret = udma_get_rchan(uc);
+ if (ret)
+ return ret;
+
+ /* For MEM_TO_MEM we don't need rflow or rings */
+ if (uc->config.dir == DMA_MEM_TO_MEM)
+ return 0;
+
+ if (uc->config.default_flow_id >= 0)
+ ret = udma_get_rflow(uc, uc->config.default_flow_id);
+ else
+ ret = udma_get_rflow(uc, uc->rchan->id);
+
+ if (ret) {
+ ret = -EBUSY;
+ goto err_rflow;
+ }
+
+ rflow = uc->rflow;
+ if (ud->tflow_cnt)
+ fd_ring_id = ud->tflow_cnt + rflow->id;
+ else
+ fd_ring_id = uc->rchan->id;
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
+ &rflow->fd_ring, &rflow->r_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+
+ k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel);
+ ring_cfg.asel = uc->config.asel;
+ ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
+
+ ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg);
+
+ ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
+ ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg);
+
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(rflow->r_ring);
+ rflow->r_ring = NULL;
+ k3_ringacc_ring_free(rflow->fd_ring);
+ rflow->fd_ring = NULL;
+err_ring:
+ udma_put_rflow(uc);
+err_rflow:
+ udma_put_rchan(uc);
+
+ return ret;
+}
+
+static int bcdma_v2_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ struct udma_dev *ud = to_udma_dev(chan->device);
+ struct platform_device *pdev = to_platform_device(ud->dev);
+ char irq_name[10];
+ u32 irq_ring_idx;
+ int ret;
+
+ /* Only TR mode is supported */
+ uc->config.pkt_mode = false;
+
+ /*
+ * Make sure that the completion is in a known state:
+ * No teardown, the channel is idle
+ */
+ reinit_completion(&uc->teardown_completed);
+ complete_all(&uc->teardown_completed);
+ uc->state = UDMA_CHAN_IS_IDLE;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_MEM:
+ /* Non synchronized - mem to mem type of transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
+ uc->id);
+
+ ret = bcdma_v2_alloc_bchan_resources(uc);
+ if (ret)
+ return ret;
+
+ irq_ring_idx = ud->match_data->chan_cnt + uc->id;
+ break;
+ case DMA_MEM_TO_DEV:
+ /* Slave transfer synchronized - mem to dev (TX) transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
+ uc->id);
+
+ ret = udma_v2_alloc_tx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = ud->psil_base + uc->tchan->id;
+ uc->config.dst_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ irq_ring_idx = uc->tchan->id;
+
+ break;
+ case DMA_DEV_TO_MEM:
+ /* Slave transfer synchronized - dev to mem (RX) transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
+ uc->id);
+
+ ret = udma_v2_alloc_rx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
+ K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ irq_ring_idx = uc->rchan->id;
+
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+ ud->reset_chan(uc, false);
+ if (udma_is_chan_running(uc)) {
+ dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+ ret = -EBUSY;
+ goto err_res_free;
+ }
+ }
+
+ uc->dma_dev = dmaengine_get_dma_device(chan);
+ if (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type) {
+ uc->config.hdesc_size =
+ cppi5_trdesc_calc_size(sizeof(struct cppi5_tr_type15_t), 2);
+
+ uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev,
+ uc->config.hdesc_size,
+ ud->desc_align,
+ 0);
+ if (!uc->hdesc_pool) {
+ dev_err(ud->ddev.dev,
+ "Descriptor pool allocation failed\n");
+ uc->use_dma_pool = false;
+ ret = -ENOMEM;
+ goto err_res_free;
+ }
+
+ uc->use_dma_pool = true;
+ } else if (uc->config.dir != DMA_MEM_TO_MEM) {
+ uc->psil_paired = true;
+ }
+
+ snprintf(irq_name, sizeof(irq_name), "chan%u", irq_ring_idx);
+ uc->irq_num_ring = platform_get_irq_byname(pdev, irq_name);
+ if (uc->irq_num_ring < 0)
+ return uc->irq_num_ring;
+
+ ret = devm_request_irq(ud->dev, uc->irq_num_ring, udma_v2_ring_irq_handler,
+ IRQF_TRIGGER_HIGH, uc->name, uc);
+ if (ret) {
+ dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id);
+ goto err_irq_free;
+ }
+
+ udma_reset_rings(uc);
+
+ INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work,
+ udma_check_tx_completion);
+ return 0;
+
+err_irq_free:
+ uc->irq_num_ring = 0;
+ uc->irq_num_udma = 0;
+err_res_free:
+ bcdma_free_bchan_resources(uc);
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ if (uc->use_dma_pool) {
+ dma_pool_destroy(uc->hdesc_pool);
+ uc->use_dma_pool = false;
+ }
+
+ return ret;
+}
+
+static enum dma_status udma_v2_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ enum dma_status ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&uc->vc.lock, flags);
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+
+ if (!udma_is_chan_running(uc))
+ ret = DMA_COMPLETE;
+
+ if (ret == DMA_IN_PROGRESS && udma_v2_is_chan_paused(uc))
+ ret = DMA_PAUSED;
+
+ if (ret == DMA_COMPLETE || !txstate)
+ goto out;
+
+ if (uc->desc && uc->desc->vd.tx.cookie == cookie) {
+ u32 peer_bcnt = 0;
+ u32 bcnt = 0;
+ u32 residue = uc->desc->residue;
+ u32 delay = 0;
+
+ if (uc->desc->dir == DMA_MEM_TO_DEV) {
+ bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
+
+ if (uc->config.ep_type != PSIL_EP_NATIVE) {
+ peer_bcnt = udma_chanrt_read(uc, 0x810);
+
+ if (bcnt > peer_bcnt)
+ delay = bcnt - peer_bcnt;
+ }
+ } else if (uc->desc->dir == DMA_DEV_TO_MEM) {
+ bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+
+ if (uc->config.ep_type != PSIL_EP_NATIVE) {
+ peer_bcnt = udma_chanrt_read(uc, 0x810);
+
+ if (peer_bcnt > bcnt)
+ delay = peer_bcnt - bcnt;
+ }
+ } else {
+ bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+ }
+
+ if (bcnt && !(bcnt % uc->desc->residue))
+ residue = 0;
+ else
+ residue -= bcnt % uc->desc->residue;
+
+ if (!residue && (uc->config.dir == DMA_DEV_TO_MEM || !delay)) {
+ ret = DMA_COMPLETE;
+ delay = 0;
+ }
+
+ dma_set_residue(txstate, residue);
+ dma_set_in_flight_bytes(txstate, delay);
+
+ } else {
+ ret = DMA_COMPLETE;
+ }
+
+out:
+ spin_unlock_irqrestore(&uc->vc.lock, flags);
+ return ret;
+}
+
+static int udma_v2_pause(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+
+ /* pause the channel */
+ udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_PAUSE, UDMA_CHAN_RT_CTL_PAUSE);
+
+ return 0;
+}
+
+static int udma_v2_resume(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+
+ /* resume the channel */
+ udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_PAUSE, 0);
+
+ return 0;
+}
+
+static struct platform_driver bcdma_v2_driver;
+
+static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param)
+{
+ struct udma_v2_filter_param *filter_param;
+ struct psil_endpoint_config *ep_config;
+ struct udma_chan_config *ucc;
+ struct udma_chan *uc;
+ struct udma_dev *ud;
+
+ if (chan->device->dev->driver != &bcdma_v2_driver.driver)
+ return false;
+
+ uc = to_udma_chan(chan);
+ ucc = &uc->config;
+ ud = uc->ud;
+ filter_param = param;
+
+ if (filter_param->asel > 15) {
+ dev_err(ud->dev, "Invalid channel asel: %u\n",
+ filter_param->asel);
+ return false;
+ }
+
+ ucc->remote_thread_id = filter_param->remote_thread_id;
+ ucc->asel = filter_param->asel;
+ ucc->tr_trigger_type = filter_param->tr_trigger_type;
+
+ if (ucc->tr_trigger_type) {
+ ucc->dir = DMA_MEM_TO_MEM;
+ goto triggered_bchan;
+ } else if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET) {
+ ucc->dir = DMA_MEM_TO_DEV;
+ } else {
+ ucc->dir = DMA_DEV_TO_MEM;
+ }
+
+ ep_config = psil_get_ep_config(ucc->remote_thread_id);
+ if (IS_ERR(ep_config)) {
+ dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
+ ucc->remote_thread_id);
+ ucc->dir = DMA_MEM_TO_MEM;
+ ucc->remote_thread_id = -1;
+ ucc->atype = 0;
+ ucc->asel = 0;
+ return false;
+ }
+
+ ucc->pkt_mode = ep_config->pkt_mode;
+ ucc->channel_tpl = ep_config->channel_tpl;
+ ucc->notdpkt = ep_config->notdpkt;
+ ucc->ep_type = ep_config->ep_type;
+
+ if (ud->match_data->version == K3_UDMA_V2 &&
+ ep_config->mapped_channel_id >= 0) {
+ ucc->mapped_channel_id = ep_config->mapped_channel_id;
+ ucc->default_flow_id = ep_config->default_flow_id;
+ } else {
+ ucc->mapped_channel_id = -1;
+ ucc->default_flow_id = -1;
+ }
+
+ ucc->needs_epib = ep_config->needs_epib;
+ ucc->psd_size = ep_config->psd_size;
+ ucc->metadata_size =
+ (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) +
+ ucc->psd_size;
+
+ if (ucc->ep_type != PSIL_EP_NATIVE) {
+ const struct udma_match_data *match_data = ud->match_data;
+
+ if ((match_data->flags & UDMA_FLAG_PDMA_ACC32) && ep_config->pdma_acc32)
+ ucc->enable_acc32 = true;
+ else
+ ucc->enable_acc32 = false;
+
+ if ((match_data->flags & UDMA_FLAG_PDMA_BURST) && ep_config->pdma_burst)
+ ucc->enable_burst = true;
+ else
+ ucc->enable_burst = false;
+ }
+ if (ucc->pkt_mode)
+ ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
+ ucc->metadata_size, ud->desc_align);
+
+ dev_dbg(ud->dev, "chan%d: Remote thread: 0x%04x (%s)\n", uc->id,
+ ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir));
+
+ return true;
+
+triggered_bchan:
+ dev_dbg(ud->dev, "chan%d: triggered channel (type: %u)\n", uc->id,
+ ucc->tr_trigger_type);
+
+ return true;
+}
+
+static struct dma_chan *udma_v2_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct udma_dev *ud = ofdma->of_dma_data;
+ dma_cap_mask_t mask = ud->ddev.cap_mask;
+ struct udma_v2_filter_param filter_param;
+ struct dma_chan *chan;
+
+ if (ud->match_data->type == DMA_TYPE_BCDMA) {
+ if (dma_spec->args_count != 4)
+ return NULL;
+
+ filter_param.tr_trigger_type = dma_spec->args[0];
+ filter_param.trigger_param = dma_spec->args[1];
+ filter_param.remote_thread_id = dma_spec->args[2];
+ filter_param.asel = dma_spec->args[3];
+ } else {
+ if (dma_spec->args_count != 1 && dma_spec->args_count != 2)
+ return NULL;
+
+ filter_param.remote_thread_id = dma_spec->args[0];
+ filter_param.tr_trigger_type = 0;
+ if (dma_spec->args_count == 2)
+ filter_param.asel = dma_spec->args[1];
+ else
+ filter_param.asel = 0;
+ }
+
+ chan = __dma_request_channel(&mask, udma_v2_dma_filter_fn, &filter_param,
+ ofdma->of_node);
+ if (!chan) {
+ dev_err(ud->dev, "get channel fail in %s.\n", __func__);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return chan;
+}
+
+static struct udma_match_data bcdma_v2_am62l_data = {
+ .type = DMA_TYPE_BCDMA,
+ .version = K3_UDMA_V2,
+ .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
+ .enable_memcpy_support = true, /* Supported via bchan */
+ .flags = UDMA_FLAGS_J7_CLASS,
+ .statictr_z_mask = GENMASK(23, 0),
+ .burst_size = {
+ TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */
+ 0, /* No H Channels */
+ 0, /* No UH Channels */
+ },
+ .bchan_cnt = 16,
+ .chan_cnt = 128,
+ .tchan_cnt = 128,
+ .rchan_cnt = 128,
+};
+
+static const struct of_device_id udma_of_match[] = {
+ {
+ .compatible = "ti,am62l-dmss-bcdma",
+ .data = &bcdma_v2_am62l_data,
+ },
+ { /* Sentinel */ },
+};
+
+static const struct soc_device_attribute k3_soc_devices[] = {
+ { .family = "AM62LX", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, udma_of_match);
+
+static int udma_v2_get_mmrs(struct platform_device *pdev, struct udma_dev *ud)
+{
+ int i;
+
+ ud->mmrs[V2_MMR_GCFG] = devm_platform_ioremap_resource_byname(pdev,
+ v2_mmr_names[V2_MMR_GCFG]);
+ if (IS_ERR(ud->mmrs[V2_MMR_GCFG]))
+ return PTR_ERR(ud->mmrs[V2_MMR_GCFG]);
+
+ ud->bchan_cnt = ud->match_data->bchan_cnt;
+ /* There are no tchan and rchan in BCDMA_V2.
+ * Duplicate chan as tchan and rchan to keep the common code
+ * in k3-udma-common.c functional for BCDMA_V2.
+ */
+ ud->chan_cnt = ud->match_data->chan_cnt;
+ ud->tchan_cnt = ud->match_data->chan_cnt;
+ ud->rchan_cnt = ud->match_data->chan_cnt;
+ ud->rflow_cnt = ud->chan_cnt;
+
+ for (i = 1; i < V2_MMR_LAST; i++) {
+ if (i == V2_MMR_BCHANRT && ud->bchan_cnt == 0)
+ continue;
+ if (i == V2_MMR_CHANRT && ud->chan_cnt == 0)
+ continue;
+
+ ud->mmrs[i] = devm_platform_ioremap_resource_byname(pdev, v2_mmr_names[i]);
+ if (IS_ERR(ud->mmrs[i]))
+ return PTR_ERR(ud->mmrs[i]);
+ }
+
+ return 0;
+}
+
+static int udma_v2_probe(struct platform_device *pdev)
+{
+ const struct soc_device_attribute *soc;
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *match;
+ struct udma_dev *ud;
+ int ch_count, i, ret;
+
+ ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48));
+ if (ret)
+ dev_err(dev, "failed to set dma mask stuff\n");
+
+ ud = devm_kzalloc(dev, sizeof(*ud), GFP_KERNEL);
+ if (!ud)
+ return -ENOMEM;
+
+ match = of_match_node(udma_of_match, dev->of_node);
+ if (!match) {
+ dev_err(dev, "No compatible match found\n");
+ return -ENODEV;
+ }
+ ud->match_data = match->data;
+
+ ud->soc_data = ud->match_data->soc_data;
+ if (!ud->soc_data) {
+ soc = soc_device_match(k3_soc_devices);
+ if (!soc) {
+ dev_err(dev, "No compatible SoC found\n");
+ return -ENODEV;
+ }
+ ud->soc_data = soc->data;
+ }
+ // Setup function pointers
+ ud->start = udma_v2_start;
+ ud->stop = udma_v2_stop;
+ ud->reset_chan = udma_v2_reset_chan;
+ ud->decrement_byte_counters = udma_v2_decrement_byte_counters;
+ ud->bcdma_setup_sci_resources = NULL;
+
+ ret = udma_v2_get_mmrs(pdev, ud);
+ if (ret)
+ return ret;
+
+ struct k3_ringacc_init_data ring_init_data = {0};
+
+ ring_init_data.num_rings = ud->bchan_cnt + ud->chan_cnt;
+
+ ud->ringacc = k3_ringacc_dmarings_init(pdev, &ring_init_data);
+
+ if (IS_ERR(ud->ringacc))
+ return PTR_ERR(ud->ringacc);
+
+ dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask);
+
+ dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask);
+ ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic;
+
+ ud->ddev.device_config = udma_slave_config;
+ ud->ddev.device_prep_slave_sg = udma_prep_slave_sg;
+ ud->ddev.device_issue_pending = udma_issue_pending;
+ ud->ddev.device_tx_status = udma_v2_tx_status;
+ ud->ddev.device_pause = udma_v2_pause;
+ ud->ddev.device_resume = udma_v2_resume;
+ ud->ddev.device_terminate_all = udma_terminate_all;
+ ud->ddev.device_synchronize = udma_synchronize;
+#ifdef CONFIG_DEBUG_FS
+ ud->ddev.dbg_summary_show = udma_dbg_summary_show;
+#endif
+
+ ud->ddev.device_alloc_chan_resources =
+ bcdma_v2_alloc_chan_resources;
+
+ ud->ddev.device_free_chan_resources = udma_free_chan_resources;
+
+ ud->ddev.src_addr_widths = TI_UDMAC_BUSWIDTHS;
+ ud->ddev.dst_addr_widths = TI_UDMAC_BUSWIDTHS;
+ ud->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ ud->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+ ud->ddev.desc_metadata_modes = DESC_METADATA_CLIENT |
+ DESC_METADATA_ENGINE;
+ if (ud->match_data->enable_memcpy_support &&
+ !(ud->match_data->type == DMA_TYPE_BCDMA && ud->bchan_cnt == 0)) {
+ dma_cap_set(DMA_MEMCPY, ud->ddev.cap_mask);
+ ud->ddev.device_prep_dma_memcpy = udma_prep_dma_memcpy;
+ ud->ddev.directions |= BIT(DMA_MEM_TO_MEM);
+ }
+
+ ud->ddev.dev = dev;
+ ud->dev = dev;
+ ud->psil_base = ud->match_data->psil_base;
+
+ INIT_LIST_HEAD(&ud->ddev.channels);
+ INIT_LIST_HEAD(&ud->desc_to_purge);
+
+ ch_count = setup_resources(ud);
+ if (ch_count <= 0)
+ return ch_count;
+
+ spin_lock_init(&ud->lock);
+ INIT_WORK(&ud->purge_work, udma_purge_desc_work);
+
+ ud->desc_align = 64;
+ if (ud->desc_align < dma_get_cache_alignment())
+ ud->desc_align = dma_get_cache_alignment();
+
+ ret = udma_setup_rx_flush(ud);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ud->bchan_cnt; i++) {
+ struct udma_bchan *bchan = &ud->bchans[i];
+
+ bchan->id = i;
+ bchan->reg_rt = ud->mmrs[V2_MMR_BCHANRT] + i * 0x1000;
+ }
+
+ for (i = 0; i < ud->tchan_cnt; i++) {
+ struct udma_tchan *tchan = &ud->tchans[i];
+
+ tchan->id = i;
+ tchan->reg_rt = ud->mmrs[V2_MMR_CHANRT] + i * 0x1000;
+ }
+
+ for (i = 0; i < ud->rchan_cnt; i++) {
+ struct udma_rchan *rchan = &ud->rchans[i];
+
+ rchan->id = i;
+ rchan->reg_rt = ud->mmrs[V2_MMR_CHANRT] + i * 0x1000;
+ }
+
+ for (i = 0; i < ud->rflow_cnt; i++) {
+ struct udma_rflow *rflow = &ud->rflows[i];
+
+ rflow->id = i;
+ rflow->reg_rt = ud->rflow_rt + i * 0x2000;
+ }
+
+ for (i = 0; i < ch_count; i++) {
+ struct udma_chan *uc = &ud->channels[i];
+
+ uc->ud = ud;
+ uc->vc.desc_free = udma_desc_free;
+ uc->id = i;
+ uc->bchan = NULL;
+ uc->tchan = NULL;
+ uc->rchan = NULL;
+ uc->config.remote_thread_id = -1;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+ uc->config.dir = DMA_MEM_TO_MEM;
+ uc->name = devm_kasprintf(dev, GFP_KERNEL, "%s chan%d",
+ dev_name(dev), i);
+
+ vchan_init(&uc->vc, &ud->ddev);
+ /* Use custom vchan completion handling */
+ tasklet_setup(&uc->vc.task, udma_vchan_complete);
+ init_completion(&uc->teardown_completed);
+ INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion);
+ }
+
+ /* Configure the copy_align to the maximum burst size the device supports */
+ ud->ddev.copy_align = udma_get_copy_align(ud);
+
+ ret = dma_async_device_register(&ud->ddev);
+ if (ret) {
+ dev_err(dev, "failed to register slave DMA engine: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, ud);
+
+ ret = of_dma_controller_register(dev->of_node, udma_v2_of_xlate, ud);
+ if (ret) {
+ dev_err(dev, "failed to register of_dma controller\n");
+ dma_async_device_unregister(&ud->ddev);
+ }
+
+ return ret;
+}
+
+static int __maybe_unused udma_v2_pm_suspend(struct device *dev)
+{
+ struct udma_dev *ud = dev_get_drvdata(dev);
+ struct dma_device *dma_dev = &ud->ddev;
+ struct dma_chan *chan;
+ struct udma_chan *uc;
+
+ list_for_each_entry(chan, &dma_dev->channels, device_node) {
+ if (chan->client_count) {
+ uc = to_udma_chan(chan);
+ /* backup the channel configuration */
+ memcpy(&uc->backup_config, &uc->config,
+ sizeof(struct udma_chan_config));
+ dev_dbg(dev, "Suspending channel %s\n",
+ dma_chan_name(chan));
+ ud->ddev.device_free_chan_resources(chan);
+ }
+ }
+
+ return 0;
+}
+
+static int __maybe_unused udma_v2_pm_resume(struct device *dev)
+{
+ struct udma_dev *ud = dev_get_drvdata(dev);
+ struct dma_device *dma_dev = &ud->ddev;
+ struct dma_chan *chan;
+ struct udma_chan *uc;
+ int ret;
+
+ list_for_each_entry(chan, &dma_dev->channels, device_node) {
+ if (chan->client_count) {
+ uc = to_udma_chan(chan);
+ /* restore the channel configuration */
+ memcpy(&uc->config, &uc->backup_config,
+ sizeof(struct udma_chan_config));
+ dev_dbg(dev, "Resuming channel %s\n",
+ dma_chan_name(chan));
+ ret = ud->ddev.device_alloc_chan_resources(chan);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct dev_pm_ops udma_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(udma_v2_pm_suspend, udma_v2_pm_resume)
+};
+
+static struct platform_driver bcdma_v2_driver = {
+ .driver = {
+ .name = "ti-udma-v2",
+ .of_match_table = udma_of_match,
+ .suppress_bind_attrs = true,
+ .pm = &udma_pm_ops,
+ },
+ .probe = udma_v2_probe,
+};
+
+module_platform_driver(bcdma_v2_driver);
+MODULE_DESCRIPTION("Texas Instruments K3 UDMA v2 support");
+MODULE_LICENSE("GPL");
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 58cbb399bc3b2..bbf4163f407b5 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1810,6 +1810,7 @@ static struct dma_chan *udma_of_xlate(struct of_phandle_args *dma_spec,
static struct udma_match_data am654_main_data = {
.type = DMA_TYPE_UDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x1000,
.enable_memcpy_support = true,
.statictr_z_mask = GENMASK(11, 0),
@@ -1822,6 +1823,7 @@ static struct udma_match_data am654_main_data = {
static struct udma_match_data am654_mcu_data = {
.type = DMA_TYPE_UDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x6000,
.enable_memcpy_support = false,
.statictr_z_mask = GENMASK(11, 0),
@@ -1834,6 +1836,7 @@ static struct udma_match_data am654_mcu_data = {
static struct udma_match_data j721e_main_data = {
.type = DMA_TYPE_UDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x1000,
.enable_memcpy_support = true,
.flags = UDMA_FLAGS_J7_CLASS,
@@ -1847,6 +1850,7 @@ static struct udma_match_data j721e_main_data = {
static struct udma_match_data j721e_mcu_data = {
.type = DMA_TYPE_UDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x6000,
.enable_memcpy_support = false, /* MEM_TO_MEM is slow via MCU UDMA */
.flags = UDMA_FLAGS_J7_CLASS,
@@ -1876,6 +1880,7 @@ static struct udma_soc_data j721s2_bcdma_csi_soc_data = {
static struct udma_match_data am62a_bcdma_csirx_data = {
.type = DMA_TYPE_BCDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x3100,
.enable_memcpy_support = false,
.burst_size = {
@@ -1888,6 +1893,7 @@ static struct udma_match_data am62a_bcdma_csirx_data = {
static struct udma_match_data am64_bcdma_data = {
.type = DMA_TYPE_BCDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
.enable_memcpy_support = true, /* Supported via bchan */
.flags = UDMA_FLAGS_J7_CLASS,
@@ -1901,6 +1907,7 @@ static struct udma_match_data am64_bcdma_data = {
static struct udma_match_data am64_pktdma_data = {
.type = DMA_TYPE_PKTDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x1000,
.enable_memcpy_support = false, /* PKTDMA does not support MEM_TO_MEM */
.flags = UDMA_FLAGS_J7_CLASS,
@@ -1914,6 +1921,7 @@ static struct udma_match_data am64_pktdma_data = {
static struct udma_match_data j721s2_bcdma_csi_data = {
.type = DMA_TYPE_BCDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x2000,
.enable_memcpy_support = false,
.burst_size = {
@@ -1926,6 +1934,7 @@ static struct udma_match_data j721s2_bcdma_csi_data = {
static struct udma_match_data j722s_bcdma_csi_data = {
.type = DMA_TYPE_BCDMA,
+ .version = K3_UDMA_V1,
.psil_base = 0x3100,
.enable_memcpy_support = false,
.burst_size = {
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index 6a95eb1ece064..771088462f80d 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -28,6 +28,11 @@
#define UDMA_CHAN_RT_SWTRIG_REG 0x8
#define UDMA_CHAN_RT_STDATA_REG 0x80
+#define UDMA_CHAN_RT_STATIC_TR_XY_REG 0x800
+#define UDMA_CHAN_RT_STATIC_TR_Z_REG 0x804
+#define UDMA_CHAN_RT_PERIPH_BCNT_REG 0x810
+#define UDMA_CHAN_RT_PDMA_STATE_REG 0x80c
+
#define UDMA_CHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4))
#define UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG \
UDMA_CHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */
@@ -67,8 +72,16 @@
#define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
#define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
#define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
+#define UDMA_CHAN_RT_CTL_AUTOPAIR BIT(23)
+#define UDMA_CHAN_RT_CTL_PAIR_TIMEOUT BIT(17)
+#define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16)
#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
+/* UDMA_CHAN_RT_PDMA_STATE_REG */
+#define UDMA_CHAN_RT_PDMA_STATE_IN_EVT BIT(31)
+#define UDMA_CHAN_RT_PDMA_STATE_TDOWN BIT(30)
+#define UDMA_CHAN_RT_PDMA_STATE_PAUSE BIT(29)
+
/* UDMA_CHAN_RT_PEER_RT_EN_REG */
#define UDMA_PEER_RT_EN_ENABLE BIT(31)
#define UDMA_PEER_RT_EN_TEARDOWN BIT(30)
@@ -99,6 +112,9 @@
*/
#define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask))
+/* UDMA_CHAN_RT_PEER_REG(8) */
+#define UDMA_CHAN_RT_PEER_REG8_FLUSH 0x09000000
+
/* Address Space Select */
#define K3_ADDRESS_ASEL_SHIFT 48
@@ -204,6 +220,11 @@ enum k3_dma_type {
DMA_TYPE_PKTDMA,
};
+enum k3_dma_version {
+ K3_UDMA_V1 = 0,
+ K3_UDMA_V2,
+};
+
enum udma_mmr {
MMR_GCFG = 0,
MMR_BCHANRT,
@@ -212,6 +233,13 @@ enum udma_mmr {
MMR_LAST,
};
+enum udma_v2_mmr {
+ V2_MMR_GCFG = 0,
+ V2_MMR_BCHANRT,
+ V2_MMR_CHANRT,
+ V2_MMR_LAST,
+};
+
struct udma_filter_param {
int remote_thread_id;
u32 atype;
@@ -219,6 +247,13 @@ struct udma_filter_param {
u32 tr_trigger_type;
};
+struct udma_v2_filter_param {
+ u32 tr_trigger_type;
+ u32 trigger_param;
+ int remote_thread_id;
+ u32 asel;
+};
+
struct udma_tchan {
void __iomem *reg_rt;
@@ -230,17 +265,13 @@ struct udma_tchan {
};
#define udma_bchan udma_tchan
+#define udma_rchan udma_tchan
struct udma_rflow {
int id;
struct k3_ring *fd_ring; /* Free Descriptor ring */
struct k3_ring *r_ring; /* Receive ring */
-};
-
-struct udma_rchan {
void __iomem *reg_rt;
-
- int id;
};
struct udma_oes_offsets {
@@ -262,12 +293,19 @@ struct udma_oes_offsets {
struct udma_match_data {
enum k3_dma_type type;
+ enum k3_dma_version version;
u32 psil_base;
bool enable_memcpy_support;
u32 flags;
u32 statictr_z_mask;
u8 burst_size[3];
struct udma_soc_data *soc_data;
+ u32 bchan_cnt;
+ u32 chan_cnt;
+ u32 tchan_cnt;
+ u32 rchan_cnt;
+ u32 tflow_cnt;
+ u32 rflow_cnt;
};
struct udma_soc_data {
@@ -302,6 +340,7 @@ struct udma_dev {
struct dma_device ddev;
struct device *dev;
void __iomem *mmrs[MMR_LAST];
+ void __iomem *rflow_rt;
const struct udma_match_data *match_data;
const struct udma_soc_data *soc_data;
@@ -322,12 +361,14 @@ struct udma_dev {
struct udma_rx_flush rx_flush;
int bchan_cnt;
+ int chan_cnt;
int tchan_cnt;
int echan_cnt;
int rchan_cnt;
int rflow_cnt;
int tflow_cnt;
unsigned long *bchan_map;
+ unsigned long *chan_map;
unsigned long *tchan_map;
unsigned long *rchan_map;
unsigned long *rflow_gp_map;
@@ -336,6 +377,7 @@ struct udma_dev {
unsigned long *tflow_map;
struct udma_bchan *bchans;
+ struct udma_tchan *chans;
struct udma_tchan *tchans;
struct udma_rchan *rchans;
struct udma_rflow *rflows;
@@ -430,6 +472,7 @@ struct udma_chan {
char *name;
struct udma_bchan *bchan;
+ struct udma_tchan *chan;
struct udma_tchan *tchan;
struct udma_rchan *rchan;
struct udma_rflow *rflow;
@@ -499,51 +542,33 @@ static inline void udma_update_bits(void __iomem *base, int reg,
writel(tmp, base + reg);
}
-/* TCHANRT */
-static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg)
-{
- if (!uc->tchan)
- return 0;
- return udma_read(uc->tchan->reg_rt, reg);
-}
-
-static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 val)
-{
- if (!uc->tchan)
- return;
- udma_write(uc->tchan->reg_rt, reg, val);
+#define _UDMA_REG_ACCESS(channel) \
+static inline u32 udma_##channel##rt_read(struct udma_chan *uc, int reg) \
+{ \
+ if (!uc->channel) \
+ return 0; \
+ return udma_read(uc->channel->reg_rt, reg); \
+} \
+\
+static inline void udma_##channel##rt_write(struct udma_chan *uc, int reg, u32 val) \
+{ \
+ if (!uc->channel) \
+ return; \
+ udma_write(uc->channel->reg_rt, reg, val); \
+} \
+\
+static inline void udma_##channel##rt_update_bits(struct udma_chan *uc, int reg, \
+ u32 mask, u32 val) \
+{ \
+ if (!uc->channel) \
+ return; \
+ udma_update_bits(uc->channel->reg_rt, reg, mask, val); \
}
-static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg,
- u32 mask, u32 val)
-{
- if (!uc->tchan)
- return;
- udma_update_bits(uc->tchan->reg_rt, reg, mask, val);
-}
-
-/* RCHANRT */
-static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg)
-{
- if (!uc->rchan)
- return 0;
- return udma_read(uc->rchan->reg_rt, reg);
-}
-
-static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 val)
-{
- if (!uc->rchan)
- return;
- udma_write(uc->rchan->reg_rt, reg, val);
-}
-
-static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg,
- u32 mask, u32 val)
-{
- if (!uc->rchan)
- return;
- udma_update_bits(uc->rchan->reg_rt, reg, mask, val);
-}
+_UDMA_REG_ACCESS(chan);
+_UDMA_REG_ACCESS(bchan);
+_UDMA_REG_ACCESS(tchan);
+_UDMA_REG_ACCESS(rchan);
static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d,
int idx)
diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ringacc.h
index 9f2d141c988bd..1ac01b97dd923 100644
--- a/include/linux/soc/ti/k3-ringacc.h
+++ b/include/linux/soc/ti/k3-ringacc.h
@@ -10,6 +10,9 @@
#include <linux/types.h>
+#define K3_RINGACC_RT_INT_STATUS_COMPLETE BIT(0)
+#define K3_RINGACC_RT_INT_STATUS_TR BIT(2)
+
struct device_node;
/**
--
2.53.0
^ permalink raw reply related
* [PATCH] arm64: dts: ti: k3-j721s2-som-p0: add bootph-pre-ram property to pmic@4c
From: Thomas Richard (TI) @ 2026-04-28 8:53 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Thomas Petazzoni, linux-arm-kernel, devicetree, linux-kernel,
gregory.clement, richard.genoud, u-kumar1, a-kumar2,
Thomas Richard (TI)
On j721s2, pmic@4c is needed to exit the DDR from retention after
suspend-to-ram. Add bootph-pre-ram property to make pmic@4c available to
the bootloader in the phase that sets up the DDR.
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 12a38dd1514b..a19e535f4946 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -250,6 +250,7 @@ buckb1: buck1 {
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
+ bootph-pre-ram;
};
buckb2: buck2 {
---
base-commit: 59b04cb2325c07ddc1cc7d984bd8c8f89f161746
change-id: 20260427-k3-j721s2-som-bootph-pre-ram-pmic-4c-744fb90b05a3
Best regards,
--
Thomas Richard (TI) <thomas.richard@bootlin.com>
^ permalink raw reply related
* [PATCH v6 18/19] dmaengine: ti: k3-udma-v2: Update glue layer to support PKTDMA V2
From: Sai Sree Kartheek Adivi @ 2026-04-28 8:51 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, vigneshr,
Frank.li, s-adivi
Cc: r-sharma3, gehariprasath
In-Reply-To: <20260428085202.1724548-1-s-adivi@ti.com>
Update glue layer to support PKTDMA V2 for non DMAengine users.
The updates include
- Handling absence of TISCI
- Direct IRQs
- Autopair: Lack of PSIL pair.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/Kconfig | 2 +-
drivers/dma/ti/k3-udma-glue.c | 91 ++++++++++++++++++++++----------
drivers/dma/ti/k3-udma-private.c | 27 ++++++++--
drivers/dma/ti/k3-udma.h | 2 +
4 files changed, 89 insertions(+), 33 deletions(-)
diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig
index 40713bd1e8e9b..ada2ea8aca4b0 100644
--- a/drivers/dma/ti/Kconfig
+++ b/drivers/dma/ti/Kconfig
@@ -68,7 +68,7 @@ config TI_K3_UDMA_COMMON
config TI_K3_UDMA_GLUE_LAYER
tristate "Texas Instruments UDMA Glue layer for non DMAengine users"
depends on ARCH_K3 || COMPILE_TEST
- depends on TI_K3_UDMA
+ depends on TI_K3_UDMA || TI_K3_UDMA_V2
help
Say y here to support the K3 NAVSS DMA glue interface
If unsure, say N.
diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c
index f87d244cc2d67..8e38b521cfecf 100644
--- a/drivers/dma/ti/k3-udma-glue.c
+++ b/drivers/dma/ti/k3-udma-glue.c
@@ -244,6 +244,9 @@ static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
const struct udma_tisci_rm *tisci_rm = tx_chn->common.tisci_rm;
struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
+ if (!tisci_rm->tisci)
+ return 0;
+
memset(&req, 0, sizeof(req));
req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |
@@ -502,21 +505,26 @@ int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
{
int ret;
- ret = xudma_navss_psil_pair(tx_chn->common.udmax,
- tx_chn->common.src_thread,
- tx_chn->common.dst_thread);
- if (ret) {
- dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret);
- return ret;
- }
+ if (tx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ ret = xudma_navss_psil_pair(tx_chn->common.udmax,
+ tx_chn->common.src_thread,
+ tx_chn->common.dst_thread);
+ if (ret) {
+ dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret);
+ return ret;
+ }
- tx_chn->psil_paired = true;
+ tx_chn->psil_paired = true;
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+ } else {
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN);
+ }
k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en");
return 0;
@@ -682,7 +690,6 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID;
- req.nav_id = tisci_rm->tisci_dev_id;
req.index = rx_chn->udma_rchan_id;
req.rx_fetch_size = rx_chn->common.hdesc_size >> 2;
/*
@@ -702,11 +709,18 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
req.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
req.rx_atype = rx_chn->common.atype_asel;
+ if (!tisci_rm->tisci) {
+ // TODO: look at the chan settings
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CFG_REG,
+ UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_PAUSE);
+ return 0;
+ }
+
+ req.nav_id = tisci_rm->tisci_dev_id;
ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
if (ret)
dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n",
- rx_chn->udma_rchan_id, ret);
-
+ rx_chn->udma_rchan_id, ret);
return ret;
}
@@ -755,8 +769,11 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
}
if (xudma_is_pktdma(rx_chn->common.udmax)) {
- rx_ringfdq_id = flow->udma_rflow_id +
+ if (tisci_rm->tisci)
+ rx_ringfdq_id = flow->udma_rflow_id +
xudma_get_rflow_ring_offset(rx_chn->common.udmax);
+ else
+ rx_ringfdq_id = flow->udma_rflow_id;
rx_ring_id = 0;
} else {
rx_ring_id = flow_cfg->ring_rxq_id;
@@ -803,6 +820,13 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
}
+ if (!tisci_rm->tisci) {
+ xudma_rflowrt_write(flow->udma_rflow, UDMA_RX_FLOWRT_RFA,
+ UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_PAUSE);
+ rx_chn->flows_ready++;
+ return 0;
+ }
+
memset(&req, 0, sizeof(req));
req.valid_params =
@@ -1307,6 +1331,9 @@ int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
if (!rx_chn->remote)
return -EINVAL;
+ if (!tisci_rm->tisci)
+ return 0;
+
rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx);
rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
@@ -1348,6 +1375,9 @@ int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
if (!rx_chn->remote)
return -EINVAL;
+ if (!tisci_rm->tisci)
+ return 0;
+
memset(&req, 0, sizeof(req));
req.valid_params =
TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
@@ -1383,21 +1413,26 @@ int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
if (rx_chn->flows_ready < rx_chn->flow_num)
return -EINVAL;
- ret = xudma_navss_psil_pair(rx_chn->common.udmax,
- rx_chn->common.src_thread,
- rx_chn->common.dst_thread);
- if (ret) {
- dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret);
- return ret;
- }
+ if (rx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ ret = xudma_navss_psil_pair(rx_chn->common.udmax,
+ rx_chn->common.src_thread,
+ rx_chn->common.dst_thread);
+ if (ret) {
+ dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret);
+ return ret;
+ }
- rx_chn->psil_paired = true;
+ rx_chn->psil_paired = true;
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
+ } else {
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN);
+ }
k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en");
return 0;
diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-private.c
index 44c097fff5ee6..619ddd15dbedf 100644
--- a/drivers/dma/ti/k3-udma-private.c
+++ b/drivers/dma/ti/k3-udma-private.c
@@ -3,6 +3,10 @@
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_platform.h>
@@ -165,6 +169,7 @@ void xudma_##res##rt_write(struct udma_##res *p, int reg, u32 val) \
EXPORT_SYMBOL(xudma_##res##rt_write)
XUDMA_RT_IO_FUNCTIONS(tchan);
XUDMA_RT_IO_FUNCTIONS(rchan);
+XUDMA_RT_IO_FUNCTIONS(rflow);
int xudma_is_pktdma(struct udma_dev *ud)
{
@@ -174,16 +179,30 @@ EXPORT_SYMBOL(xudma_is_pktdma);
int xudma_pktdma_tflow_get_irq(struct udma_dev *ud, int udma_tflow_id)
{
- const struct udma_oes_offsets *oes = &ud->soc_data->oes;
+ if (ud->match_data->version == K3_UDMA_V1) {
+ const struct udma_oes_offsets *oes = &ud->soc_data->oes;
- return msi_get_virq(ud->dev, udma_tflow_id + oes->pktdma_tchan_flow);
+ return msi_get_virq(ud->dev, udma_tflow_id + oes->pktdma_tchan_flow);
+ }
+ struct platform_device *pdev = to_platform_device(ud->dev);
+ char irq_name[10];
+
+ snprintf(irq_name, sizeof(irq_name), "chan%u", udma_tflow_id);
+ return platform_get_irq_byname(pdev, irq_name);
}
EXPORT_SYMBOL(xudma_pktdma_tflow_get_irq);
int xudma_pktdma_rflow_get_irq(struct udma_dev *ud, int udma_rflow_id)
{
- const struct udma_oes_offsets *oes = &ud->soc_data->oes;
+ if (ud->match_data->version == K3_UDMA_V1) {
+ const struct udma_oes_offsets *oes = &ud->soc_data->oes;
+
+ return msi_get_virq(ud->dev, udma_rflow_id + oes->pktdma_rchan_flow);
+ }
+ struct platform_device *pdev = to_platform_device(ud->dev);
+ char irq_name[10];
- return msi_get_virq(ud->dev, udma_rflow_id + oes->pktdma_rchan_flow);
+ snprintf(irq_name, sizeof(irq_name), "chan%u", udma_rflow_id);
+ return platform_get_irq_byname(pdev, irq_name);
}
EXPORT_SYMBOL(xudma_pktdma_rflow_get_irq);
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index 642d8fc8f3175..8afcd69bc0d76 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -743,6 +743,8 @@ u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg);
void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val);
bool xudma_rflow_is_gp(struct udma_dev *ud, int id);
int xudma_get_rflow_ring_offset(struct udma_dev *ud);
+u32 xudma_rflowrt_read(struct udma_rflow *rflow, int reg);
+void xudma_rflowrt_write(struct udma_rflow *rflow, int reg, u32 val);
int xudma_is_pktdma(struct udma_dev *ud);
--
2.53.0
^ permalink raw reply related
* [PATCH v6 19/19] dmaengine: ti: k3-udma: Validate resource ID and fix logging in reservation
From: Sai Sree Kartheek Adivi @ 2026-04-28 8:51 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, vigneshr,
Frank.li, s-adivi
Cc: r-sharma3, gehariprasath
In-Reply-To: <20260428085202.1724548-1-s-adivi@ti.com>
The `__udma_reserve_##res` macro currently lacks a bounds check for
the provided `id`. If a caller passes an ID exceeding the resource
count (`ud->res##_cnt`), `test_bit()` performs an out-of-bounds
memory access on the bitmap.
Additionally, the macro returns `-ENOENT` when a resource is already
in use, which is semantically incorrect. The logging logic is also
broken, printing the literal "res##<id>" instead of the resource
name.
Update the macro to:
1. Validate `id` against `ud->res##_cnt` and return `-EINVAL` if out
of bounds.
2. Return `-EBUSY` instead of `-ENOENT` when a resource is already
reserved, correctly reflecting the resource state.
3. Use the stringification operator `#res` to correctly print the
resource name (e.g., "tchan") in error messages.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/k3-udma-common.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index 304dad59bf183..92b14b0b620a8 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -2010,9 +2010,14 @@ struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
int id) \
{ \
if (id >= 0) { \
+ if (id >= ud->res##_cnt) { \
+ dev_err(ud->dev, \
+ #res " id %d is out of bounds.\n", id); \
+ return ERR_PTR(-EINVAL); \
+ } \
if (test_bit(id, ud->res##_map)) { \
- dev_err(ud->dev, "res##%d is in use\n", id); \
- return ERR_PTR(-ENOENT); \
+ dev_err(ud->dev, #res "%d is in use\n", id); \
+ return ERR_PTR(-EBUSY); \
} \
} else { \
int start; \
--
2.53.0
^ permalink raw reply related
* [PATCH v6 14/19] dt-bindings: dma: ti: Add K3 PKTDMA V2
From: Sai Sree Kartheek Adivi @ 2026-04-28 8:51 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, vigneshr,
Frank.li, s-adivi
Cc: r-sharma3, gehariprasath
In-Reply-To: <20260428085202.1724548-1-s-adivi@ti.com>
New binding document for
Texas Instruments K3 Packet DMA (PKTDMA) V2.
PKTDMA V2 is introduced as part of AM62L.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
.../bindings/dma/ti/ti,am62l-dmss-pktdma.yaml | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-pktdma.yaml
diff --git a/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-pktdma.yaml b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-pktdma.yaml
new file mode 100644
index 0000000000000..32bcb0ba502c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-pktdma.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/ti/ti,am62l-dmss-pktdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 DMSS PKTDMA V2
+
+maintainers:
+ - Sai Sree Kartheek Adivi <s-adivi@ti.com>
+
+description:
+ The PKTDMA V2 is intended to perform similar functions as the packet mode
+ channels of K3 UDMA-P. PKTDMA V2 only includes Split channels to service
+ PSI-L based peripherals.
+
+ The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
+ with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
+ legacy peripheral.
+
+allOf:
+ - $ref: /schemas/dma/dma-controller.yaml#
+
+properties:
+ compatible:
+ const: ti,am62l-dmss-pktdma
+
+ reg:
+ items:
+ - description: Packet DMA Control & Status
+ - description: Channel Realtime
+ - description: Ring Realtime
+
+ reg-names:
+ items:
+ - const: gcfg
+ - const: chanrt
+ - const: ringrt
+
+ "#address-cells":
+ const: 0
+
+ "#dma-cells":
+ const: 2
+ description: |
+ cell 1: Channel identification for the peripheral
+ PSI-L thread ID of the remote (to PKTDMA) end.
+ Valid ranges for thread ID depends on the data movement direction:
+ for source thread IDs (rx): 0 - 0x7fff
+ for destination thread IDs (tx): 0x8000 - 0xffff
+
+ Please refer to the device documentation for the PSI-L thread map and
+ also the PSI-L peripheral chapter for the correct thread ID.
+
+ cell 2: ASEL value for the channel
+
+ interrupts:
+ minItems: 1
+ maxItems: 112
+ description:
+ Interrupts for DMA channels.
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 112
+ items:
+ pattern: "^chan[0-9]+$"
+ description:
+ The name of the interrupt corresponding to the DMA channel.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#address-cells"
+ - "#dma-cells"
+ - interrupts
+ - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ dma-controller@485c0000 {
+ compatible = "ti,am62l-dmss-pktdma";
+ reg = <0x485c0000 0x4000>,
+ <0x48900000 0x80000>,
+ <0x47200000 0x100000>;
+ reg-names = "gcfg", "chanrt", "ringrt";
+
+ #address-cells = <0>;
+ #dma-cells = <2>;
+
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "chan64", "chan65";
+ };
--
2.53.0
^ permalink raw reply related
* [PATCH v5 00/29] media: platform: rga: Add RGA3 support
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne, Michael Olbrich
This series adds support for the Raster Graphic Acceleration 3 (RGA3)
peripheral, which is included in the RK3588 SoC. The RK3588
contains one RGA2-Enhanced core (which is already implemented by the
rockchip rga driver) and two independent RGA3 cores. They feature
a similar functionality of scaling, cropping and rotating of up to two input
images into one output image. Key differences of the RGA3 are:
- supports 10bit YUV output formats
- supports 8x8 tiles and FBCD as inputs and outputs
- supports BT2020 color space conversion
- max output resolution of (8192-64)x(8192-64)
- MMU can map up to 32G DDR RAM
- fully planar formats (3 planes) are not supported
- max scale up/down factor of 8 (RGA2 allows up to 16)
This patch set adds support for one RGA3 core in the existing
rga m2m driver. The feature set of the PR is limited to scaling,
format and color space conversions between common 8bit RGB/YUV formats.
This already allows a practical usage of the RGA3.
During testing it has been noted that the scaling of the hardware is
slightly incorrect. A test conversion of 128x128 RGBA to 256x256 RGBA
causes a slight shift to the bottom right. The shift is suddle, as it seems
that the image is shifted by about 2px down and right and then cropped to
it's final size (probably caused by the source sampling).
The same behavior has been observed when using the vendor driver
with the librga library.
Furthermore comparing the RGA3 conversion with the GStreamer
videoconvertscale element, the chroma-site is different. A quick testing
didn't reveal a chroma-site that creates the same image with the
GStreamer Element. Also when converting from YUV to RGB the RGB values
differ by 1 or 2. This doesn't seem to be a colorspace conversion issue
but rather a slightly different precision on the calculation.
This was tested on a Radxa Rock 5T. Around 80 fps were measured when
scaling and converting from RGBA 480x360 to NV12 3840x2160 in a single
gstreamer pipeline. Format conversions were tested with a single
gstreamer pipeline converting a fixed input to a given input format.
Afterwards it's piped through the RGA3 and the result is converted back
to rgba and compared against a given hash value (generated after
comparing the output manually to the input).
The patchset also fixes the failing v4l2-compliance tests due to the
missing colorimetry propagation from output to capture:
v4l2-compliance 1.32.0, 64 bits, 64-bit time_t
...
Card type : rga2
...
Total for rockchip-rga device /dev/video0: 48, Succeeded: 48, Failed: 0, Warnings: 0
v4l2-compliance 1.32.0, 64 bits, 64-bit time_t
...
Card type : rga3
...
Total for rockchip-rga device /dev/video1: 48, Succeeded: 48, Failed: 0, Warnings: 0
To distinguish the RGA2 core from the RGA3 cores the Card type is set
accordingly. Scheduling operations between both RGA3 cores to double
the possible frame rate might be a future improvement. Until then
additional RGA3 cores are disabled to only provide one video device to
the user space. This prevents a potential ABI breakage when multi core
support is implemented.
The DTS change at the end is just as a preview, as this series targets
media/next. After it's merged the DTS change will be sent as a new
patch not targeting media.
Patch 1 updates the dtb bindings doc to support the RGA3
Patch 2-5 extend v4l2 common functionality
Patch 6-10 are general cleanups
Patch 11-27 prepare the rga driver for the RGA3
Patch 28 adds RGA3 support to the rga driver
Patch 29 dtsi additions for the RGA3
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
Changes in v5:
- Fixed cmdbuf allocation size being only a quarter
- Fixed streamon cmdbuf preparation to not set
rotation/flipping which prevents changing it during streaming
- Link to v4: https://patch.msgid.link/20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de
Changes in v4:
- Add Nicolas to Cc for potential reviews and Sebastian for the nice
RK3588 mainline status table
- Improved single memory plane y stride alignment adjustments
- Adjusted scaling inaccuracy description
- Dropped required iommu property from the binding yaml
- Fixed binding yaml indentation
- Link to v3: https://lore.kernel.org/r/20260127-spu-rga3-v3-0-77b273067beb@pengutronix.de
Changes in v3:
- Add iommus property to the dtb bindings documentation
- Drop interrupt name from the dtsi
- Added v4l2_format_info for missing 2 byte RGB formats
- Fixed incorrect dt node reference in the binding patch commit message
- Removed now unused depth member of rga_frame
- Replaced RGA3 semi planar bool with v4l2_format_info check
- Calculated x_div/y_div variables instead of storing them
- Limited width/height to even values for YUV formats
- Support all 4 CSC modes: BT601L, BT601F, BT709L, BT2020L
- Note slightly incorrect scaling by the hardware
- Fix stride alignment to bytes
- Use early returns in rga-buf init/cleanup
- Fix incorrect devm_clk_bulk_get with devm_clk_bulk_get_all
- Don't enforce max scaling factor in try_fmt (only in s_fmt)
- Merge single register editing RGA3 functions into the other functions
- Link to v2: https://lore.kernel.org/r/20251203-spu-rga3-v2-0-989a67947f71@pengutronix.de
Changes in v2:
- Removed overclocking (assigning higher clock speeds in the dts)
- Disable the second RGA3 core
- Improved RGA3 feature documentation and code comments
- Don't write the whole command buffer in each frame
- Don't announce CIDs for the RGA3 and error out on s_selection
- Check the max scaling factor of 16 (RGA2) and 8 (RGA3)
- Move stride alignment and alpha checking to v4l2 common
- Register the interrupt as shared for an external IOMMU
- Add IOMMU patch as dependency to fix sporadic hangups
- Link to v1: https://lore.kernel.org/r/20251007-spu-rga3-v1-0-36ad85570402@pengutronix.de
To: Jacob Chen <jacob-chen@iotwrt.com>
To: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
To: Mauro Carvalho Chehab <mchehab@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
To: Hans Verkuil <hverkuil@kernel.org>
Cc: linux-media@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
Michael Olbrich (1):
media: rockchip: rga: share the interrupt when an external iommu is used
Sven Püschel (28):
media: dt-bindings: media: rockchip-rga: add rockchip,rk3588-rga3
media: v4l2-common: sort RGB formats in v4l2_format_info
media: v4l2-common: add missing 1 and 2 byte RGB formats to v4l2_format_info
media: v4l2-common: add has_alpha to v4l2_format_info
media: v4l2-common: add v4l2_fill_pixfmt_mp_aligned helper
media: rockchip: rga: fix too small buffer size
media: rockchip: rga: use clk_bulk api
media: rockchip: rga: use stride for offset calculation
media: rockchip: rga: remove redundant rga_frame variables
media: rockchip: rga: announce and sync colorimetry
media: rockchip: rga: move hw specific parts to a dedicated struct
media: rockchip: rga: avoid odd frame sizes for YUV formats
media: rockchip: rga: calculate x_div/y_div using v4l2_format_info
media: rockchip: rga: move cmdbuf to rga_ctx
media: rockchip: rga: align stride to 4 bytes
media: rockchip: rga: split flip and rotate into separate function
media: rockchip: rga: prepare cmdbuf on streamon
media: rockchip: rga: check scaling factor
media: rockchip: rga: use card type to specify rga type
media: rockchip: rga: change offset to dma_addresses
media: rockchip: rga: support external iommus
media: rockchip: rga: remove size from rga_frame
media: rockchip: rga: remove stride from rga_frame
media: rockchip: rga: move rga_fmt to rga-hw.h
media: rockchip: rga: add feature flags
media: rockchip: rga: disable multi-core support
media: rockchip: rga: add rga3 support
arm64: dts: rockchip: add rga3 dt nodes
.../devicetree/bindings/media/rockchip-rga.yaml | 10 +-
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 44 ++
drivers/media/platform/rockchip/rga/Makefile | 2 +-
drivers/media/platform/rockchip/rga/rga-buf.c | 61 ++-
drivers/media/platform/rockchip/rga/rga-hw.c | 413 ++++++++++-----
drivers/media/platform/rockchip/rga/rga-hw.h | 16 +-
drivers/media/platform/rockchip/rga/rga.c | 577 ++++++++++-----------
drivers/media/platform/rockchip/rga/rga.h | 85 +--
drivers/media/platform/rockchip/rga/rga3-hw.c | 507 ++++++++++++++++++
drivers/media/platform/rockchip/rga/rga3-hw.h | 192 +++++++
drivers/media/v4l2-core/v4l2-common.c | 128 +++--
include/media/v4l2-common.h | 6 +
12 files changed, 1514 insertions(+), 527 deletions(-)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20251001-spu-rga3-8a00e018b120
prerequisite-change-id: 20251126-spu-iommudtefix-cd0c5244c74a:v1
prerequisite-patch-id: 10c6c977c0f71400931941b42da73adcaf63e810
Best regards,
--
Sven Püschel <s.pueschel@pengutronix.de>
^ permalink raw reply
* [PATCH v5 22/29] media: rockchip: rga: share the interrupt when an external iommu is used
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Michael Olbrich, Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
From: Michael Olbrich <m.olbrich@pengutronix.de>
The RGA3 and the corresponding iommu share the interrupt. So in that
case, request a shared interrupt so that the iommu driver can request
it as well.
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index 5bdc8dc51ab68..eb7b211a99e66 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -761,7 +761,8 @@ static int rga_probe(struct platform_device *pdev)
goto err_put_clk;
}
- ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
+ ret = devm_request_irq(rga->dev, irq, rga_isr,
+ rga_has_internal_iommu(rga) ? 0 : IRQF_SHARED,
dev_name(rga->dev), rga);
if (ret < 0) {
dev_err(rga->dev, "failed to request irq\n");
--
2.54.0
^ permalink raw reply related
* [PATCH v5 09/29] media: rockchip: rga: remove redundant rga_frame variables
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Remove the redundant rga_frame variables width, height and color space.
The value of these variables is already contained in the pix member
of rga_frame. The code also keeps these values in sync. Therefore drop
them in favor of the existing pix member.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-buf.c | 6 ++---
drivers/media/platform/rockchip/rga/rga-hw.c | 6 ++---
drivers/media/platform/rockchip/rga/rga.c | 32 ++++++++++-----------------
drivers/media/platform/rockchip/rga/rga.h | 5 -----
4 files changed, 18 insertions(+), 31 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-buf.c b/drivers/media/platform/rockchip/rga/rga-buf.c
index 65fc0d5b4aa10..ffc6162b2e681 100644
--- a/drivers/media/platform/rockchip/rga/rga-buf.c
+++ b/drivers/media/platform/rockchip/rga/rga-buf.c
@@ -103,10 +103,10 @@ static int get_plane_offset(struct rga_frame *f,
if (plane == 0)
return 0;
if (plane == 1)
- return stride * f->height;
+ return stride * f->pix.height;
if (plane == 2)
- return stride * f->height +
- (stride * f->height / info->hdiv / info->vdiv);
+ return stride * f->pix.height +
+ (stride * f->pix.height / info->hdiv / info->vdiv);
return -EINVAL;
}
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index d1618bb247501..ec6c17504ca15 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -53,7 +53,7 @@ rga_get_addr_offset(struct rga_frame *frm, struct rga_addr_offset *offset,
x_div = frm->fmt->x_div;
y_div = frm->fmt->y_div;
uv_stride = frm->stride / x_div;
- pixel_width = frm->stride / frm->width;
+ pixel_width = frm->stride / frm->pix.width;
lt->y_off = offset->y_off + y * frm->stride + x * pixel_width;
lt->u_off = offset->u_off + (y / y_div) * uv_stride + x / x_div;
@@ -191,7 +191,7 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
if (RGA_COLOR_FMT_IS_YUV(ctx->in.fmt->hw_format) &&
RGA_COLOR_FMT_IS_RGB(ctx->out.fmt->hw_format)) {
- switch (ctx->in.colorspace) {
+ switch (ctx->in.pix.colorspace) {
case V4L2_COLORSPACE_REC709:
src_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
break;
@@ -203,7 +203,7 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
if (RGA_COLOR_FMT_IS_RGB(ctx->in.fmt->hw_format) &&
RGA_COLOR_FMT_IS_YUV(ctx->out.fmt->hw_format)) {
- switch (ctx->out.colorspace) {
+ switch (ctx->out.pix.colorspace) {
case V4L2_COLORSPACE_REC709:
dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
break;
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index c07207edffdb6..ca8d8a53dc251 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -329,9 +329,6 @@ static struct rga_fmt *rga_fmt_find(u32 pixelformat)
}
static struct rga_frame def_frame = {
- .width = DEFAULT_WIDTH,
- .height = DEFAULT_HEIGHT,
- .colorspace = V4L2_COLORSPACE_DEFAULT,
.crop.left = 0,
.crop.top = 0,
.crop.width = DEFAULT_WIDTH,
@@ -363,9 +360,9 @@ static int rga_open(struct file *file)
ctx->out = def_frame;
v4l2_fill_pixfmt_mp(&ctx->in.pix,
- ctx->in.fmt->fourcc, ctx->out.width, ctx->out.height);
+ ctx->in.fmt->fourcc, DEFAULT_WIDTH, DEFAULT_HEIGHT);
v4l2_fill_pixfmt_mp(&ctx->out.pix,
- ctx->out.fmt->fourcc, ctx->out.width, ctx->out.height);
+ ctx->out.fmt->fourcc, DEFAULT_WIDTH, DEFAULT_HEIGHT);
if (mutex_lock_interruptible(&rga->mutex)) {
kfree(ctx);
@@ -453,10 +450,8 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
if (IS_ERR(frm))
return PTR_ERR(frm);
- v4l2_fill_pixfmt_mp(pix_fmt, frm->fmt->fourcc, frm->width, frm->height);
-
+ *pix_fmt = frm->pix;
pix_fmt->field = V4L2_FIELD_NONE;
- pix_fmt->colorspace = frm->colorspace;
return 0;
}
@@ -505,27 +500,24 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
frm = rga_get_frame(ctx, f->type);
if (IS_ERR(frm))
return PTR_ERR(frm);
- frm->width = pix_fmt->width;
- frm->height = pix_fmt->height;
frm->size = 0;
for (i = 0; i < pix_fmt->num_planes; i++)
frm->size += pix_fmt->plane_fmt[i].sizeimage;
frm->fmt = rga_fmt_find(pix_fmt->pixelformat);
frm->stride = pix_fmt->plane_fmt[0].bytesperline;
- frm->colorspace = pix_fmt->colorspace;
/* Reset crop settings */
frm->crop.left = 0;
frm->crop.top = 0;
- frm->crop.width = frm->width;
- frm->crop.height = frm->height;
+ frm->crop.width = pix_fmt->width;
+ frm->crop.height = pix_fmt->height;
frm->pix = *pix_fmt;
v4l2_dbg(debug, 1, &rga->v4l2_dev,
"[%s] fmt - %p4cc %dx%d (stride %d, sizeimage %d)\n",
V4L2_TYPE_IS_OUTPUT(f->type) ? "OUTPUT" : "CAPTURE",
- &frm->fmt->fourcc, frm->width, frm->height,
+ &frm->fmt->fourcc, pix_fmt->width, pix_fmt->height,
frm->stride, frm->size);
for (i = 0; i < pix_fmt->num_planes; i++) {
@@ -579,8 +571,8 @@ static int vidioc_g_selection(struct file *file, void *priv,
} else {
s->r.left = 0;
s->r.top = 0;
- s->r.width = f->width;
- s->r.height = f->height;
+ s->r.width = f->pix.width;
+ s->r.height = f->pix.height;
}
return 0;
@@ -629,8 +621,8 @@ static int vidioc_s_selection(struct file *file, void *priv,
return -EINVAL;
}
- if (s->r.left + s->r.width > f->width ||
- s->r.top + s->r.height > f->height ||
+ if (s->r.left + s->r.width > f->pix.width ||
+ s->r.top + s->r.height > f->pix.height ||
s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n");
return -EINVAL;
@@ -821,8 +813,8 @@ static int rga_probe(struct platform_device *pdev)
goto rel_m2m;
}
- def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
- def_frame.size = def_frame.stride * def_frame.height;
+ def_frame.stride = (DEFAULT_WIDTH * def_frame.fmt->depth) >> 3;
+ def_frame.size = def_frame.stride * DEFAULT_HEIGHT;
ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
if (ret) {
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 477cf5b62bbb2..c4a3905a48f0d 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -24,11 +24,6 @@ struct rga_fmt {
};
struct rga_frame {
- /* Original dimensions */
- u32 width;
- u32 height;
- u32 colorspace;
-
/* Crop */
struct v4l2_rect crop;
--
2.54.0
^ permalink raw reply related
* [PATCH v5 10/29] media: rockchip: rga: announce and sync colorimetry
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Announce the capability to adjust the quantization and ycbcr_enc on the
capture side and check if the SET_CSC flag is set when the colorimetry
is changed. Furthermore copy the colorimetry from the output to the
capture side to fix the currently failing v4l2-compliance tests, which
expect exactly this behavior.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga.c | 37 +++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index ca8d8a53dc251..8c34f73d69764 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -437,6 +437,15 @@ static int vidioc_enum_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f
fmt = &formats[f->index];
f->pixelformat = fmt->fourcc;
+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+ f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+ return 0;
+
+ /* allow changing the quantization and xfer func for YUV formats */
+ if (v4l2_is_format_yuv(v4l2_format_info(f->pixelformat)))
+ f->flags |= V4L2_FMT_FLAG_CSC_QUANTIZATION |
+ V4L2_FMT_FLAG_CSC_YCBCR_ENC;
+
return 0;
}
@@ -459,8 +468,25 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp;
+ struct rga_ctx *ctx = file_to_rga_ctx(file);
struct rga_fmt *fmt;
+ if (V4L2_TYPE_IS_CAPTURE(f->type)) {
+ const struct rga_frame *frm;
+
+ frm = rga_get_frame(ctx, f->type);
+ if (IS_ERR(frm))
+ return PTR_ERR(frm);
+
+ if (!(pix_fmt->flags & V4L2_PIX_FMT_FLAG_SET_CSC)) {
+ pix_fmt->quantization = frm->pix.quantization;
+ pix_fmt->ycbcr_enc = frm->pix.ycbcr_enc;
+ }
+ /* disallow values not announced in vidioc_enum_fmt */
+ pix_fmt->colorspace = frm->pix.colorspace;
+ pix_fmt->xfer_func = frm->pix.xfer_func;
+ }
+
fmt = rga_fmt_find(pix_fmt->pixelformat);
if (!fmt)
fmt = &formats[0];
@@ -506,6 +532,17 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
frm->fmt = rga_fmt_find(pix_fmt->pixelformat);
frm->stride = pix_fmt->plane_fmt[0].bytesperline;
+ /*
+ * Copy colorimetry from output to capture as required by the
+ * v4l2-compliance tests
+ */
+ if (V4L2_TYPE_IS_OUTPUT(f->type)) {
+ ctx->out.pix.colorspace = pix_fmt->colorspace;
+ ctx->out.pix.ycbcr_enc = pix_fmt->ycbcr_enc;
+ ctx->out.pix.quantization = pix_fmt->quantization;
+ ctx->out.pix.xfer_func = pix_fmt->xfer_func;
+ }
+
/* Reset crop settings */
frm->crop.left = 0;
frm->crop.top = 0;
--
2.54.0
^ permalink raw reply related
* [PATCH v5 12/29] media: rockchip: rga: avoid odd frame sizes for YUV formats
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Avoid odd frame sizes for YUV formats, as they may cause undefined
behavior. This is done in preparation for the RGA3, which hangs when the
output format is set to 129x129 pixel YUV420 SP (NV12).
This requirement is documented explicitly for the RGA3 in section 5.6.3
of the RK3588 TRM Part 2. For the RGA2 the RK3588 TRM Part 2
(section 6.1.2) and RK3568 TRM Part 2 (section 14.2) only mentions the
x/y offsets and stride aligning requirements. But the vendor driver for
the RGA2 also contains checks for the width and height to be aligned to
2 bytes.
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index f599c992829dd..77b8c7ab74274 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -337,6 +337,19 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
struct rga_ctx *ctx = file_to_rga_ctx(file);
const struct rga_hw *hw = ctx->rga->hw;
struct rga_fmt *fmt;
+ struct v4l2_frmsize_stepwise frmsize = {
+ .min_width = hw->min_width,
+ .max_width = hw->max_width,
+ .min_height = hw->min_height,
+ .max_height = hw->max_height,
+ .step_width = 1,
+ .step_height = 1,
+ };
+
+ if (v4l2_is_format_yuv(v4l2_format_info(pix_fmt->pixelformat))) {
+ frmsize.step_width = 2;
+ frmsize.step_height = 2;
+ }
if (V4L2_TYPE_IS_CAPTURE(f->type)) {
const struct rga_frame *frm;
@@ -358,11 +371,7 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
if (!fmt)
fmt = &hw->formats[0];
- pix_fmt->width = clamp(pix_fmt->width,
- hw->min_width, hw->max_width);
- pix_fmt->height = clamp(pix_fmt->height,
- hw->min_height, hw->max_height);
-
+ v4l2_apply_frmsize_constraints(&pix_fmt->width, &pix_fmt->height, &frmsize);
v4l2_fill_pixfmt_mp(pix_fmt, fmt->fourcc, pix_fmt->width, pix_fmt->height);
pix_fmt->field = V4L2_FIELD_NONE;
--
2.54.0
^ permalink raw reply related
* [PATCH v5 01/29] media: dt-bindings: media: rockchip-rga: add rockchip,rk3588-rga3
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Add a new compatible for the RGA3 (Raster Graphic Acceleration 3)
peripheral found on the RK3588 SoC. Also specify an iommu property,
as the RGA3 contains the generic rockchip iommu. While other versions
also have an iommu, it's usually specific to them.
The RK3588 contains one RGA2-Enhance core (also contained on the RK3399)
and two RGA3 cores. Both feature a similar functionality of scaling,
cropping and rotating of up to two input images into one output image.
Key differences of the RGA3 are:
- supports 10bit YUV output formats
- supports 8x8 tiles and FBCD as inputs and outputs
- supports BT2020 color space conversion
- max output resolution of (8192-64)x(8192-64)
- MMU can map up to 32G DDR RAM
- fully planar formats (3 planes) are not supported
- max scale up/down factor of 8 (RGA2 allows up to 16)
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
Changed in v3/v4:
- Dropped Acked-by: Krzysztof Kozlowski due to the added iommus property
and description adjustments.
---
Documentation/devicetree/bindings/media/rockchip-rga.yaml | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.yaml b/Documentation/devicetree/bindings/media/rockchip-rga.yaml
index ac17cda65191b..7bd92f7336664 100644
--- a/Documentation/devicetree/bindings/media/rockchip-rga.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip-rga.yaml
@@ -9,7 +9,11 @@ title: Rockchip 2D raster graphic acceleration controller (RGA)
description:
RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D
graphics operations, such as point/line drawing, image scaling, rotation,
- BitBLT, alpha blending and image blur/sharpness.
+ BitBLT, alpha blending and image blur/sharpness. There exist many versions
+ of this unit that differ in the supported inputs/output formats,
+ the attached IOMMU and the supported operations on the input. As some SoCs
+ include multiple RGA units with different versions, a more specific
+ compatible name to differentiate the concrete unit is used for them.
maintainers:
- Jacob Chen <jacob-chen@iotwrt.com>
@@ -20,6 +24,7 @@ properties:
oneOf:
- const: rockchip,rk3288-rga
- const: rockchip,rk3399-rga
+ - const: rockchip,rk3588-rga3
- items:
- enum:
- rockchip,rk3228-rga
@@ -45,6 +50,9 @@ properties:
power-domains:
maxItems: 1
+ iommus:
+ maxItems: 1
+
resets:
maxItems: 3
--
2.54.0
^ permalink raw reply related
* [PATCH v5 13/29] media: rockchip: rga: calculate x_div/y_div using v4l2_format_info
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Calculate the x_div and y_div variables with the information from
v4l2_format_info instead of storing these in the rga_fmt struct.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-hw.c | 45 +++++++---------------------
drivers/media/platform/rockchip/rga/rga.h | 2 --
2 files changed, 11 insertions(+), 36 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index 40498796507e0..17f7a67c0b4bb 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -42,6 +42,7 @@ rga_get_addr_offset(struct rga_frame *frm, struct rga_addr_offset *offset,
{
struct rga_corners_addr_offset offsets;
struct rga_addr_offset *lt, *lb, *rt, *rb;
+ const struct v4l2_format_info *format_info;
unsigned int x_div = 0,
y_div = 0, uv_stride = 0, pixel_width = 0;
@@ -50,8 +51,16 @@ rga_get_addr_offset(struct rga_frame *frm, struct rga_addr_offset *offset,
rt = &offsets.right_top;
rb = &offsets.right_bottom;
- x_div = frm->fmt->x_div;
- y_div = frm->fmt->y_div;
+ format_info = v4l2_format_info(frm->pix.pixelformat);
+ /* x_div is only used for the u/v planes.
+ * When the format doesn't have these, use 1 to avoid a division by zero.
+ */
+ if (format_info->bpp[1])
+ x_div = format_info->hdiv * format_info->bpp_div[1] /
+ format_info->bpp[1];
+ else
+ x_div = 1;
+ y_div = format_info->vdiv;
uv_stride = frm->stride / x_div;
pixel_width = frm->stride / frm->pix.width;
@@ -476,128 +485,96 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_ALPHA_SWAP,
.hw_format = RGA_COLOR_FMT_ABGR8888,
.depth = 32,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_ABGR32,
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_ABGR8888,
.depth = 32,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_XBGR32,
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_XBGR8888,
.depth = 32,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_RGB24,
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_RGB888,
.depth = 24,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_BGR24,
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_RGB888,
.depth = 24,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_ARGB444,
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_ABGR4444,
.depth = 16,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_ARGB555,
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_ABGR1555,
.depth = 16,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_RGB565,
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_BGR565,
.depth = 16,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_NV21,
.color_swap = RGA_COLOR_UV_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420SP,
.depth = 12,
- .y_div = 2,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_NV61,
.color_swap = RGA_COLOR_UV_SWAP,
.hw_format = RGA_COLOR_FMT_YUV422SP,
.depth = 16,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_NV12,
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420SP,
.depth = 12,
- .y_div = 2,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_NV12M,
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420SP,
.depth = 12,
- .y_div = 2,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_NV16,
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV422SP,
.depth = 16,
- .y_div = 1,
- .x_div = 1,
},
{
.fourcc = V4L2_PIX_FMT_YUV420,
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420P,
.depth = 12,
- .y_div = 2,
- .x_div = 2,
},
{
.fourcc = V4L2_PIX_FMT_YUV422P,
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV422P,
.depth = 16,
- .y_div = 1,
- .x_div = 2,
},
{
.fourcc = V4L2_PIX_FMT_YVU420,
.color_swap = RGA_COLOR_UV_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420P,
.depth = 12,
- .y_div = 2,
- .x_div = 2,
},
};
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 640e510285341..27b3c9b4f220c 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -20,8 +20,6 @@
struct rga_fmt {
u32 fourcc;
int depth;
- u8 y_div;
- u8 x_div;
u8 color_swap;
u8 hw_format;
};
--
2.54.0
^ permalink raw reply related
* [PATCH v5 07/29] media: rockchip: rga: use clk_bulk api
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Use the clk_bulk API to avoid code duplication for each of the three
clocks.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga.c | 65 ++++---------------------------
drivers/media/platform/rockchip/rga/rga.h | 6 +--
2 files changed, 11 insertions(+), 60 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index fea63b94c5f3d..4e710a050cb7c 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -698,48 +698,10 @@ static const struct video_device rga_videodev = {
.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
};
-static int rga_enable_clocks(struct rockchip_rga *rga)
-{
- int ret;
-
- ret = clk_prepare_enable(rga->sclk);
- if (ret) {
- dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
- return ret;
- }
-
- ret = clk_prepare_enable(rga->aclk);
- if (ret) {
- dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
- goto err_disable_sclk;
- }
-
- ret = clk_prepare_enable(rga->hclk);
- if (ret) {
- dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
- goto err_disable_aclk;
- }
-
- return 0;
-
-err_disable_aclk:
- clk_disable_unprepare(rga->aclk);
-err_disable_sclk:
- clk_disable_unprepare(rga->sclk);
-
- return ret;
-}
-
-static void rga_disable_clocks(struct rockchip_rga *rga)
-{
- clk_disable_unprepare(rga->sclk);
- clk_disable_unprepare(rga->hclk);
- clk_disable_unprepare(rga->aclk);
-}
-
static int rga_parse_dt(struct rockchip_rga *rga)
{
struct reset_control *core_rst, *axi_rst, *ahb_rst;
+ int ret;
core_rst = devm_reset_control_get(rga->dev, "core");
if (IS_ERR(core_rst)) {
@@ -771,23 +733,12 @@ static int rga_parse_dt(struct rockchip_rga *rga)
udelay(1);
reset_control_deassert(ahb_rst);
- rga->sclk = devm_clk_get(rga->dev, "sclk");
- if (IS_ERR(rga->sclk)) {
- dev_err(rga->dev, "failed to get sclk clock\n");
- return PTR_ERR(rga->sclk);
- }
-
- rga->aclk = devm_clk_get(rga->dev, "aclk");
- if (IS_ERR(rga->aclk)) {
- dev_err(rga->dev, "failed to get aclk clock\n");
- return PTR_ERR(rga->aclk);
- }
-
- rga->hclk = devm_clk_get(rga->dev, "hclk");
- if (IS_ERR(rga->hclk)) {
- dev_err(rga->dev, "failed to get hclk clock\n");
- return PTR_ERR(rga->hclk);
+ ret = devm_clk_bulk_get_all(rga->dev, &rga->clks);
+ if (ret < 0) {
+ dev_err(rga->dev, "failed to get clocks\n");
+ return ret;
}
+ rga->num_clks = ret;
return 0;
}
@@ -935,7 +886,7 @@ static int __maybe_unused rga_runtime_suspend(struct device *dev)
{
struct rockchip_rga *rga = dev_get_drvdata(dev);
- rga_disable_clocks(rga);
+ clk_bulk_disable_unprepare(rga->num_clks, rga->clks);
return 0;
}
@@ -944,7 +895,7 @@ static int __maybe_unused rga_runtime_resume(struct device *dev)
{
struct rockchip_rga *rga = dev_get_drvdata(dev);
- return rga_enable_clocks(rga);
+ return clk_bulk_prepare_enable(rga->num_clks, rga->clks);
}
static const struct dev_pm_ops rga_pm = {
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 72a28b120fabf..2db10acecb405 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -6,6 +6,7 @@
#ifndef __RGA_H__
#define __RGA_H__
+#include <linux/clk.h>
#include <linux/platform_device.h>
#include <media/videobuf2-v4l2.h>
#include <media/v4l2-ctrls.h>
@@ -81,9 +82,8 @@ struct rockchip_rga {
struct device *dev;
struct regmap *grf;
void __iomem *regs;
- struct clk *sclk;
- struct clk *aclk;
- struct clk *hclk;
+ struct clk_bulk_data *clks;
+ int num_clks;
struct rockchip_rga_version version;
/* vfd lock */
--
2.54.0
^ permalink raw reply related
* [PATCH v5 06/29] media: rockchip: rga: fix too small buffer size
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Fix the command buffer size being only a quarter of the actual size.
The RGA_CMDBUF_SIZE macro was potentially intended to specify the length
of the cmdbuf u32 array pointer. But as it's used to specify the size of
the allocation, which is counted in bytes. Therefore adjust the macro
size to bytes as it better matches the variable name and adjust it's
users accordingly.
As the command buffer is relatively small, it probably didn't caused
an issue due to being smaller than a single page.
Fixes: f7e7b48e6d79 ("[media] rockchip/rga: v4l2 m2m support")
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-hw.c | 2 +-
drivers/media/platform/rockchip/rga/rga-hw.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index 43ed742a16492..d1618bb247501 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -414,7 +414,7 @@ static void rga_cmd_set(struct rga_ctx *ctx,
{
struct rockchip_rga *rga = ctx->rga;
- memset(rga->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
+ memset(rga->cmdbuf_virt, 0, RGA_CMDBUF_SIZE);
rga_cmd_set_src_addr(ctx, src->dma_desc_pa);
/*
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.h b/drivers/media/platform/rockchip/rga/rga-hw.h
index cc6bd7f5b0300..2b8537a5fd0d7 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.h
+++ b/drivers/media/platform/rockchip/rga/rga-hw.h
@@ -6,7 +6,7 @@
#ifndef __RGA_HW_H__
#define __RGA_HW_H__
-#define RGA_CMDBUF_SIZE 0x20
+#define RGA_CMDBUF_SIZE 0x80
/* Hardware limits */
#define MAX_WIDTH 8192
--
2.54.0
^ permalink raw reply related
* [PATCH v5 17/29] media: rockchip: rga: prepare cmdbuf on streamon
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Prepare the command buffer on streamon to reuse it's contents instead of
completely writing it for every frame. Due to the stream settings being
fixed after a streamon we only need to replace the source and destination
addresses for each frame. This reduces the amount of CPU and memory
operations done in each frame.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
Changes in v5:
- Don't set the flipping and rotation values at streamon and preventing
the userspace from chainging them at runtime
---
drivers/media/platform/rockchip/rga/rga-hw.c | 13 +++++++++----
drivers/media/platform/rockchip/rga/rga.c | 13 ++++++++++++-
drivers/media/platform/rockchip/rga/rga.h | 1 +
3 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index 6c1956b04f6ba..11079477a3008 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -427,8 +427,6 @@ static void rga_cmd_set(struct rga_ctx *ctx,
{
struct rockchip_rga *rga = ctx->rga;
- memset(ctx->cmdbuf_virt, 0, RGA_CMDBUF_SIZE);
-
rga_cmd_set_src_addr(ctx, src->dma_desc_pa);
/*
* Due to hardware bug,
@@ -437,11 +435,9 @@ static void rga_cmd_set(struct rga_ctx *ctx,
rga_cmd_set_src1_addr(ctx, dst->dma_desc_pa);
rga_cmd_set_dst_addr(ctx, dst->dma_desc_pa);
- rga_cmd_set_mode(ctx);
rga_cmd_set_src_info(ctx, &src->offset);
rga_cmd_set_dst_info(ctx, &dst->offset);
- rga_cmd_set_format_scale_info(ctx);
rga_cmd_set_flip_rotate_info(ctx);
rga_write(rga, RGA_CMD_BASE, ctx->cmdbuf_phy);
@@ -451,6 +447,14 @@ static void rga_cmd_set(struct rga_ctx *ctx,
PAGE_SIZE, DMA_BIDIRECTIONAL);
}
+static void rga_hw_setup_cmdbuf(struct rga_ctx *ctx)
+{
+ memset(ctx->cmdbuf_virt, 0, RGA_CMDBUF_SIZE);
+
+ rga_cmd_set_mode(ctx);
+ rga_cmd_set_format_scale_info(ctx);
+}
+
static void rga_hw_start(struct rockchip_rga *rga,
struct rga_vb_buffer *src, struct rga_vb_buffer *dst)
{
@@ -593,6 +597,7 @@ const struct rga_hw rga2_hw = {
.max_height = MAX_HEIGHT,
.stride_alignment = 4,
+ .setup_cmdbuf = rga_hw_setup_cmdbuf,
.start = rga_hw_start,
.handle_irq = rga_handle_irq,
.get_version = rga_get_version,
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index 16a663aeef8c9..d111b348255e2 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -568,6 +568,17 @@ static int vidioc_s_selection(struct file *file, void *priv,
return ret;
}
+static int vidioc_streamon(struct file *file, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct rga_ctx *ctx = file_to_rga_ctx(file);
+ const struct rga_hw *hw = ctx->rga->hw;
+
+ hw->setup_cmdbuf(ctx);
+
+ return v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, type);
+}
+
static const struct v4l2_ioctl_ops rga_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
@@ -592,7 +603,7 @@ static const struct v4l2_ioctl_ops rga_ioctl_ops = {
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
- .vidioc_streamon = v4l2_m2m_ioctl_streamon,
+ .vidioc_streamon = vidioc_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
.vidioc_g_selection = vidioc_g_selection,
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 38518146910a6..c741213710b32 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -152,6 +152,7 @@ struct rga_hw {
u32 max_width, max_height;
u8 stride_alignment;
+ void (*setup_cmdbuf)(struct rga_ctx *ctx);
void (*start)(struct rockchip_rga *rga,
struct rga_vb_buffer *src, struct rga_vb_buffer *dst);
bool (*handle_irq)(struct rockchip_rga *rga);
--
2.54.0
^ permalink raw reply related
* [PATCH v5 18/29] media: rockchip: rga: check scaling factor
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Check the scaling factor to avoid potential problems. This is relevant
for the upcoming RGA3 support, as it can hang when the scaling factor
is exceeded.
There are two relevant scenarios that have to be considered to protect
against invalid scaling values:
When the output or capture is already streaming, setting the format on
the other side should consider the max scaling factor and clamp it
accordingly. This is only done in the streaming case, as it otherwise
may unintentionally clamp the value when the application sets the first
format (due to a default format on the other side).
When the format is set on both sides first, then the format won't be
corrected by above means. Therefore the second streamon call has to
check the scaling factor and fail otherwise.
As try functions should only be state aware if specified, the scaling
limitation is only done in s_fmt.
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-hw.c | 1 +
drivers/media/platform/rockchip/rga/rga-hw.h | 1 +
drivers/media/platform/rockchip/rga/rga.c | 47 ++++++++++++++++++++++++++++
drivers/media/platform/rockchip/rga/rga.h | 1 +
4 files changed, 50 insertions(+)
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index 11079477a3008..11a1a914668f6 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -595,6 +595,7 @@ const struct rga_hw rga2_hw = {
.max_width = MAX_WIDTH,
.min_height = MIN_HEIGHT,
.max_height = MAX_HEIGHT,
+ .max_scaling_factor = MAX_SCALING_FACTOR,
.stride_alignment = 4,
.setup_cmdbuf = rga_hw_setup_cmdbuf,
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.h b/drivers/media/platform/rockchip/rga/rga-hw.h
index c2e34be751939..805ec23e5e3f4 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.h
+++ b/drivers/media/platform/rockchip/rga/rga-hw.h
@@ -14,6 +14,7 @@
#define MIN_WIDTH 34
#define MIN_HEIGHT 34
+#define MAX_SCALING_FACTOR 16
#define RGA_TIMEOUT 500
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index d111b348255e2..75d05c86b1c00 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -405,10 +405,36 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp;
struct rga_ctx *ctx = file_to_rga_ctx(file);
struct rockchip_rga *rga = ctx->rga;
+ const struct rga_hw *hw = rga->hw;
struct vb2_queue *vq;
struct rga_frame *frm;
int ret = 0;
int i;
+ struct rga_frame *limit_frm = NULL;
+
+ /* Limit before try_fmt to avoid recalculating the stride */
+ if (V4L2_TYPE_IS_OUTPUT(f->type) &&
+ v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx)->streaming)
+ limit_frm = &ctx->out;
+ if (V4L2_TYPE_IS_CAPTURE(f->type) &&
+ v4l2_m2m_get_src_vq(ctx->fh.m2m_ctx)->streaming)
+ limit_frm = &ctx->in;
+ if (limit_frm) {
+ const struct v4l2_frmsize_stepwise frmsize = {
+ .min_width = DIV_ROUND_UP(limit_frm->pix.width,
+ hw->max_scaling_factor),
+ .max_width =
+ limit_frm->pix.width * hw->max_scaling_factor,
+ .min_height = DIV_ROUND_UP(limit_frm->pix.height,
+ hw->max_scaling_factor),
+ .max_height =
+ limit_frm->pix.height * hw->max_scaling_factor,
+ .step_width = 1,
+ .step_height = 1,
+ };
+ v4l2_apply_frmsize_constraints(&pix_fmt->width,
+ &pix_fmt->height, &frmsize);
+ }
/* Adjust all values accordingly to the hardware capabilities
* and chosen format.
@@ -568,12 +594,33 @@ static int vidioc_s_selection(struct file *file, void *priv,
return ret;
}
+static bool check_scaling(const struct rga_hw *hw, u32 src_size, u32 dst_size)
+{
+ if (src_size < dst_size)
+ return src_size * hw->max_scaling_factor >= dst_size;
+ else
+ return dst_size * hw->max_scaling_factor >= src_size;
+}
+
static int vidioc_streamon(struct file *file, void *priv,
enum v4l2_buf_type type)
{
struct rga_ctx *ctx = file_to_rga_ctx(file);
const struct rga_hw *hw = ctx->rga->hw;
+ if ((V4L2_TYPE_IS_OUTPUT(type) &&
+ v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx)->streaming) ||
+ (V4L2_TYPE_IS_CAPTURE(type) &&
+ v4l2_m2m_get_src_vq(ctx->fh.m2m_ctx)->streaming)) {
+ /*
+ * As the other side is already streaming,
+ * check that the max scaling factor isn't exceeded.
+ */
+ if (!check_scaling(hw, ctx->in.pix.width, ctx->out.pix.width) ||
+ !check_scaling(hw, ctx->in.pix.height, ctx->out.pix.height))
+ return -EINVAL;
+ }
+
hw->setup_cmdbuf(ctx);
return v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, type);
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index c741213710b32..454af283b1694 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -150,6 +150,7 @@ struct rga_hw {
size_t cmdbuf_size;
u32 min_width, min_height;
u32 max_width, max_height;
+ u8 max_scaling_factor;
u8 stride_alignment;
void (*setup_cmdbuf)(struct rga_ctx *ctx);
--
2.54.0
^ permalink raw reply related
* [PATCH v5 21/29] media: rockchip: rga: support external iommus
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
In preparation for the RGA3 add support for external iommus. This is a
transition step to just disable the RGA2 specific mmu table setup code.
Currently a simple rga_hw struct field is used to set the internal iommu.
But to handle the case of more sophisticated detection mechanisms
(e.g. check for an iommu property in the device tree), it is abstracted
by an inline function.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-buf.c | 31 ++++++++++++++++++---------
drivers/media/platform/rockchip/rga/rga-hw.c | 1 +
drivers/media/platform/rockchip/rga/rga.c | 11 ++++++++--
drivers/media/platform/rockchip/rga/rga.h | 6 ++++++
4 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-buf.c b/drivers/media/platform/rockchip/rga/rga-buf.c
index bc349d0a46365..4e82ca1a5e8d9 100644
--- a/drivers/media/platform/rockchip/rga/rga-buf.c
+++ b/drivers/media/platform/rockchip/rga/rga-buf.c
@@ -12,6 +12,7 @@
#include <media/v4l2-ioctl.h>
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-dma-sg.h>
+#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-v4l2.h>
#include "rga.h"
@@ -82,6 +83,9 @@ static int rga_buf_init(struct vb2_buffer *vb)
if (IS_ERR(f))
return PTR_ERR(f);
+ if (!rga_has_internal_iommu(rga))
+ return 0;
+
n_desc = DIV_ROUND_UP(f->size, PAGE_SIZE);
rbuf->n_desc = n_desc;
@@ -136,17 +140,21 @@ static int rga_buf_prepare(struct vb2_buffer *vb)
for (i = 0; i < vb->num_planes; i++) {
vb2_set_plane_payload(vb, i, f->pix.plane_fmt[i].sizeimage);
- /* Create local MMU table for RGA */
- n_desc = fill_descriptors(&rbuf->dma_desc[curr_desc],
- rbuf->n_desc - curr_desc,
- vb2_dma_sg_plane_desc(vb, i));
- if (n_desc < 0) {
- v4l2_err(&ctx->rga->v4l2_dev,
- "Failed to map video buffer to RGA\n");
- return n_desc;
+ if (rga_has_internal_iommu(ctx->rga)) {
+ /* Create local MMU table for RGA */
+ n_desc = fill_descriptors(&rbuf->dma_desc[curr_desc],
+ rbuf->n_desc - curr_desc,
+ vb2_dma_sg_plane_desc(vb, i));
+ if (n_desc < 0) {
+ v4l2_err(&ctx->rga->v4l2_dev,
+ "Failed to map video buffer to RGA\n");
+ return n_desc;
+ }
+ dma_addrs[i] = curr_desc << PAGE_SHIFT;
+ curr_desc += n_desc;
+ } else {
+ dma_addrs[i] = vb2_dma_contig_plane_dma_addr(vb, i);
}
- dma_addrs[i] = curr_desc << PAGE_SHIFT;
- curr_desc += n_desc;
}
/* Fill the remaining planes */
@@ -176,6 +184,9 @@ static void rga_buf_cleanup(struct vb2_buffer *vb)
struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct rockchip_rga *rga = ctx->rga;
+ if (!rga_has_internal_iommu(rga))
+ return;
+
dma_free_coherent(rga->dev, rbuf->n_desc * sizeof(*rbuf->dma_desc),
rbuf->dma_desc, rbuf->dma_desc_pa);
}
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index 8f60482f538c5..ea4d2b0832d82 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -588,6 +588,7 @@ static struct rga_fmt formats[] = {
const struct rga_hw rga2_hw = {
.card_type = "rga2",
+ .has_internal_iommu = true,
.formats = formats,
.num_formats = ARRAY_SIZE(formats),
.cmdbuf_size = RGA_CMDBUF_SIZE,
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index 421a70558c3c7..5bdc8dc51ab68 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -23,6 +23,7 @@
#include <media/v4l2-ioctl.h>
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-dma-sg.h>
+#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-v4l2.h>
#include "rga.h"
@@ -95,7 +96,10 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
src_vq->drv_priv = ctx;
src_vq->ops = &rga_qops;
- src_vq->mem_ops = &vb2_dma_sg_memops;
+ if (rga_has_internal_iommu(ctx->rga))
+ src_vq->mem_ops = &vb2_dma_sg_memops;
+ else
+ src_vq->mem_ops = &vb2_dma_contig_memops;
src_vq->gfp_flags = __GFP_DMA32;
src_vq->buf_struct_size = sizeof(struct rga_vb_buffer);
src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
@@ -110,7 +114,10 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
dst_vq->drv_priv = ctx;
dst_vq->ops = &rga_qops;
- dst_vq->mem_ops = &vb2_dma_sg_memops;
+ if (rga_has_internal_iommu(ctx->rga))
+ dst_vq->mem_ops = &vb2_dma_sg_memops;
+ else
+ dst_vq->mem_ops = &vb2_dma_contig_memops;
dst_vq->gfp_flags = __GFP_DMA32;
dst_vq->buf_struct_size = sizeof(struct rga_vb_buffer);
dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 025b1df594e9a..95fa7fd1c509a 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -146,6 +146,7 @@ static inline void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask)
struct rga_hw {
const char *card_type;
+ bool has_internal_iommu;
struct rga_fmt *formats;
u32 num_formats;
size_t cmdbuf_size;
@@ -161,6 +162,11 @@ struct rga_hw {
void (*get_version)(struct rockchip_rga *rga);
};
+static inline bool rga_has_internal_iommu(const struct rockchip_rga *rga)
+{
+ return rga->hw->has_internal_iommu;
+}
+
extern const struct rga_hw rga2_hw;
#endif
--
2.54.0
^ permalink raw reply related
* [PATCH v5 03/29] media: v4l2-common: add missing 1 and 2 byte RGB formats to v4l2_format_info
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Add all missing one and two byte RGB formats to v4l2_format_info. This
allows drivers to more consistently use v4l2_format_info, as it now
covers all currently defined RGB formats.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/v4l2-core/v4l2-common.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
index 49c1ec08e2eb3..58a4b372cf5be 100644
--- a/drivers/media/v4l2-core/v4l2-common.c
+++ b/drivers/media/v4l2-core/v4l2-common.c
@@ -246,8 +246,29 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
{
static const struct v4l2_format_info formats[] = {
/* RGB formats (1 or 2 bytes per pixel) */
+ { .format = V4L2_PIX_FMT_RGB332, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 1, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGB444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ARGB444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XRGB444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGBA444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGBX444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ABGR444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XBGR444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_BGRA444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_BGRX444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_RGB555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ARGB555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XRGB555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGBA555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGBX555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ABGR555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XBGR555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_BGRA555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_BGRX555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_RGB565, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGB555X, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ARGB555X, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XRGB555X, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_RGB565X, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
/* RGB formats (3 or 4 bytes per pixel) */
--
2.54.0
^ permalink raw reply related
* [PATCH v5 08/29] media: rockchip: rga: use stride for offset calculation
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Use the stride instead of the width for the offset calculation. This
ensures that the bytesperline value doesn't need to match the width
value of the image.
Furthermore this patch removes the dependency on the uv_factor property
and instead reuses the v4l2_format_info to determine the correct
division factor.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-buf.c | 14 +++++++++-----
drivers/media/platform/rockchip/rga/rga.c | 16 ----------------
drivers/media/platform/rockchip/rga/rga.h | 1 -
3 files changed, 9 insertions(+), 22 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-buf.c b/drivers/media/platform/rockchip/rga/rga-buf.c
index bb575873f2b24..65fc0d5b4aa10 100644
--- a/drivers/media/platform/rockchip/rga/rga-buf.c
+++ b/drivers/media/platform/rockchip/rga/rga-buf.c
@@ -14,7 +14,6 @@
#include <media/videobuf2-dma-sg.h>
#include <media/videobuf2-v4l2.h>
-#include "rga-hw.h"
#include "rga.h"
static ssize_t fill_descriptors(struct rga_dma_desc *desc, size_t max_desc,
@@ -95,14 +94,19 @@ static int rga_buf_init(struct vb2_buffer *vb)
return 0;
}
-static int get_plane_offset(struct rga_frame *f, int plane)
+static int get_plane_offset(struct rga_frame *f,
+ const struct v4l2_format_info *info,
+ int plane)
{
+ u32 stride = f->pix.plane_fmt[0].bytesperline;
+
if (plane == 0)
return 0;
if (plane == 1)
- return f->width * f->height;
+ return stride * f->height;
if (plane == 2)
- return f->width * f->height + (f->width * f->height / f->fmt->uv_factor);
+ return stride * f->height +
+ (stride * f->height / info->hdiv / info->vdiv);
return -EINVAL;
}
@@ -148,7 +152,7 @@ static int rga_buf_prepare(struct vb2_buffer *vb)
/* Fill the remaining planes */
info = v4l2_format_info(f->fmt->fourcc);
for (i = info->mem_planes; i < info->comp_planes; i++)
- offsets[i] = get_plane_offset(f, i);
+ offsets[i] = get_plane_offset(f, info, i);
rbuf->offset.y_off = offsets[0];
rbuf->offset.u_off = offsets[1];
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index 4e710a050cb7c..c07207edffdb6 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -190,7 +190,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_ALPHA_SWAP,
.hw_format = RGA_COLOR_FMT_ABGR8888,
.depth = 32,
- .uv_factor = 1,
.y_div = 1,
.x_div = 1,
},
@@ -199,7 +198,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_ABGR8888,
.depth = 32,
- .uv_factor = 1,
.y_div = 1,
.x_div = 1,
},
@@ -208,7 +206,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_XBGR8888,
.depth = 32,
- .uv_factor = 1,
.y_div = 1,
.x_div = 1,
},
@@ -217,7 +214,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_RGB888,
.depth = 24,
- .uv_factor = 1,
.y_div = 1,
.x_div = 1,
},
@@ -226,7 +222,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_RGB888,
.depth = 24,
- .uv_factor = 1,
.y_div = 1,
.x_div = 1,
},
@@ -235,7 +230,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_ABGR4444,
.depth = 16,
- .uv_factor = 1,
.y_div = 1,
.x_div = 1,
},
@@ -244,7 +238,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_ABGR1555,
.depth = 16,
- .uv_factor = 1,
.y_div = 1,
.x_div = 1,
},
@@ -253,7 +246,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_RB_SWAP,
.hw_format = RGA_COLOR_FMT_BGR565,
.depth = 16,
- .uv_factor = 1,
.y_div = 1,
.x_div = 1,
},
@@ -262,7 +254,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_UV_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420SP,
.depth = 12,
- .uv_factor = 4,
.y_div = 2,
.x_div = 1,
},
@@ -271,7 +262,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_UV_SWAP,
.hw_format = RGA_COLOR_FMT_YUV422SP,
.depth = 16,
- .uv_factor = 2,
.y_div = 1,
.x_div = 1,
},
@@ -280,7 +270,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420SP,
.depth = 12,
- .uv_factor = 4,
.y_div = 2,
.x_div = 1,
},
@@ -289,7 +278,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420SP,
.depth = 12,
- .uv_factor = 4,
.y_div = 2,
.x_div = 1,
},
@@ -298,7 +286,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV422SP,
.depth = 16,
- .uv_factor = 2,
.y_div = 1,
.x_div = 1,
},
@@ -307,7 +294,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420P,
.depth = 12,
- .uv_factor = 4,
.y_div = 2,
.x_div = 2,
},
@@ -316,7 +302,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_NONE_SWAP,
.hw_format = RGA_COLOR_FMT_YUV422P,
.depth = 16,
- .uv_factor = 2,
.y_div = 1,
.x_div = 2,
},
@@ -325,7 +310,6 @@ static struct rga_fmt formats[] = {
.color_swap = RGA_COLOR_UV_SWAP,
.hw_format = RGA_COLOR_FMT_YUV420P,
.depth = 12,
- .uv_factor = 4,
.y_div = 2,
.x_div = 2,
},
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 2db10acecb405..477cf5b62bbb2 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -17,7 +17,6 @@
struct rga_fmt {
u32 fourcc;
int depth;
- u8 uv_factor;
u8 y_div;
u8 x_div;
u8 color_swap;
--
2.54.0
^ permalink raw reply related
* [PATCH v5 15/29] media: rockchip: rga: align stride to 4 bytes
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
Add an alignment setting to rga_hw to set the desired stride alignment.
As the RGA2 register for the stride counts in word units, the code
already divides the bytesperline value by 4 when writing it into the
register. Therefore fix the alignment to a multiple of 4 to avoid
potential off by one errors due from the division.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-hw.c | 1 +
drivers/media/platform/rockchip/rga/rga.c | 11 ++++++-----
drivers/media/platform/rockchip/rga/rga.h | 1 +
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index 9881c14f908d5..dac3cb6aa17d3 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -580,6 +580,7 @@ const struct rga_hw rga2_hw = {
.max_width = MAX_WIDTH,
.min_height = MIN_HEIGHT,
.max_height = MAX_HEIGHT,
+ .stride_alignment = 4,
.start = rga_hw_start,
.handle_irq = rga_handle_irq,
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index bf6bbcbfc869b..16a663aeef8c9 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -234,10 +234,10 @@ static int rga_open(struct file *file)
ctx->in = def_frame;
ctx->out = def_frame;
- v4l2_fill_pixfmt_mp(&ctx->in.pix,
- ctx->in.fmt->fourcc, def_width, def_height);
- v4l2_fill_pixfmt_mp(&ctx->out.pix,
- ctx->out.fmt->fourcc, def_width, def_height);
+ v4l2_fill_pixfmt_mp_aligned(&ctx->in.pix, ctx->in.fmt->fourcc,
+ def_width, def_height, rga->hw->stride_alignment);
+ v4l2_fill_pixfmt_mp_aligned(&ctx->out.pix, ctx->out.fmt->fourcc,
+ def_width, def_height, rga->hw->stride_alignment);
if (mutex_lock_interruptible(&rga->mutex)) {
ret = -ERESTARTSYS;
@@ -393,7 +393,8 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
fmt = &hw->formats[0];
v4l2_apply_frmsize_constraints(&pix_fmt->width, &pix_fmt->height, &frmsize);
- v4l2_fill_pixfmt_mp(pix_fmt, fmt->fourcc, pix_fmt->width, pix_fmt->height);
+ v4l2_fill_pixfmt_mp_aligned(pix_fmt, pix_fmt->pixelformat,
+ pix_fmt->width, pix_fmt->height, hw->stride_alignment);
pix_fmt->field = V4L2_FIELD_NONE;
return 0;
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 04aeb7b429523..38518146910a6 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -150,6 +150,7 @@ struct rga_hw {
size_t cmdbuf_size;
u32 min_width, min_height;
u32 max_width, max_height;
+ u8 stride_alignment;
void (*start)(struct rockchip_rga *rga,
struct rga_vb_buffer *src, struct rga_vb_buffer *dst);
--
2.54.0
^ permalink raw reply related
* [PATCH v5 19/29] media: rockchip: rga: use card type to specify rga type
From: Sven Püschel @ 2026-04-28 9:00 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans Verkuil
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260428-spu-rga3-v5-0-eb7f5d019d86@pengutronix.de>
In preparation of the RGA3 support add a filed to the rga_hw struct
to specify the desired card type value. This allows the user to
differentiate the RGA2 and RGA3 video device nodes.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-hw.c | 1 +
drivers/media/platform/rockchip/rga/rga.c | 4 +++-
drivers/media/platform/rockchip/rga/rga.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index 11a1a914668f6..931b4c4074a29 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -588,6 +588,7 @@ static struct rga_fmt formats[] = {
};
const struct rga_hw rga2_hw = {
+ .card_type = "rga2",
.formats = formats,
.num_formats = ARRAY_SIZE(formats),
.cmdbuf_size = RGA_CMDBUF_SIZE,
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index 75d05c86b1c00..421a70558c3c7 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -306,8 +306,10 @@ static const struct v4l2_file_operations rga_fops = {
static int
vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
{
+ struct rockchip_rga *rga = video_drvdata(file);
+
strscpy(cap->driver, RGA_NAME, sizeof(cap->driver));
- strscpy(cap->card, "rockchip-rga", sizeof(cap->card));
+ strscpy(cap->card, rga->hw->card_type, sizeof(cap->card));
strscpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
return 0;
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 454af283b1694..dc6f90b843c32 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -145,6 +145,7 @@ static inline void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask)
};
struct rga_hw {
+ const char *card_type;
struct rga_fmt *formats;
u32 num_formats;
size_t cmdbuf_size;
--
2.54.0
^ permalink raw reply related
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