* [PATCH v3 03/13] iio: adc: at91-sama5d2_adc: rework temp calibration layout handling
From: Varshini Rajendran @ 2026-06-30 9:35 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Extend support to handle different temperature calibration layouts.
Add a temperature calibration data layout structure to describe indexes
of the factors P1, P4, P6, tag, minimum length of the packet and the
scaling factors for P1 (mul, div) which are SoC-specific instead of the
older non scalable id structure. This helps handle the differences in the
same function flow and prepare the calibration data to be applied. Add
additional condition to validate the calibration data read from the
NVMEM cell using the TAG of the packet.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
drivers/iio/adc/at91-sama5d2_adc.c | 67 ++++++++++++++++++++++--------
1 file changed, 49 insertions(+), 18 deletions(-)
diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
index 5015c234289e..2a25165bc874 100644
--- a/drivers/iio/adc/at91-sama5d2_adc.c
+++ b/drivers/iio/adc/at91-sama5d2_adc.c
@@ -445,6 +445,29 @@ static const struct at91_adc_reg_layout sama7g5_layout = {
#define at91_adc_writel(st, reg, val) \
writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
+/* Temperature calibration tag "ACST" in ASCII */
+#define AT91_TEMP_CALIB_TAG_ACST 0x41435354
+
+/**
+ * struct at91_adc_temp_calib_layout - temperature calibration packet layout
+ * @tag_idx: index of Packet tag in the NVMEM cell buffer
+ * @p1_idx: index of FT1_TEMP, equivalent to P1 in the NVMEM cell buffer
+ * @p4_idx: index of FT1_VPAT, equivalent to P4 in the NVMEM cell buffer
+ * @p6_idx: index of FT2_VBG, equivalent to P6 in the NVMEM cell buffer
+ * @min_len: minimum number of u32 words expected in the NVMEM cell buffer
+ * @p1_mul: multiplier applied to P1 to convert to millicelcius
+ * @p1_div: divider applied to P1 to convert to millicelcius
+ */
+struct at91_adc_temp_calib_layout {
+ unsigned int tag_idx;
+ unsigned int p1_idx;
+ unsigned int p4_idx;
+ unsigned int p6_idx;
+ unsigned int min_len;
+ unsigned int p1_mul;
+ unsigned int p1_div;
+};
+
/**
* struct at91_adc_platform - at91-sama5d2 platform information struct
* @layout: pointer to the reg layout struct
@@ -463,6 +486,7 @@ static const struct at91_adc_reg_layout sama7g5_layout = {
* @oversampling_avail_no: number of available oversampling values
* @chan_realbits: realbits for registered channels
* @temp_chan: temperature channel index
+ * @temp_calib_layout: temperature calibration packet layout
* @temp_sensor: temperature sensor supported
*/
struct at91_adc_platform {
@@ -480,6 +504,7 @@ struct at91_adc_platform {
unsigned int oversampling_avail_no;
unsigned int chan_realbits;
unsigned int temp_chan;
+ const struct at91_adc_temp_calib_layout *temp_calib_layout;
bool temp_sensor;
};
@@ -496,18 +521,14 @@ struct at91_adc_temp_sensor_clb {
u32 p6;
};
-/**
- * enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer
- * @AT91_ADC_TS_CLB_IDX_P1: index for P1
- * @AT91_ADC_TS_CLB_IDX_P4: index for P4
- * @AT91_ADC_TS_CLB_IDX_P6: index for P6
- * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet in OTP
- */
-enum at91_adc_ts_clb_idx {
- AT91_ADC_TS_CLB_IDX_P1 = 2,
- AT91_ADC_TS_CLB_IDX_P4 = 5,
- AT91_ADC_TS_CLB_IDX_P6 = 7,
- AT91_ADC_TS_CLB_IDX_MAX = 19,
+static const struct at91_adc_temp_calib_layout sama7g5_temp_calib = {
+ .tag_idx = 1,
+ .p1_idx = 2,
+ .p4_idx = 5,
+ .p6_idx = 7,
+ .min_len = 19,
+ .p1_mul = 1000,
+ .p1_div = 1,
};
/* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */
@@ -745,6 +766,7 @@ static const struct at91_adc_platform sama7g5_platform = {
.chan_realbits = 16,
.temp_sensor = true,
.temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL,
+ .temp_calib_layout = &sama7g5_temp_calib,
};
static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
@@ -2250,6 +2272,7 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
struct device *dev)
{
struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
+ const struct at91_adc_temp_calib_layout *layout;
struct nvmem_cell *temp_calib;
u32 *buf __free(kfree) = NULL;
void *cell_data;
@@ -2259,6 +2282,10 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
if (!st->soc_info.platform->temp_sensor)
return 0;
+ layout = st->soc_info.platform->temp_calib_layout;
+ if (!layout || !layout->p1_div)
+ return -EINVAL;
+
/* Get the calibration data from NVMEM. */
temp_calib = nvmem_cell_get(dev, "temperature_calib");
if (IS_ERR(temp_calib)) {
@@ -2277,20 +2304,24 @@ static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
buf = cell_data;
- if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) {
+ if (len < layout->min_len * sizeof(*buf) ||
+ buf[layout->tag_idx] != AT91_TEMP_CALIB_TAG_ACST) {
dev_err(dev, "Invalid calibration data!\n");
return -EINVAL;
}
/* Store calibration data for later use. */
- clb->p1 = buf[AT91_ADC_TS_CLB_IDX_P1];
- clb->p4 = buf[AT91_ADC_TS_CLB_IDX_P4];
- clb->p6 = buf[AT91_ADC_TS_CLB_IDX_P6];
+ clb->p1 = buf[layout->p1_idx];
+ clb->p4 = buf[layout->p4_idx];
+ clb->p6 = buf[layout->p6_idx];
/*
- * We prepare here the conversion to milli to avoid doing it on hotpath.
+ * Here we prepare the conversion to milli to avoid doing it on hotpath.
+ * The p1 value is multiplied and divided with a scaling factor as per
+ * the SoC storage format described by per-platform calibration layout.
*/
- clb->p1 = clb->p1 * 1000;
+ clb->p1 *= layout->p1_mul;
+ clb->p1 /= layout->p1_div;
return 0;
}
--
2.34.1
^ permalink raw reply related
* [PATCH v3 04/13] iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65
From: Varshini Rajendran @ 2026-06-30 9:35 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add support for sama7d65 ADC. The differences are highlighted with the
compatible. The calibration data layout is the main difference.
Update Kconfig help text to mention SAMA7 SoC family support.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
drivers/iio/adc/Kconfig | 2 +-
drivers/iio/adc/at91-sama5d2_adc.c | 31 ++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index a9dedbb8eb46..cf28755a6109 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -626,7 +626,7 @@ config AT91_SAMA5D2_ADC
select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for Atmel SAMA5D2 ADC which is
- available on SAMA5D2 SoC family.
+ available on SAMA5D2 and SAMA7 SoC families.
To compile this driver as a module, choose M here: the module will be
called at91-sama5d2_adc.
diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c
index 2a25165bc874..7e3e347bb6a5 100644
--- a/drivers/iio/adc/at91-sama5d2_adc.c
+++ b/drivers/iio/adc/at91-sama5d2_adc.c
@@ -531,6 +531,16 @@ static const struct at91_adc_temp_calib_layout sama7g5_temp_calib = {
.p1_div = 1,
};
+static const struct at91_adc_temp_calib_layout sama7d65_temp_calib = {
+ .tag_idx = 1,
+ .p1_idx = 3,
+ .p4_idx = 2,
+ .p6_idx = 5,
+ .min_len = 11,
+ .p1_mul = 1,
+ .p1_div = 1000,
+};
+
/* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */
#define AT91_ADC_TS_VTEMP_DT (2080U)
@@ -769,6 +779,24 @@ static const struct at91_adc_platform sama7g5_platform = {
.temp_calib_layout = &sama7g5_temp_calib,
};
+static const struct at91_adc_platform sama7d65_platform = {
+ .layout = &sama7g5_layout,
+ .adc_channels = &at91_sama7g5_adc_channels,
+ .nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT +
+ AT91_SAMA7G5_DIFF_CHAN_CNT +
+ AT91_SAMA7G5_TEMP_CHAN_CNT,
+ .max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels),
+ .max_index = AT91_SAMA7G5_MAX_CHAN_IDX,
+ .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT,
+ .osr_mask = GENMASK(18, 16),
+ .oversampling_avail = { 1, 4, 16, 64, 256, },
+ .oversampling_avail_no = 5,
+ .chan_realbits = 16,
+ .temp_sensor = true,
+ .temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL,
+ .temp_calib_layout = &sama7d65_temp_calib,
+};
+
static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
{
int i;
@@ -2639,6 +2667,9 @@ static const struct of_device_id at91_adc_dt_match[] = {
}, {
.compatible = "microchip,sama7g5-adc",
.data = (const void *)&sama7g5_platform,
+ }, {
+ .compatible = "microchip,sama7d65-adc",
+ .data = (const void *)&sama7d65_platform,
}, {
/* sentinel */
}
--
2.34.1
^ permalink raw reply related
* [PATCH v3 05/13] dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node example
From: Varshini Rajendran @ 2026-06-30 9:35 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
Cc: Conor Dooley
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add support for sama7d65 and a dt node example that shows tag can be used
to reference a packet stored in the OTP memory.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../nvmem/microchip,sama7g5-otpc.yaml | 28 +++++++++++++++++--
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
index cc25f2927682..04b44660554e 100644
--- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
+++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
@@ -20,9 +20,15 @@ allOf:
properties:
compatible:
- items:
- - const: microchip,sama7g5-otpc
- - const: syscon
+ oneOf:
+ - items:
+ - const: microchip,sama7g5-otpc
+ - const: syscon
+ - items:
+ - enum:
+ - microchip,sama7d65-otpc
+ - const: microchip,sama7g5-otpc
+ - const: syscon
reg:
maxItems: 1
@@ -48,4 +54,20 @@ examples:
};
};
+ - |
+ efuse@e8c00000 {
+ compatible = "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "syscon";
+ reg = <0xe8c00000 0x100>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ calib@41435354 {
+ reg = <0x41435354 0x2c>; /* Temp calib data packet TAG */
+ };
+ };
+ };
+
...
--
2.34.1
^ permalink raw reply related
* [PATCH v3 06/13] nvmem: microchip-otpc: add tag-based packet lookup
From: Varshini Rajendran @ 2026-06-30 9:35 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add support for accessing OTP packets by their 4-byte ASCII tag while
preserving backward compatibility with the existing ID-based lookup.
The OTP memory layout can vary across devices and may change over time,
making the packet ID approach unreliable when the memory map is not
known in advance. The packet tag provides a reliable way to identify
and access packets without prior knowledge of the OTP memory layout.
Two offset encoding are now supported:
1. Legacy ID-based: offset = OTP_PKT(id) = id * 4
Used in DT as: reg = <OTP_PKT(1) 76>;
2. TAG-based: offset = 4-byte ASCII packet tag
Used in DT as: reg = <0x41435354 0x4c>; (tag "ACST")
The driver resolves offsets matching valid legacy selectors (multiples
of 4 within the packet count) through ID lookup, falling back to tag
lookup for other values. This ensures existing device trees continue
to work while enabling new tag-based access.
During probe, packet meta data including the tag is read and cached.
The driver also validates OTP memory accessibility and emulation mode
status. When the boot packet is not configured, emulation mode allows
access to the other packets. When both are not available an
informational message is logged.
The stride of the nvmem memory is set to 1 in order to support tag based
offsets, comment in the header file is updated accordingly.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
drivers/nvmem/microchip-otpc.c | 143 ++++++++++++++++--
.../nvmem/microchip,sama7g5-otpc.h | 4 +-
2 files changed, 136 insertions(+), 11 deletions(-)
diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index df979e8549fd..bf8589048e17 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -18,16 +18,20 @@
#define MCHP_OTPC_CR_READ BIT(6)
#define MCHP_OTPC_MR (0x4)
#define MCHP_OTPC_MR_ADDR GENMASK(31, 16)
+#define MCHP_OTPC_MR_EMUL BIT(7)
#define MCHP_OTPC_AR (0x8)
#define MCHP_OTPC_SR (0xc)
#define MCHP_OTPC_SR_READ BIT(6)
#define MCHP_OTPC_HR (0x20)
#define MCHP_OTPC_HR_SIZE GENMASK(15, 8)
+#define MCHP_OTPC_HR_PACKET_TYPE GENMASK(2, 0)
#define MCHP_OTPC_DR (0x24)
#define MCHP_OTPC_NAME "mchp-otpc"
#define MCHP_OTPC_SIZE (11 * 1024)
+#define PACKET_TYPE_REGULAR 1
+
/**
* struct mchp_otpc - OTPC private data structure
* @base: base address
@@ -47,11 +51,15 @@ struct mchp_otpc {
* @list: list head
* @id: packet ID
* @offset: packet offset (in words) in OTP memory
+ * @type: type of the packet
+ * @tag: 4-byte ASCII tag of the packet
*/
struct mchp_otpc_packet {
struct list_head list;
u32 id;
u32 offset;
+ u32 type;
+ u32 tag;
};
static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *otpc,
@@ -70,6 +78,56 @@ static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *otpc,
return NULL;
}
+/**
+ * mchp_otpc_tag_to_packet() - find packet by tag
+ * @otpc: OTPC private data
+ * @tag: 4-byte ASCII tag to search for
+ *
+ * Return: pointer to packet if found, NULL otherwise
+ */
+static struct mchp_otpc_packet *mchp_otpc_tag_to_packet(struct mchp_otpc *otpc,
+ u32 tag)
+{
+ struct mchp_otpc_packet *packet;
+
+ list_for_each_entry(packet, &otpc->packets, list) {
+ if (packet->tag == tag)
+ return packet;
+ }
+
+ return NULL;
+}
+
+/**
+ * mchp_otpc_resolve_packet() - resolve offset to packet
+ * @otpc: OTPC private data
+ * @off: NVMEM offset (legacy ID-based or TAG-based)
+ *
+ * Legacy offsets (multiples of 4 within valid ID range) are resolved
+ * through ID lookup. Other offsets are treated as 4-byte ASCII tags.
+ *
+ * Return: pointer to packet if found, NULL otherwise
+ */
+static struct mchp_otpc_packet *mchp_otpc_resolve_packet(struct mchp_otpc *otpc,
+ u32 off)
+{
+ /*
+ * Legacy id based packet access: offset = id * 4
+ * Inside the driver we use continuous unsigned integer numbers
+ * for packet id, thus divide off by 4 before passing it to
+ * mchp_otpc_id_to_packet().
+ */
+ u32 id = off / 4;
+
+ if (!(off % 4) && id < otpc->npackets)
+ return mchp_otpc_id_to_packet(otpc, id);
+
+ /*
+ * TAG-based packet access: offset is a 4-byte ASCII tag
+ */
+ return mchp_otpc_tag_to_packet(otpc, off);
+}
+
static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
unsigned int offset)
{
@@ -140,8 +198,29 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
* offset returned by hardware.
*
* For this, the read function will return the first requested bytes in the
- * packet. The user will have to be aware of the memory footprint before doing
- * the read request.
+ * packet.
+ *
+ * Two offset encoding are supported:
+ *
+ * 1. Legacy ID-based: offset = OTP_PKT(id) = id * 4
+ * Used in DT as: reg = <OTP_PKT(1) 76>;
+ * 2. TAG-based: offset = 4-byte ASCII packet tag
+ * Used in DT as: reg = <0x41435354 0x4c>; (tag "ACST")
+ *
+ * To use the legacy ID based packet lookup the user will have to be aware of
+ * the memory footprint before doing the read request.
+ *
+ * But by using the TAG based packet lookup, the user won't have to be aware
+ * of the memory footprint before doing the read request since this driver has
+ * it abstracted and taken care of.
+ *
+ * Practically, there is no way of knowing the mapping of the OTP memory table
+ * in advance for every device. But by using the packet tag - the identifier
+ * ASCII value, the packets can be recognized without being aware of the
+ * flashed OTP memory map table and the payload can be acquired reliably.
+ *
+ * While the legacy ID based lookup is still supported, TAG based approach is
+ * recommended.
*/
static int mchp_otpc_read(void *priv, unsigned int off, void *val,
size_t bytes)
@@ -154,12 +233,11 @@ static int mchp_otpc_read(void *priv, unsigned int off, void *val,
int ret, payload_size;
/*
- * We reach this point with off being multiple of stride = 4 to
- * be able to cross the subsystem. Inside the driver we use continuous
- * unsigned integer numbers for packet id, thus divide off by 4
- * before passing it to mchp_otpc_id_to_packet().
+ * From this point the offset has to be translated into the actual
+ * packet. For this we traverse the table of contents stored in a list
+ * "packet" based on the access type - packet id or tag.
*/
- packet = mchp_otpc_id_to_packet(otpc, off / 4);
+ packet = mchp_otpc_resolve_packet(otpc, off);
if (!packet)
return -EINVAL;
offset = packet->offset;
@@ -190,6 +268,29 @@ static int mchp_otpc_read(void *priv, unsigned int off, void *val,
return 0;
}
+/**
+ * mchp_otpc_read_packet_tag() - read tag from packet payload
+ * @otpc: OTPC private data
+ * @offset: packet offset in OTP memory
+ * @val: pointer to store the tag value
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int mchp_otpc_read_packet_tag(struct mchp_otpc *otpc, unsigned int offset,
+ unsigned int *val)
+{
+ int ret;
+
+ ret = mchp_otpc_prepare_read(otpc, offset);
+ if (ret)
+ return ret;
+
+ writel_relaxed(0, otpc->base + MCHP_OTPC_AR);
+ *val = readl_relaxed(otpc->base + MCHP_OTPC_DR);
+
+ return 0;
+}
+
static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
{
struct mchp_otpc_packet *packet;
@@ -215,6 +316,17 @@ static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
packet->id = id++;
packet->offset = word_pos;
+ packet->type = FIELD_GET(MCHP_OTPC_HR_PACKET_TYPE, word);
+
+ if (packet->type == PACKET_TYPE_REGULAR) {
+ ret = mchp_otpc_read_packet_tag(otpc, packet->offset,
+ &packet->tag);
+ if (ret)
+ return ret;
+ } else {
+ packet->tag = 0;
+ }
+
INIT_LIST_HEAD(&packet->list);
list_add_tail(&packet->list, &otpc->packets);
@@ -236,7 +348,7 @@ static struct nvmem_config mchp_nvmem_config = {
.type = NVMEM_TYPE_OTP,
.read_only = true,
.word_size = 4,
- .stride = 4,
+ .stride = 1,
.reg_read = mchp_otpc_read,
};
@@ -244,7 +356,8 @@ static int mchp_otpc_probe(struct platform_device *pdev)
{
struct nvmem_device *nvmem;
struct mchp_otpc *otpc;
- u32 size;
+ bool emul_enable;
+ u32 size, tmp;
int ret;
otpc = devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL);
@@ -256,10 +369,22 @@ static int mchp_otpc_probe(struct platform_device *pdev)
return PTR_ERR(otpc->base);
otpc->dev = &pdev->dev;
+
+ tmp = readl_relaxed(otpc->base + MCHP_OTPC_MR);
+ emul_enable = tmp & MCHP_OTPC_MR_EMUL;
+ if (emul_enable)
+ dev_info(otpc->dev, "Emulation mode enabled\n");
+
ret = mchp_otpc_init_packets_list(otpc, &size);
if (ret)
return ret;
+ if (!size) {
+ dev_warn(otpc->dev, "Cannot access OTP memory\n");
+ if (!emul_enable)
+ dev_info(otpc->dev, "Boot packet not programmed and emulation mode disabled\n");
+ }
+
mchp_nvmem_config.dev = otpc->dev;
mchp_nvmem_config.add_legacy_fixed_of_cells = true;
mchp_nvmem_config.size = size;
diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
index f570b23165a2..5f72e75ad091 100644
--- a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
+++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
@@ -4,8 +4,8 @@
#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H
/*
- * Need to have it as a multiple of 4 as NVMEM memory is registered with
- * stride = 4.
+ * Need to have it as a multiple of 4 for the legacy id based packet
+ * access.
*/
#define OTP_PKT(id) ((id) * 4)
--
2.34.1
^ permalink raw reply related
* [PATCH v3 07/13] ARM: dts: microchip: sama7d65: add cpu opps
From: Varshini Rajendran @ 2026-06-30 9:35 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add CPU OPPs table for SAMA7D65.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 36 +++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 67253bbc08df..94d49e20dc79 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -35,6 +35,7 @@ cpu0: cpu@0 {
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
+ operating-points-v2 = <&cpu_opp_table>;
L2: l2-cache {
compatible = "cache";
@@ -45,6 +46,41 @@ L2: l2-cache {
};
};
+ cpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-90000000 {
+ opp-hz = /bits/ 64 <90000000>;
+ opp-microvolt = <1050000 1050000 1225000>;
+ clock-latency-ns = <320000>;
+ };
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1050000 1050000 1225000>;
+ clock-latency-ns = <320000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1050000 1050000 1225000>;
+ clock-latency-ns = <320000>;
+ opp-suspend;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1150000 1125000 1225000>;
+ clock-latency-ns = <320000>;
+ };
+
+ opp-1000000002 {
+ opp-hz = /bits/ 64 <1000000002>;
+ opp-microvolt = <1250000 1225000 1300000>;
+ clock-latency-ns = <320000>;
+ };
+ };
+
clocks {
main_xtal: clock-mainxtal {
compatible = "fixed-clock";
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v7 3/4] reset: cix: add sky1 audss auxiliary reset driver
From: Philipp Zabel @ 2026-06-30 9:37 UTC (permalink / raw)
To: joakim.zhang, mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt
Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260629091500.52540-4-joakim.zhang@cixtech.com>
On Mo, 2026-06-29 at 17:14 +0800, joakim.zhang@cixtech.com wrote:
> From: Joakim Zhang <joakim.zhang@cixtech.com>
>
> Add an auxiliary reset controller driver for the AUDSS CRU. Sixteen
> software reset lines for audio subsystem peripherals are controlled
> through one register in the CRU register map.
>
> The driver is created by the AUDSS clock platform driver and registers
> the reset controller on the CRU device node.
>
> Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com>
> ---
> drivers/reset/Kconfig | 14 ++++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-sky1-audss.c | 137 +++++++++++++++++++++++++++++++
> 3 files changed, 152 insertions(+)
> create mode 100644 drivers/reset/reset-sky1-audss.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index d009eb0849a3..f74859b292ae 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -300,6 +300,20 @@ config RESET_SKY1
> help
> This enables the reset controller for Cix Sky1.
>
> +config RESET_SKY1_AUDSS
> + tristate "Cix Sky1 Audio Subsystem reset controller"
> + depends on ARCH_CIX || COMPILE_TEST
> + select AUXILIARY_BUS
> + select REGMAP_MMIO
This driver doesn't need REGMAP_MMIO itself, it just inherits its
parent's regmap.
regards
Philipp
^ permalink raw reply
* [PATCH v3 08/13] ARM: dts: microchip: sama7d65: Add ADC node
From: Varshini Rajendran @ 2026-06-30 9:35 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add node for the ADC controller in sama7d65 SoC. Add the vddout25 fixed
regulator node which provides the 2.5V reference voltage for the ADC.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 29 +++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 94d49e20dc79..ba775459a816 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/at91-usart.h>
@@ -95,6 +96,16 @@ slow_xtal: clock-slowxtal {
};
};
+ vddout25: fixed-regulator-vddout25 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VDDOUT25";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-boot-on;
+ status = "disabled";
+ };
+
ns_sram: sram@100000 {
compatible = "mmio-sram";
reg = <0x100000 0x20000>;
@@ -296,6 +307,24 @@ can4: can@e0838000 {
status = "disabled";
};
+ adc: adc@e1000000 {
+ compatible = "microchip,sama7d65-adc";
+ reg = <0xe1000000 0x200>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_GCK 25>;
+ assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+ assigned-clock-rates = <100000000>;
+ clock-names = "adc_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
+ dma-names = "rx";
+ atmel,min-sample-rate-hz = <200000>;
+ atmel,max-sample-rate-hz = <20000000>;
+ atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+ atmel,startup-time-ms = <4>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
dma2: dma-controller@e1200000 {
compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
reg = <0xe1200000 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v3 09/13] ARM: dts: microchip: sama7d65_curiosity: Enable ADC, DVFS
From: Varshini Rajendran @ 2026-06-30 9:35 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add regulator, pinmux and enable ADC for sama7d65 curiosity. Add
cpu-supply regulator for DVFS.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
.../dts/microchip/at91-sama7d65_curiosity.dts | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
index 927c27260b6c..c2d1e5308170 100644
--- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
+++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
@@ -79,6 +79,14 @@ reg_5v: regulator-5v {
};
};
+&adc {
+ vddana-supply = <&vddout25>;
+ vref-supply = <&vddout25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+ status = "okay";
+};
+
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
@@ -97,6 +105,10 @@ &can3 {
status = "okay";
};
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+};
+
&dma0 {
status = "okay";
};
@@ -334,6 +346,16 @@ &main_xtal {
};
&pioa {
+ pinctrl_adc_default: adc-default {
+ pinmux = <PIN_PC5__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_adtrg_default: adtrg-default {
+ pinmux = <PIN_PB7__ADTRG>;
+ bias-pull-up;
+ };
+
pinctrl_can1_default: can1-default {
pinmux = <PIN_PD10__CANTX1>,
<PIN_PD11__CANRX1>;
@@ -457,3 +479,8 @@ input@0 {
&slow_xtal {
clock-frequency = <32768>;
};
+
+&vddout25 {
+ vin-supply = <&vdd_3v3>;
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related
* [PATCH v3 10/13] ARM: dts: microchip: sama7d65: add otpc node
From: Varshini Rajendran @ 2026-06-30 9:36 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add OTPC node along with temperature calibration cell.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index ba775459a816..5867fda378b1 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/at91-usart.h>
+#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
/ {
model = "Microchip SAMA7D65 family SoC";
@@ -1112,6 +1113,21 @@ ddr3phy: ddr3phy@e3804000 {
reg = <0xe3804000 0x1000>;
};
+ otpc: efuse@e8c00000 {
+ compatible = "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "syscon";
+ reg = <0xe8c00000 0x100>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ temperature_calib: calib@41435354 {
+ reg = <0x41435354 0x2c>; /* Temp calib data packet TAG */
+ };
+ };
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,cortex-a7-gic";
reg = <0xe8c11000 0x1000>,
--
2.34.1
^ permalink raw reply related
* [PATCH v3 11/13] ARM: dts: microchip: sama7d65: add cells for temperature calibration
From: Varshini Rajendran @ 2026-06-30 9:36 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add NVMEM cell to ADC for temperature calibration data.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 5867fda378b1..c336f863406d 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -323,6 +323,8 @@ adc: adc@e1000000 {
atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
atmel,startup-time-ms = <4>;
#io-channel-cells = <1>;
+ nvmem-cells = <&temperature_calib>;
+ nvmem-cell-names = "temperature_calib";
status = "disabled";
};
--
2.34.1
^ permalink raw reply related
* [PATCH v3 12/13] ARM: dts: microchip: sama7d65: add temperature sensor
From: Varshini Rajendran @ 2026-06-30 9:36 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add temperature sensor node.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index c336f863406d..89904397d021 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -120,6 +120,13 @@ pmu {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
};
+ thermal_sensor: thermal-sensor {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>;
+ io-channel-names = "sensor-channel";
+ };
+
soc {
compatible = "simple-bus";
ranges;
--
2.34.1
^ permalink raw reply related
* [PATCH v3 13/13] ARM: dts: microchip: sama7d65: add thermal zones node
From: Varshini Rajendran @ 2026-06-30 9:36 UTC (permalink / raw)
To: ehristev, jic23, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni, claudiu.beznea, srini,
marcelo.schmitt, jorge.marques, mazziesaccount, Jonathan.Santos,
jishnu.prakash, antoniu.miclaus, duje, varshini.rajendran,
linux-iio, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com>
Add thermal zones node with its associated trips and cooling-maps.
It uses CPUFreq as cooling device for temperatures in the interval
[90, 100) degrees Celsius and describe the temperature of 100 degrees
Celsius as critical temperature. System will shut down when reaching
critical temperature.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 42 +++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 89904397d021..f2140010d337 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -16,6 +16,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
model = "Microchip SAMA7D65 family SoC";
@@ -38,6 +39,7 @@ cpu0: cpu@0 {
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
L2: l2-cache {
compatible = "cache";
@@ -127,6 +129,46 @@ thermal_sensor: thermal-sensor {
io-channel-names = "sensor-channel";
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&thermal_sensor>;
+
+ trips {
+ cpu_normal: cpu-alert0 {
+ temperature = <90000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ cpu_hot: cpu-alert1 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ cpu_critical: cpu-critical {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_normal>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
ranges;
--
2.34.1
^ permalink raw reply related
* [PATCH v3] ARM: entry: expand comment in __switch_to
From: Linus Walleij @ 2026-06-30 9:38 UTC (permalink / raw)
To: Russell King, Ard Biesheuvel
Cc: linux-arm-kernel, Mark Rutland, Linus Walleij
From: Linus Walleij <linus.walleij@linaro.org>
As per discussion between the developers in the mail thread
linked, expand the comment in __switch_to so that readers
of the code understand what is going on.
Link: https://lore.kernel.org/linux-arm-kernel/ZxDh9biUbf9W8gNN@J2N7QTR9R3/
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
---
Changes in v3:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v2: https://lore.kernel.org/r/20251216-comments-in-switch-to-v2-1-190d8741db14@kernel.org
Changes in v2:
- Rebased on v6.19-rc1
- Link to v1: https://lore.kernel.org/r/20241028-comments-in-switch-to-v1-0-7280d09671a8@linaro.org
---
| 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
--git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index a3d050ce9b79..2d2ea3ca880c 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -557,9 +557,16 @@ ENTRY(__switch_to)
ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously
#ifdef CONFIG_VMAP_STACK
@
- @ Do a dummy read from the new stack while running from the old one so
- @ that we can rely on do_translation_fault() to fix up any stale PMD
- @ entries covering the vmalloc region.
+ @ For a non-lazy mm switch, check_vmalloc_seq() has ensured that
+ @ that the active mm's page tables have mappings for the prev
+ @ task's stack and the next task's stack.
+ @
+ @ For a lazy mm switch the active mm's page tables have mappings
+ @ for the prev task's stack but might not have mappings for the
+ @ new task's stack. Do a dummy read from the new stack while
+ @ running from the old stack so that we can rely on
+ @ do_translation_fault() to populate missing PMD entries covering the
+ @ new task's stack in the old task's page tables.
@
ldr r2, [ip]
#ifdef CONFIG_KASAN_VMALLOC
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20241028-comments-in-switch-to-0e24480e8495
Best regards,
--
Linus Walleij <linusw@kernel.org>
^ permalink raw reply related
* Re: [PATCH] firmware: arm_scmi: Grammar s/may needed/may be needed/
From: Sudeep Holla @ 2026-06-30 9:40 UTC (permalink / raw)
To: Cristian Marussi, Geert Uytterhoeven
Cc: Sudeep Holla, arm-scmi, linux-arm-kernel, linux-kernel
In-Reply-To: <5180d04abfb8e3074a321e2eb73bacfdd61c30c5.1780499850.git.geert+renesas@glider.be>
On Wed, 03 Jun 2026 17:17:51 +0200, Geert Uytterhoeven wrote:
> Fix grammar in the help text for the ARM_SCMI_POWER_CONTROL symbol.
Applied to sudeep.holla/linux (for-next/scmi/fixes), thanks!
[1/1] firmware: arm_scmi: Grammar s/may needed/may be needed/
https://git.kernel.org/sudeep.holla/c/05e5ffde9b666
--
Regards,
Sudeep
^ permalink raw reply
* Re: [PATCH v3 12/17] arm64: dts: nvidia: Add EL2 virtual timer interrupt
From: Jon Hunter @ 2026-06-30 9:42 UTC (permalink / raw)
To: Marc Zyngier, linux-arm-kernel, linux-acpi, linux-kernel,
devicetree, linux-tegra@vger.kernel.org
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Bjorn Andersson, Konrad Dybcio, Andreas Färber,
Yu-Chun Lin [林祐君], Heiko Stuebner, Shawn Lin,
Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-13-maz@kernel.org>
Hi Marc,
On 23/05/2026 15:02, Marc Zyngier wrote:
> The ARMv8.2 based CPUs used in a number of nvidia SoCs are missing
> the EL2 virtual timer interrupt. Add it.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 ++
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 3 ++-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 849694f751d90..45cc180ac9973 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -3163,6 +3163,8 @@ timer {
> <GIC_PPI 11
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 12
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> always-on;
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index 04a95b6658caa..ab9813f9ba30c 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -5872,7 +5872,8 @@ timer {
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> always-on;
> };
Sorry for the delay. I gave this a test because I observed the warning
that was added on the Tegra194 and Tegra234 platforms. This change fixes
the warning for Tegra234, but on Tegra194 the platforms I tested hang on
boot. It appears to be similar to the issue that Marek saw on his
platforms and so I am wondering if Tegra194 also doesn't have this wired up?
Was there any resolution to the issue reported by Marek?
FYI, the Tegra194 SoC has the 'NVIDIA Carmel ARM v8.2' CPUs [0].
Jon
[0]
https://www.nvidia.com/en-gb/autonomous-machines/embedded-systems/jetson-xavier-series/
--
nvpublic
^ permalink raw reply
* [PATCH v6 10/16] arm64: dts: st: add sai1 pins for stm32mp25
From: Dario Binacchi @ 2026-06-30 9:24 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, francesco.utel, michael, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260630092628.1695560-1-dario.binacchi@amarulasolutions.com>
Add the sai1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 695c9d771853..002fbc724b9d 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -520,6 +520,51 @@ pins {
};
};
+ /omit-if-no-ref/
+ sai1a_pins_a: sai1a-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 9, AF3)>, /* SAI1_SD_A */
+ <STM32_PINMUX('D', 8, AF3)>, /* SAI1_FS_A */
+ <STM32_PINMUX('D', 10, AF3)>; /* SAI1_SCK_A */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 11, AF3)>; /* SAI1_MCLK_A */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1a_sleep_pins_a: sai1a-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('D', 8, ANALOG)>, /* SAI1_FS_A */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 11, ANALOG)>; /* SAI1_MCLK_A */
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1b_pins_a: sai1b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, AF4)>; /* SAI1_SD_B */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1b_sleep_pins_a: sai1b-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>; /* SAI1_SD_B */
+ };
+ };
+
/omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v1 0/3] Add support for Variscite VAR-SOM-MX8QM and Symphony board
From: Stefano Radaelli @ 2026-06-30 9:46 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Dario Binacchi,
Josua Mayer, Alexander Stein, Ernest Van Hoecke, Maud Spierings,
Francesco Dolcini, Hugo Villeneuve
This patch series adds support for the Variscite VAR-SOM-MX8 QuadMax
system on module and the Symphony carrier board.
The series includes:
- SOM device tree with on-module peripherals
- Symphony carrier board device tree with board-specific features
The implementation follows the standard SOM + carrier board pattern
where the SOM dtsi contains only peripherals mounted on the module,
while carrier-specific interfaces are enabled in the board dts.
Stefano Radaelli (3):
dt-bindings: arm: fsl: add Variscite VAR-SOM-MX8 QuadMax Boards
arm64: dts: freescale: Add support for Variscite VAR-SOM-MX8 QuadMax
arm64: dts: imx8qm-var-som: Add support for Variscite Symphony board
.../devicetree/bindings/arm/fsl.yaml | 6 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8qm-var-som-symphony.dts | 488 ++++++++++++++++
.../boot/dts/freescale/imx8qm-var-som.dtsi | 529 ++++++++++++++++++
4 files changed, 1024 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi
base-commit: 6d1a5ede11552f559ac02b31af03bfaa67f1e91f
--
2.47.3
^ permalink raw reply
* [PATCH v1 1/3] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX8 QuadMax Boards
From: Stefano Radaelli @ 2026-06-30 9:46 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Dario Binacchi,
Josua Mayer, Alexander Stein, Ernest Van Hoecke, Maud Spierings,
Francesco Dolcini, Hugo Villeneuve
In-Reply-To: <cover.1782812572.git.stefano.r@variscite.com>
From: Stefano Radaelli <stefano.r@variscite.com>
Add DT compatible strings for Variscite VAR-SOM-MX8 QuadMax SoM and
Variscite Symphony development carrier Board.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 86876311ec59..242a58eeb314 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1369,6 +1369,12 @@ properties:
- fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board
- const: fsl,imx8qm
+ - description: i.MX8QM Variscite VAR-SOM-MX8 based Boards
+ items:
+ - const: variscite,var-som-imx8qm-symphony
+ - const: variscite,var-som-imx8qm
+ - const: fsl,imx8qm
+
- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
items:
- enum:
--
2.47.3
^ permalink raw reply related
* [PATCH v1 2/3] arm64: dts: freescale: Add support for Variscite VAR-SOM-MX8 QuadMax
From: Stefano Radaelli @ 2026-06-30 9:46 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Dario Binacchi,
Josua Mayer, Alexander Stein, Ernest Van Hoecke, Maud Spierings,
Francesco Dolcini, Hugo Villeneuve
In-Reply-To: <cover.1782812572.git.stefano.r@variscite.com>
From: Stefano Radaelli <stefano.r@variscite.com>
Add device tree support for the Variscite VAR-SOM-MX8 QuadMax
system on module.
This SOM is designed to be used with various carrier boards.
The module includes:
- NXP i.MX8 QuadMax MPU processor
- Up to 8GB of LPDDR4 memory
- Up to 128GB of eMMC storage memory
- Integrated 10/100/1000 Mbps Ethernet Transceiver
- Codec audio WM8904
- WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth
Only SOM-specific peripherals are enabled by default. Carrier board
specific interfaces are left disabled to be enabled in the respective
carrier board device trees.
Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
.../boot/dts/freescale/imx8qm-var-som.dtsi | 529 ++++++++++++++++++
1 file changed, 529 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi
new file mode 100644
index 000000000000..2ffc32ddbf51
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common dtsi for Variscite VAR-SOM-MX8
+ *
+ * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8qm.dtsi"
+
+/ {
+ model = "Variscite i.MX8QM VAR-SOM-MX8 Module";
+ compatible = "variscite,var-som-imx8qm", "fsl,imx8qm";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
+
+ reg_audio_supply: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8904-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_phy_vddio: regulator-phy-vddio {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ vdev0vring0: memory@90000000 {
+ reg = <0 0x90000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: memory@90008000 {
+ reg = <0 0x90008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: memory@90010000 {
+ reg = <0 0x90010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: memory@90018000 {
+ reg = <0 0x90018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table0: memory@900ff000 {
+ reg = <0 0x900ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdev2vring0: memory@90100000 {
+ reg = <0 0x90100000 0 0x8000>;
+ no-map;
+ };
+
+ vdev2vring1: memory@90108000 {
+ reg = <0 0x90108000 0 0x8000>;
+ no-map;
+ };
+
+ vdev3vring0: memory@90110000 {
+ reg = <0 0x90110000 0 0x8000>;
+ no-map;
+ };
+
+ vdev3vring1: memory@90118000 {
+ reg = <0 0x90118000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table1: memory@901ff000 {
+ reg = <0 0x901ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: memory@90400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x90400000 0 0x100000>;
+ no-map;
+ };
+
+ dsp_reserved: memory@92400000 {
+ reg = <0 0x92400000 0 0x1000000>;
+ no-map;
+ };
+
+ dsp_vdev0vring0: memory@942f0000 {
+ reg = <0 0x942f0000 0 0x8000>;
+ no-map;
+ };
+
+ dsp_vdev0vring1: memory@942f8000 {
+ reg = <0 0x942f8000 0 0x8000>;
+ no-map;
+ };
+
+ dsp_vdev0buffer: memory@94300000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x94300000 0 0x100000>;
+ no-map;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0xc0000000 0 0x3c000000>;
+ size = <0 0x3c000000>;
+ linux,cma-default;
+ reusable;
+ };
+ };
+
+ sound-wm8904 {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "wm8904-audio";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "IN1L", "Microphone Jack",
+ "IN1R", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8904>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&esai0>;
+ };
+ };
+};
+
+&acm {
+ status = "okay";
+};
+
+&asrc0 {
+ fsl,asrc-rate = <48000>;
+ status = "okay";
+};
+
+&asrc1 {
+ fsl,asrc-rate = <48000>;
+ status = "okay";
+};
+
+&cm41_intmux {
+ status = "okay";
+};
+
+&esai0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esai0>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&esai0_lpcg 0>;
+ assigned-clock-parents = <&aud_pll_div0_lpcg 0>;
+ assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ /*
+ * The required RGMII TX and RX 2ns delays are implemented directly
+ * in hardware via passive delay elements on the SOM PCB.
+ * No delay configuration is needed in software via PHY driver.
+ */
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ reset-gpios = <&lsio_gpio2 28 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+ vddio-supply = <®_phy_vddio>;
+ };
+ };
+};
+
+&gpio0_mipi_csi0 {
+ status = "disabled";
+};
+
+&gpio0_mipi_csi1 {
+ status = "disabled";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ status = "okay";
+
+ wm8904: codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ clocks = <&mclkout0_lpcg 0>;
+ clock-names = "mclk";
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&mclkout0_lpcg 0>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
+ AVDD-supply = <®_audio_supply>;
+ CPVDD-supply = <®_audio_supply>;
+ DBVDD-supply = <®_audio_supply>;
+ DCVDD-supply = <®_audio_supply>;
+ MICVDD-supply = <®_audio_supply>;
+ wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+ "soft", "music";
+ /*
+ * Config registers per name, respectively:
+ * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
+ * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
+ * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
+ * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
+ * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+ */
+ wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+ /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+ /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+ /* GPIO1 = DMIC_CLK, don't touch others */
+ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+ };
+};
+
+/* Bluetooth */
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&mu_m0{
+ status = "okay";
+};
+
+&mu1_m0{
+ status = "okay";
+};
+
+&mu2_m0{
+ status = "okay";
+};
+
+&rtc {
+ status = "disabled";
+};
+
+&sai6 {
+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai6_lpcg 0>;
+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
+ assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
+ fsl,sai-asynchronous;
+ status = "okay";
+};
+
+&sai7 {
+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai7_lpcg 0>;
+ assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
+ assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
+ fsl,sai-asynchronous;
+ status = "okay";
+};
+
+&thermal_zones {
+ pmic-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
+ trips {
+ pmic_alert0: trip0 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pmic_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&pmic_alert0>;
+ cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+/* WIFI */
+&usdhc3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi>;
+ bus-width = <4>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_esai0: esai0grp {
+ fsl,pins = <
+ IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040
+ IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040
+ IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040
+ IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040
+ IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040
+ IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040
+ IMX8QM_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK 0xc600004c
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000048
+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
+ IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x06000028
+ IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x06000048
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041
+ IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041
+ IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041
+ IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000041
+ IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 0x00000041
+ >;
+ };
+
+ pinctrl_i2c0: i2c0grp {
+ fsl,pins = <
+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc6000020
+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc6000020
+ >;
+ };
+
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020
+ IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020
+ IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B 0x06000020
+ IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
+ IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
+ fsl,pins = <
+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
+ IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
+ IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
+ IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
+ IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
+ IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0xc600004c
+ IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x06000021
+ IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021
+ IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
+ >;
+ };
+};
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v7 6/7] KVM: arm64: Ensure FFA ranges are page aligned
From: Sebastian Ene @ 2026-06-30 9:51 UTC (permalink / raw)
To: Vincent Donnefort
Cc: catalin.marinas, oupton, sudeep.holla, will, jens.wiklander,
joey.gouly, kvmarm, linux-arm-kernel, linux-kernel, android-kvm,
maz, mrigendra.chaubey, op-tee, perlarsen, seiden, smostafa,
sumit.garg, suzuki.poulose, yuzenghui
In-Reply-To: <ajQmN-UQD3uJJddJ@google.com>
On Thu, Jun 18, 2026 at 06:09:11PM +0100, Vincent Donnefort wrote:
> On Wed, Jun 17, 2026 at 02:51:29PM +0000, Sebastian Ene wrote:
> > From: Mostafa Saleh <smostafa@google.com>
> >
> > At the moment we only check that the size of the range is page
> > aligned, and truncate the address to the page boundary.
> > This make an assumption that TZ will do the same.
> >
> > However, it might decide to use the extra offset of the neighbour
> > page at the end, which is valid under FFA if NS is using larger
> > page size.
>
Hey Vincent,
> I failed to parse this
>
> But I see
>
> /* The base IPA of the constituent memory region, aligned to 4 kiB */
>
> So it sounds fair to prevent oversharing when PAGE_SIZE > 4KiB
>
I think the problem is when you have a mismatch between FFA_PAGE_SIZE
and the system PAGE_SIZE. We expect a fixed FFA_PAGE_SIZE of 4kb and
this is enforced by :
https://elixir.bootlin.com/linux/v7.1.2/source/arch/arm64/kvm/hyp/nvhe/ffa.c#L761
if FFA_PAGE_SIZE = 4kb and PAGE_SIZE = 16kb you can end up annotating more pages with FF-A then
needed when the range->address is unaligned.
It took me a while to understand this so I guess it is better to rephrase the commit msg.
> >
> > Harden this check by also checking that the base address is aligned
> > and reject it otherwise.
> >
> > Fixes: 436090001776 ("KVM: arm64: Handle FFA_MEM_SHARE calls from the host")
> > Signed-off-by: Mostafa Saleh <smostafa@google.com>
> > Signed-off-by: Sebastian Ene <sebastianene@google.com>
>
> Perhaps the commit description needs some improvement.
>
> The rest looks good.
>
> Reviewed-by: Vincent Donnefort <vdonnefort@google.com>
>
> > ---
> > arch/arm64/kvm/hyp/nvhe/ffa.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/hyp/nvhe/ffa.c b/arch/arm64/kvm/hyp/nvhe/ffa.c
> > index 1a2abd0154c6..d7c5701d0584 100644
> > --- a/arch/arm64/kvm/hyp/nvhe/ffa.c
> > +++ b/arch/arm64/kvm/hyp/nvhe/ffa.c
> > @@ -352,7 +352,7 @@ static u32 __ffa_host_share_ranges(struct ffa_mem_region_addr_range *ranges,
> > u64 sz = (u64)range->pg_cnt * FFA_PAGE_SIZE;
> > u64 pfn = hyp_phys_to_pfn(range->address);
> >
> > - if (!PAGE_ALIGNED(sz))
> > + if (!PAGE_ALIGNED(sz | range->address))
> > break;
> >
> > if (__pkvm_host_share_ffa(pfn, sz / PAGE_SIZE))
> > @@ -372,7 +372,7 @@ static u32 __ffa_host_unshare_ranges(struct ffa_mem_region_addr_range *ranges,
> > u64 sz = (u64)range->pg_cnt * FFA_PAGE_SIZE;
> > u64 pfn = hyp_phys_to_pfn(range->address);
> >
> > - if (!PAGE_ALIGNED(sz))
> > + if (!PAGE_ALIGNED(sz | range->address))
> > break;
> >
> > if (__pkvm_host_unshare_ffa(pfn, sz / PAGE_SIZE))
> > --
> > 2.54.0.1136.gdb2ca164c4-goog
> >
Thanks,
Sebastian
^ permalink raw reply
* Re: [PATCH v15 1/9] drm/bridge: Implement generic USB Type-C DP HPD bridge
From: Heikki Krogerus @ 2026-06-30 9:54 UTC (permalink / raw)
To: Chaoyi Chen
Cc: Xu Yang, Chaoyi Chen, Greg Kroah-Hartman, Dmitry Baryshkov,
Peter Chen, Luca Ceresoli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner,
Sandy Huang, Andy Yan, Yubing Zhang, Frank Wang, Andrzej Hajda,
Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Amit Sunil Dhamne,
Dragan Simic, Johan Jonker, Diederik de Haas, Peter Robinson,
Hugh Cole-Baker, linux-usb, devicetree, linux-kernel, linux-phy,
linux-arm-kernel, linux-rockchip, dri-devel
In-Reply-To: <b2633b22-da30-4778-8e23-7b5bed9ead07@rock-chips.com>
> @Heikki, what do you think of the following change?
> Should we add a new patch for this? Thanks.
>
> diff --git a/drivers/usb/typec/altmodes/Kconfig b/drivers/usb/typec/altmodes/Kconfig
> index 7867fa7c405d..f89cdf3c949b 100644
> --- a/drivers/usb/typec/altmodes/Kconfig
> +++ b/drivers/usb/typec/altmodes/Kconfig
> @@ -5,6 +5,7 @@ menu "USB Type-C Alternate Mode drivers"
> config TYPEC_DP_ALTMODE
> tristate "DisplayPort Alternate Mode driver"
> depends on DRM
> + select DRM_AUX_HPD_BRIDGE
> help
> DisplayPort USB Type-C Alternate Mode allows DisplayPort
> displays and adapters to be attached to the USB Type-C
This look good to me. Please do add the patch for this.
thanks,
--
heikki
^ permalink raw reply
* Re: [PATCH v2 2/2] arm64: dts: qcom: kaanapali: fix traceNoC probe issue
From: Leo Yan @ 2026-06-30 10:01 UTC (permalink / raw)
To: Jie Gan
Cc: Suzuki K Poulose, Mike Leach, James Clark, Konrad Dybcio,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jingyi Wang, Abel Vesa,
Yuanfang Zhang, linux-arm-msm, devicetree, linux-kernel,
coresight, linux-arm-kernel
In-Reply-To: <37017aa2-e18c-4568-a37c-d13964cbb418@oss.qualcomm.com>
On Tue, Jun 30, 2026 at 04:42:39PM +0800, Jie Gan wrote:
[...]
> As Suzuki mentioned in the other thread, I think it would be better to add
> separate compatibles in the of_match_table to distinguish between Aggregator
> TraceNoC and Interconnect TraceNoC when probing with the platform driver.
> This would allow us to allocate an ATID only for Aggregator TraceNoC during
> probe, which is consistent with our original design.
Makes sense for me!
^ permalink raw reply
* Re: [PATCH RFC v7 0/9] firmware: arm_scmi: vendors: Qualcomm Generic Vendor Extensions
From: Pragnesh Papaniya @ 2026-06-30 10:02 UTC (permalink / raw)
To: Sudeep Holla
Cc: Cristian Marussi, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sibi Sankar, MyungJoo Ham, Kyungmin Park, Chanwoo Choi,
Dmitry Osipenko, Thierry Reding, Jonathan Hunter, Bjorn Andersson,
Konrad Dybcio, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra, Amir Vajid, Ramakrishna Gottimukkula
In-Reply-To: <20260625-metal-chachalaca-of-fascination-eabc0f@sudeepholla>
On 27-Jun-26 7:43 PM, Sudeep Holla wrote:
> On Thu, Jun 25, 2026 at 10:57:40AM +0530, Pragnesh Papaniya wrote:
>>
>>
>> On 23-Jun-26 2:17 PM, Sudeep Holla wrote:
>>> On Fri, Jun 19, 2026 at 06:01:23PM +0530, Pragnesh Papaniya wrote:
>>>>
>>>> On 16-Jun-26 1:57 PM, Sudeep Holla wrote:
>>>>
>>>>> Not sure if it was discussed in the previous versions or not, it would be
>>>>> good if you can capture why some of bus scaling doesn't work with the existing
>>>>> SCMI performance protocol and the monitors don't fit the MPAM mode.
>>>>>
>>>>> Please capture them in 1/9 as a motivation for this vendor protocol. It will
>>>>> then help to understand it better as I am still struggling to. Sorry for that.
>>>>
>>>> Thanks for the input!
>>>>
>>>> SCMI perf protocol exports perf domains to kernel where kernel can set
>>>> the frequency but here the scaling governor runs on the SCP while kernel
>>>> just observes frequency changes made by remote governor.
>>>
>>> OK if it is sort of read-only w.r.t kernel, why not perf domain notifications
>>> work to consume the change done by the SCMI platform.
>>>
>>> And why do you have set operations in the vendor protocol being proposed then.
>>> It all looks like something just cooked up to make things work. I need
>>> detailed reasoning as why the existing perf protocol can't work considering
>>> all the existing notifications in place.
>>
>> Please do take another look at the documentation and driver changes to see
>> how it all comes together, since it's apparent that we use SET operation for
>> a ton of things. Taking another stab at explaining how the MEMLAT uses all
>> the ops exposed by the vendor protocol.
>>
>
> Sure I will have a look at the documentation again and sorry if I missed
> anything. But in general I would expect the document to be self-explanatory
> and not having to look at the driver on how it is used to understand the
> firmware interface. Please make sure of that if not already.
>
>> We use the SET operation to pass on various tuneables (IPM CEIL, stall floors,
>> write-back filter, freq-scale params, adaptive low/high freq, sample ms),
>> the core-freq -> mem-freq map, and min/max clamps) required to run the
>> MEMLAT algorithm on the SCP. You might ask why can't we have these values
>> stored somewhere on the SCP itself?
>
> Exactly, thanks for saving a round trip.
>
>> We would like to but all of these are tuneable values, that can change for
>> various boards for the same SoC.
>>
>
> Sure and where do these boards get these values from ? I assume device tree ?
> If so, are the fixed and can be done once at boot ?
There are no memlat tunables in DT (We tried to have in device tree in the earlier
revisions but they introduced unnecessary complexity). They are in kernel structs (see 7/9),
fixed per SoC/board variant and pushed to the SCP exactly once at probe. The driver
walks the selected config, sends the event maps, freq maps, tuneables and min/max
clamps via SET, and then issues START. Any further SET traffic is limited to a sub-set
of tuneables like changing sample_ms, limiting max_freq that the devfreq framework
supports.
>
>> The START/STOP operations are meant to start/stop the algorithm, in this case
>> the bus scaling algorithm.
>>
>
> Yes you need to add more details on that algorithm. Can firmware take random
> strings as input. I guess not. Please list the valid strings and explain them.
> Filter invalid strings in the driver if only handful of values are valid.
Thanks, will add a filter that just accepts valid strings in the next re-spin.
>
>> We use the GET operation to get the current frequency of memory that we
>> are trying to scale. It can be also used to read back all the parameters
>> that we are trying to set. Another thing to note is that exposing the current
>> frequency to the userspace was something that the community wanted.
>>
>
> More fun, user ABI involved, so the firmware interface needs to be as clear
> as possible.
>
>> With all of ^^ in mind, re-using the perf protocol becomes impossible.
>>
>> https://lore.kernel.org/lkml/k4lpzxtrq3x6riyv6etxiobn7nbpczf2bp3m4oc752nhjknlit@uo53kbppzim7/
>> https://lore.kernel.org/lkml/20241115003809epcms1p518df149458f3023d33ec6d87a315e8f6@epcms1p5/
>>
>
> It is good to capture summary of these old discussions if they are relevant.
Ack
Thanks,
Pragnesh
>
>> We'll add more call flow diagrams as part of the documentation for the next
>> re-spin to make reviews a bit more easier.
>>
>
> Anything that improves and helps in understanding this is always welcome.
>
^ permalink raw reply
* Re: [PATCH v4 0/4] arm64: cross-CPU NMI via SDEI
From: Kiryl Shutsemau @ 2026-06-30 10:04 UTC (permalink / raw)
To: Catalin Marinas
Cc: Will Deacon, James Morse, Mark Rutland, Marc Zyngier,
Doug Anderson, Petr Mladek, Thomas Gleixner, Andrew Morton,
Baoquan He, Puranjay Mohan, Usama Arif, Breno Leitao,
Julien Thierry, Lecopzer Chen, Sumit Garg, kernel-team, kexec,
linux-arm-kernel, linux-kernel
In-Reply-To: <akKiV3CAKWLwHnsW@thinkstation>
On Mon, Jun 29, 2026 at 05:53:57PM +0100, Kiryl Shutsemau wrote:
> On Mon, Jun 29, 2026 at 04:54:18PM +0100, Catalin Marinas wrote:
> > Have you tried SDEI_EVENT_COMPLETE_AND_RESUME instead? Just COMPLETE
> > won't return to the kernel. We have sdei_handler_abort() to complete the
> > event and, hopefully, you can continue with the CPU_OFF. It's a work
> > around the TF-A non-compliance but I think this is useful even if you
> > don't issue the CPU_OFF (e.g. no CPU hotplug, just the park loop).
>
> Tried it. The result is the opposite of what I expected, and it argues
> against doing the complete at all under QEMU's TF-A.
I have to walk back on this. My test setup was broken. I will be back to
you with proper data.
--
Kiryl Shutsemau / Kirill A. Shutemov
^ permalink raw reply
* [PATCH v5 0/5] phy: fsl-imx8mq-usb: few improvements
From: Xu Yang @ 2026-06-30 10:11 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Jun Li
Cc: linux-phy, imx, linux-arm-kernel, linux-kernel, Felix Gu, stable,
Xu Yang
This patchset is a continuous of v2, it mainly resolves some concerns
reported by sashiko-bot.
Patch #1 fix Type-C switch resource leak if probe() fails.
Patch #3 add runtime PM support to avoid register access issue if the
USB controller enters into runtime suspended state, in this state
accessing USB PHY register may lack some resources. This will also
avoid regulator leak if power_on() fails.
Patch #4 add debug control register regmap
Patch #5 correct i.MX8MP USB runtime wakeup issue after introduce runtime
PM support.
---
Changes in v5:
- not use devm runtime callback to avoid clk enable/disable imblance
- Link to v4: https://patch.msgid.link/20260605-imx8mp-usb-phy-improvement-v4-0-b2ddf2f3862c@nxp.com
Changes in v4:
- add Rb tag
- replace guard() with PM_RUNTIME_ACQUIRE()
- Link to v3: https://patch.msgid.link/20260603-imx8mp-usb-phy-improvement-v3-0-7afb8f89abc6@nxp.com
Link to v2:
- https://lore.kernel.org/linux-phy/20260512101046.1498096-1-xu.yang_2@nxp.com/
- https://lore.kernel.org/linux-phy/20260512101212.1498223-1-xu.yang_2@nxp.com/
---
Felix Gu (1):
phy: fsl-imx8mq-usb: fix typec switch leak on probe error path
Xu Yang (4):
phy: fsl-imx8mq-usb: set usb phy to be wakeup capable
phy: fsl-imx8mq-usb: add runtime PM support
phy: fsl-imx8mq-usb: add control register regmap
phy: fsl-imx8mq-usb: keep PHY power domain runtime always-on for i.MX8MP
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 131 +++++++++++++++++++++--------
1 file changed, 96 insertions(+), 35 deletions(-)
---
base-commit: 7de6ae9e12207ec146f2f3f1e58d1a99317e88bc
change-id: 20260602-imx8mp-usb-phy-improvement-4272d308d862
Best regards,
--
Xu Yang <xu.yang_2@nxp.com>
^ permalink raw reply
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