[PATCH 0/6] msm8996: db820c: Fix mmc/ufs and get 5.4 to userspace

[PATCH 0/6] msm8996: db820c: Fix mmc/ufs and get 5.4 to userspace

[Paolo Pisati]

With 5.4 + arm64 defconfig, db820c fails to boot to userspace: crashes
right before mounting rootfs, and resets back to LK (Bjorn pushed a
series of dts changes to support the IFC6640[1] out of msm8996, and i
thought 5.4 was in a good state for this SoC).

To get a basic set of features working (mmc, ufs, eth, usb, etc), i had
to cherry-pick a couple of patches and config changes from Linaro
4.14[2], and revert an upstream qmp patch:

1) these two cherry-picks from Linaro 4.14 fix the broken mmc[3].

clk: qcom: Drop gcc_aggre1_pnoc_ahb_clk clock
arm64: dts: qcom: msm8996: Disable USB2 PHY suspend by core

2) without these =y config changes, UFS refuses to init[4].

arm64: defconfig: PHY_QCOM_QMP=y
arm64: defconfig: PHY_QCOM_QUSB2=y
arm64: defconfig: PHY_QCOM_UFS=y

3) without this upstream revert, pci, ethernet and are wifi dead[5].

Revert "phy: qcom-qmp: Correct ready status, again"

4) with all the above patches applied, msm_drm still complain about
clks, but at least the board is up, running and reachable[6].

Any thoughts from the author of these patches or the ml?
In particular, the =y config changes are bothering me because we
are clearly pushing problems under the rug.

1: https://lkml.org/lkml/2019/10/21/15
2: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git/log/?h=release/qcomlt-4.14
3: https://pastebin.com/DDHvZD6Q
4: https://pastebin.com/hmPVqNqs
5: https://pastebin.com/fMqtH8u5
6: https://pastebin.com/irGv9Qmb

Amit Pundir (1):
  clk: qcom: Drop gcc_aggre1_pnoc_ahb_clk clock

Manu Gautam (1):
  arm64: dts: qcom: msm8996: Disable USB2 PHY suspend by core

Paolo Pisati (4):
  Revert "phy: qcom-qmp: Correct ready status, again"
  arm64: defconfig: PHY_QCOM_QMP=y
  arm64: defconfig: PHY_QCOM_QUSB2=y
  arm64: defconfig: PHY_QCOM_UFS=y

 arch/arm64/boot/dts/qcom/msm8996.dtsi |  4 ++++
 arch/arm64/configs/defconfig          |  5 +++--
 drivers/clk/qcom/gcc-msm8996.c        | 15 ---------------
 drivers/phy/qualcomm/phy-qcom-qmp.c   | 33 +++++++++++++++++----------------
 4 files changed, 24 insertions(+), 33 deletions(-)

-- 
2.7.4

[PATCH 1/6] clk: qcom: Drop gcc_aggre1_pnoc_ahb_clk clock

[Paolo Pisati]

From: Amit Pundir <amit.pundir@linaro.org>

Clock "gcc_aggre1_pnoc_ahb_clk" added in QcomLT commit 9a108d744fda
("clk: qcom: Add some missing gcc clks for msm8996"), broke USB
gagdets for db820c. So drop it for now and re-visit the dropped
changes while submitting it upstream.

Fixes: 9a108d744fda ("clk: qcom: Add some missing gcc clks for msm8996")
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
---
 drivers/clk/qcom/gcc-msm8996.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index d004cda..c1e1148 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -2937,20 +2937,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
 	},
 };
 
-static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
-	.halt_reg = 0x82014,
-	.clkr = {
-		.enable_reg = 0x82014,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "gcc_aggre1_pnoc_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
-			.num_parents = 1,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
 	.halt_reg = 0x83014,
 	.clkr = {
@@ -3453,7 +3439,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
 	[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
 	[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
 	[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
-	[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
 	[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
 	[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
 	[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
-- 
2.7.4

[PATCH v2] arm64: dts: qcom: msm8996: Disable USB2 PHY suspend by core

[Paolo Pisati]

From: Manu Gautam <mgautam@codeaurora.org>

QUSB2 PHY on msm8996 doesn't work well when autosuspend by
dwc3 core using USB2PHYCFG register is enabled. One of the
issue seen is that PHY driver reports PLL lock failure and
fails phy_init() if dwc3 core has USB2 PHY suspend enabled.
Fix this by using quirks to disable USB2 PHY LPM/suspend and
dwc3 core already takes care of explicitly suspending PHY
during suspend if quirks are specified.

Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 87f4d9c..fbb8ce7 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1598,6 +1598,8 @@
 				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&hsusb_phy2>;
 				phy-names = "usb2-phy";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
 			};
 		};
 
@@ -1628,6 +1630,8 @@
 				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
 			};
 		};
 
-- 
2.7.4

[PATCH v2] clk: qcom: Drop gcc_aggre1_pnoc_ahb_clk clock

[Paolo Pisati]

From: Amit Pundir <amit.pundir@linaro.org>

Clock "gcc_aggre1_pnoc_ahb_clk" added in QcomLT commit 9a108d744fda
("clk: qcom: Add some missing gcc clks for msm8996"), broke USB
gagdets for db820c. So drop it for now and re-visit the dropped
changes while submitting it upstream.

Fixes: 9a108d744fda ("clk: qcom: Add some missing gcc clks for msm8996")
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
---
 drivers/clk/qcom/gcc-msm8996.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index d004cda..c1e1148 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -2937,20 +2937,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
 	},
 };
 
-static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
-	.halt_reg = 0x82014,
-	.clkr = {
-		.enable_reg = 0x82014,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "gcc_aggre1_pnoc_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
-			.num_parents = 1,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
 	.halt_reg = 0x83014,
 	.clkr = {
@@ -3453,7 +3439,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
 	[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
 	[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
 	[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
-	[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
 	[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
 	[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
 	[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
-- 
2.7.4

Re: [PATCH 1/6] clk: qcom: Drop gcc_aggre1_pnoc_ahb_clk clock

[Amit Pundir]

This patch of mine was more of a stopgap fix. Adding Rajendra, who
authored "clk: qcom: Add some missing gcc clks for msm8996", for
review.

On Thu, 5 Dec 2019 at 21:45, Paolo Pisati <p.pisati@gmail.com> wrote:
>
> From: Amit Pundir <amit.pundir@linaro.org>
>
> Clock "gcc_aggre1_pnoc_ahb_clk" added in QcomLT commit 9a108d744fda
> ("clk: qcom: Add some missing gcc clks for msm8996"), broke USB
> gagdets for db820c. So drop it for now and re-visit the dropped
> changes while submitting it upstream.
>
> Fixes: 9a108d744fda ("clk: qcom: Add some missing gcc clks for msm8996")

Also this ^^ is not upstream commit. Upstream commit is:
b567752144e3 ("clk: qcom: Add some missing gcc clks for msm8996")

Regards,
Amit Pundir

> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
> ---
>  drivers/clk/qcom/gcc-msm8996.c | 15 ---------------
>  1 file changed, 15 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> index d004cda..c1e1148 100644
> --- a/drivers/clk/qcom/gcc-msm8996.c
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -2937,20 +2937,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
>         },
>  };
>
> -static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
> -       .halt_reg = 0x82014,
> -       .clkr = {
> -               .enable_reg = 0x82014,
> -               .enable_mask = BIT(0),
> -               .hw.init = &(struct clk_init_data){
> -                       .name = "gcc_aggre1_pnoc_ahb_clk",
> -                       .parent_names = (const char *[]){ "periph_noc_clk_src" },
> -                       .num_parents = 1,
> -                       .ops = &clk_branch2_ops,
> -               },
> -       },
> -};
> -
>  static struct clk_branch gcc_aggre2_ufs_axi_clk = {
>         .halt_reg = 0x83014,
>         .clkr = {
> @@ -3453,7 +3439,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
>         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
>         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
>         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
> -       [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
>         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
>         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
>         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
> --
> 2.7.4
>

[PATCH 2/6] arm64: dts: qcom: msm8996: Disable USB2 PHY suspend by core

[Paolo Pisati]

From: Manu Gautam <mgautam@codeaurora.org>

QUSB2 PHY on msm8996 doesn't work well when autosuspend by
dwc3 core using USB2PHYCFG register is enabled. One of the
issue seen is that PHY driver reports PLL lock failure and
fails phy_init() if dwc3 core has USB2 PHY suspend enabled.
Fix this by using quirks to disable USB2 PHY LPM/suspend and
dwc3 core already takes care of explicitly suspending PHY
during suspend if quirks are specified.

Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 87f4d9c..fbb8ce7 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1598,6 +1598,8 @@
 				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&hsusb_phy2>;
 				phy-names = "usb2-phy";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
 			};
 		};
 
@@ -1628,6 +1630,8 @@
 				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
 			};
 		};
 
-- 
2.7.4

Re: [PATCH 2/6] arm64: dts: qcom: msm8996: Disable USB2 PHY suspend by core

[Bjorn Andersson]

On Thu 05 Dec 08:15 PST 2019, Paolo Pisati wrote:

> From: Manu Gautam <mgautam@codeaurora.org>
> 
> QUSB2 PHY on msm8996 doesn't work well when autosuspend by
> dwc3 core using USB2PHYCFG register is enabled. One of the
> issue seen is that PHY driver reports PLL lock failure and
> fails phy_init() if dwc3 core has USB2 PHY suspend enabled.
> Fix this by using quirks to disable USB2 PHY LPM/suspend and
> dwc3 core already takes care of explicitly suspending PHY
> during suspend if quirks are specified.
> 
> Signed-off-by: Manu Gautam <mgautam@codeaurora.org>

I haven't yet had the chance to test this, but please add your
Signed-off-by below Manu's and resubmit this patch.

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 87f4d9c..fbb8ce7 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -1598,6 +1598,8 @@
>  				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
>  				phys = <&hsusb_phy2>;
>  				phy-names = "usb2-phy";
> +				snps,dis_u2_susphy_quirk;
> +				snps,dis_enblslpm_quirk;
>  			};
>  		};
>  
> @@ -1628,6 +1630,8 @@
>  				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
>  				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
>  				phy-names = "usb2-phy", "usb3-phy";
> +				snps,dis_u2_susphy_quirk;
> +				snps,dis_enblslpm_quirk;
>  			};
>  		};
>  
> -- 
> 2.7.4
> 

[PATCH v2] arm64: dts: qcom: msm8996: Disable USB2 PHY suspend by core

[Paolo Pisati]

From: Manu Gautam <mgautam@codeaurora.org>

QUSB2 PHY on msm8996 doesn't work well when autosuspend by
dwc3 core using USB2PHYCFG register is enabled. One of the
issue seen is that PHY driver reports PLL lock failure and
fails phy_init() if dwc3 core has USB2 PHY suspend enabled.
Fix this by using quirks to disable USB2 PHY LPM/suspend and
dwc3 core already takes care of explicitly suspending PHY
during suspend if quirks are specified.

Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 87f4d9c..fbb8ce7 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1598,6 +1598,8 @@
 				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&hsusb_phy2>;
 				phy-names = "usb2-phy";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
 			};
 		};
 
@@ -1628,6 +1630,8 @@
 				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
 			};
 		};
 
-- 
2.7.4

[PATCH 4/6] arm64: defconfig: PHY_QCOM_QMP=y

[Paolo Pisati]

Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
---
 arch/arm64/configs/defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9a867a..8f713091 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -787,7 +787,7 @@ CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_HISTB_COMBPHY=y
 CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_MVEBU_CP110_COMPHY=y
-CONFIG_PHY_QCOM_QMP=m
+CONFIG_PHY_QCOM_QMP=y
 CONFIG_PHY_QCOM_QUSB2=m
 CONFIG_PHY_QCOM_USB_HS=y
 CONFIG_PHY_RCAR_GEN3_PCIE=y
-- 
2.7.4

[PATCH 5/6] arm64: defconfig: PHY_QCOM_QUSB2=y

[Paolo Pisati]

Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
---
 arch/arm64/configs/defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 8f713091..560cb54 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -788,7 +788,7 @@ CONFIG_PHY_HISTB_COMBPHY=y
 CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_MVEBU_CP110_COMPHY=y
 CONFIG_PHY_QCOM_QMP=y
-CONFIG_PHY_QCOM_QUSB2=m
+CONFIG_PHY_QCOM_QUSB2=y
 CONFIG_PHY_QCOM_USB_HS=y
 CONFIG_PHY_RCAR_GEN3_PCIE=y
 CONFIG_PHY_RCAR_GEN3_USB2=y
-- 
2.7.4

[PATCH 6/6] arm64: defconfig: PHY_QCOM_UFS=y

[Paolo Pisati]

Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 560cb54..2c91d75 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -859,3 +859,4 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_FTRACE is not set
 CONFIG_MEMTEST=y
+CONFIG_PHY_QCOM_UFS=y
-- 
2.7.4

[PATCH 3/6] Revert "phy: qcom-qmp: Correct ready status, again"

[Paolo Pisati]

This reverts commit 14ced7e3a1ae9bed7051df3718c8c7b583854a5c.

Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 39e8deb..e7b8283 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -35,7 +35,7 @@
 #define PLL_READY_GATE_EN			BIT(3)
 /* QPHY_PCS_STATUS bit */
 #define PHYSTATUS				BIT(6)
-/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
+/* QPHY_COM_PCS_READY_STATUS bit */
 #define PCS_READY				BIT(0)
 
 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
@@ -115,7 +115,6 @@ enum qphy_reg_layout {
 	QPHY_SW_RESET,
 	QPHY_START_CTRL,
 	QPHY_PCS_READY_STATUS,
-	QPHY_PCS_STATUS,
 	QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 	QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
@@ -134,7 +133,7 @@ static const unsigned int pciephy_regs_layout[] = {
 	[QPHY_FLL_MAN_CODE]		= 0xd4,
 	[QPHY_SW_RESET]			= 0x00,
 	[QPHY_START_CTRL]		= 0x08,
-	[QPHY_PCS_STATUS]		= 0x174,
+	[QPHY_PCS_READY_STATUS]		= 0x174,
 };
 
 static const unsigned int usb3phy_regs_layout[] = {
@@ -145,7 +144,7 @@ static const unsigned int usb3phy_regs_layout[] = {
 	[QPHY_FLL_MAN_CODE]		= 0xd0,
 	[QPHY_SW_RESET]			= 0x00,
 	[QPHY_START_CTRL]		= 0x08,
-	[QPHY_PCS_STATUS]		= 0x17c,
+	[QPHY_PCS_READY_STATUS]		= 0x17c,
 	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0x0d4,
 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
@@ -154,7 +153,7 @@ static const unsigned int usb3phy_regs_layout[] = {
 static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
 	[QPHY_SW_RESET]			= 0x00,
 	[QPHY_START_CTRL]		= 0x08,
-	[QPHY_PCS_STATUS]		= 0x174,
+	[QPHY_PCS_READY_STATUS]		= 0x174,
 	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0x0d8,
 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
@@ -912,6 +911,7 @@ struct qmp_phy_cfg {
 
 	unsigned int start_ctrl;
 	unsigned int pwrdn_ctrl;
+	unsigned int mask_pcs_ready;
 	unsigned int mask_com_pcs_ready;
 
 	/* true, if PHY has a separate PHY_COM control block */
@@ -1074,6 +1074,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
 
 	.start_ctrl		= PCS_START | PLL_READY_GATE_EN,
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
+	.mask_pcs_ready		= PHYSTATUS,
 	.mask_com_pcs_ready	= PCS_READY,
 
 	.has_phy_com_ctrl	= true,
@@ -1105,6 +1106,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
 
 	.start_ctrl		= SERDES_START | PCS_START,
 	.pwrdn_ctrl		= SW_PWRDN,
+	.mask_pcs_ready		= PHYSTATUS,
 };
 
 /* list of resets */
@@ -1134,6 +1136,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
 
 	.start_ctrl		= SERDES_START | PCS_START,
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
+	.mask_pcs_ready		= PHYSTATUS,
 
 	.has_phy_com_ctrl	= false,
 	.has_lane_rst		= false,
@@ -1164,6 +1167,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
 
 	.start_ctrl		= SERDES_START | PCS_START,
 	.pwrdn_ctrl		= SW_PWRDN,
+	.mask_pcs_ready		= PHYSTATUS,
 
 	.has_pwrdn_delay	= true,
 	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
@@ -1195,6 +1199,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
 
 	.start_ctrl		= SERDES_START | PCS_START,
 	.pwrdn_ctrl		= SW_PWRDN,
+	.mask_pcs_ready		= PHYSTATUS,
 
 	.has_pwrdn_delay	= true,
 	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
@@ -1221,6 +1226,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
 
 	.start_ctrl		= SERDES_START,
 	.pwrdn_ctrl		= SW_PWRDN,
+	.mask_pcs_ready		= PCS_READY,
 
 	.is_dual_lane_phy	= true,
 	.no_pcs_sw_reset	= true,
@@ -1248,6 +1254,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
 
 	.start_ctrl             = SERDES_START | PCS_START,
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
+	.mask_pcs_ready		= PHYSTATUS,
 };
 
 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
@@ -1272,6 +1279,7 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
 
 	.start_ctrl             = SERDES_START | PCS_START,
 	.pwrdn_ctrl             = SW_PWRDN,
+	.mask_pcs_ready         = PHYSTATUS,
 
 	.is_dual_lane_phy       = true,
 };
@@ -1449,7 +1457,7 @@ static int qcom_qmp_phy_enable(struct phy *phy)
 	void __iomem *pcs = qphy->pcs;
 	void __iomem *dp_com = qmp->dp_com;
 	void __iomem *status;
-	unsigned int mask, val, ready;
+	unsigned int mask, val;
 	int ret;
 
 	dev_vdbg(qmp->dev, "Initializing QMP phy\n");
@@ -1537,17 +1545,10 @@ static int qcom_qmp_phy_enable(struct phy *phy)
 	/* start SerDes and Phy-Coding-Sublayer */
 	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
 
-	if (cfg->type == PHY_TYPE_UFS) {
-		status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-		mask = PCS_READY;
-		ready = PCS_READY;
-	} else {
-		status = pcs + cfg->regs[QPHY_PCS_STATUS];
-		mask = PHYSTATUS;
-		ready = 0;
-	}
+	status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
+	mask = cfg->mask_pcs_ready;
 
-	ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
+	ret = readl_poll_timeout(status, val, val & mask, 10,
 				 PHY_INIT_COMPLETE_TIMEOUT);
 	if (ret) {
 		dev_err(qmp->dev, "phy initialization timed-out\n");
-- 
2.7.4

Re: [PATCH 3/6] Revert "phy: qcom-qmp: Correct ready status, again"

[Bjorn Andersson]

On Thu 05 Dec 08:15 PST 2019, Paolo Pisati wrote:

> This reverts commit 14ced7e3a1ae9bed7051df3718c8c7b583854a5c.
> 
> Signed-off-by: Paolo Pisati <p.pisati@gmail.com>

Thanks for the patch Paolo, but reverting this commit means we're
checking for the wrong status bit and thereby relies on timing of that
bit having an appropriate value again.

The problem at hand seems to be that some resources are missing while
trying to initialize the PHY, which causes it to not become ready. I saw
the same problem when bringing up PCIe on SDM845, but failed to validate
MSM8996, as this was not booting since mid-summer.

I verified that this is the case by applying:
https://lore.kernel.org/linux-arm-msm/20191107000917.1092409-4-bjorn.andersson@linaro.org/

Regards,
Bjorn

> ---
>  drivers/phy/qualcomm/phy-qcom-qmp.c | 33 +++++++++++++++++----------------
>  1 file changed, 17 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 39e8deb..e7b8283 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -35,7 +35,7 @@
>  #define PLL_READY_GATE_EN			BIT(3)
>  /* QPHY_PCS_STATUS bit */
>  #define PHYSTATUS				BIT(6)
> -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
> +/* QPHY_COM_PCS_READY_STATUS bit */
>  #define PCS_READY				BIT(0)
>  
>  /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
> @@ -115,7 +115,6 @@ enum qphy_reg_layout {
>  	QPHY_SW_RESET,
>  	QPHY_START_CTRL,
>  	QPHY_PCS_READY_STATUS,
> -	QPHY_PCS_STATUS,
>  	QPHY_PCS_AUTONOMOUS_MODE_CTRL,
>  	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
>  	QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> @@ -134,7 +133,7 @@ static const unsigned int pciephy_regs_layout[] = {
>  	[QPHY_FLL_MAN_CODE]		= 0xd4,
>  	[QPHY_SW_RESET]			= 0x00,
>  	[QPHY_START_CTRL]		= 0x08,
> -	[QPHY_PCS_STATUS]		= 0x174,
> +	[QPHY_PCS_READY_STATUS]		= 0x174,
>  };
>  
>  static const unsigned int usb3phy_regs_layout[] = {
> @@ -145,7 +144,7 @@ static const unsigned int usb3phy_regs_layout[] = {
>  	[QPHY_FLL_MAN_CODE]		= 0xd0,
>  	[QPHY_SW_RESET]			= 0x00,
>  	[QPHY_START_CTRL]		= 0x08,
> -	[QPHY_PCS_STATUS]		= 0x17c,
> +	[QPHY_PCS_READY_STATUS]		= 0x17c,
>  	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0x0d4,
>  	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
>  	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
> @@ -154,7 +153,7 @@ static const unsigned int usb3phy_regs_layout[] = {
>  static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
>  	[QPHY_SW_RESET]			= 0x00,
>  	[QPHY_START_CTRL]		= 0x08,
> -	[QPHY_PCS_STATUS]		= 0x174,
> +	[QPHY_PCS_READY_STATUS]		= 0x174,
>  	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0x0d8,
>  	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
>  	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
> @@ -912,6 +911,7 @@ struct qmp_phy_cfg {
>  
>  	unsigned int start_ctrl;
>  	unsigned int pwrdn_ctrl;
> +	unsigned int mask_pcs_ready;
>  	unsigned int mask_com_pcs_ready;
>  
>  	/* true, if PHY has a separate PHY_COM control block */
> @@ -1074,6 +1074,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
>  
>  	.start_ctrl		= PCS_START | PLL_READY_GATE_EN,
>  	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> +	.mask_pcs_ready		= PHYSTATUS,
>  	.mask_com_pcs_ready	= PCS_READY,
>  
>  	.has_phy_com_ctrl	= true,
> @@ -1105,6 +1106,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
>  
>  	.start_ctrl		= SERDES_START | PCS_START,
>  	.pwrdn_ctrl		= SW_PWRDN,
> +	.mask_pcs_ready		= PHYSTATUS,
>  };
>  
>  /* list of resets */
> @@ -1134,6 +1136,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
>  
>  	.start_ctrl		= SERDES_START | PCS_START,
>  	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> +	.mask_pcs_ready		= PHYSTATUS,
>  
>  	.has_phy_com_ctrl	= false,
>  	.has_lane_rst		= false,
> @@ -1164,6 +1167,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
>  
>  	.start_ctrl		= SERDES_START | PCS_START,
>  	.pwrdn_ctrl		= SW_PWRDN,
> +	.mask_pcs_ready		= PHYSTATUS,
>  
>  	.has_pwrdn_delay	= true,
>  	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
> @@ -1195,6 +1199,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
>  
>  	.start_ctrl		= SERDES_START | PCS_START,
>  	.pwrdn_ctrl		= SW_PWRDN,
> +	.mask_pcs_ready		= PHYSTATUS,
>  
>  	.has_pwrdn_delay	= true,
>  	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,
> @@ -1221,6 +1226,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>  
>  	.start_ctrl		= SERDES_START,
>  	.pwrdn_ctrl		= SW_PWRDN,
> +	.mask_pcs_ready		= PCS_READY,
>  
>  	.is_dual_lane_phy	= true,
>  	.no_pcs_sw_reset	= true,
> @@ -1248,6 +1254,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
>  
>  	.start_ctrl             = SERDES_START | PCS_START,
>  	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> +	.mask_pcs_ready		= PHYSTATUS,
>  };
>  
>  static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> @@ -1272,6 +1279,7 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
>  
>  	.start_ctrl             = SERDES_START | PCS_START,
>  	.pwrdn_ctrl             = SW_PWRDN,
> +	.mask_pcs_ready         = PHYSTATUS,
>  
>  	.is_dual_lane_phy       = true,
>  };
> @@ -1449,7 +1457,7 @@ static int qcom_qmp_phy_enable(struct phy *phy)
>  	void __iomem *pcs = qphy->pcs;
>  	void __iomem *dp_com = qmp->dp_com;
>  	void __iomem *status;
> -	unsigned int mask, val, ready;
> +	unsigned int mask, val;
>  	int ret;
>  
>  	dev_vdbg(qmp->dev, "Initializing QMP phy\n");
> @@ -1537,17 +1545,10 @@ static int qcom_qmp_phy_enable(struct phy *phy)
>  	/* start SerDes and Phy-Coding-Sublayer */
>  	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
>  
> -	if (cfg->type == PHY_TYPE_UFS) {
> -		status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
> -		mask = PCS_READY;
> -		ready = PCS_READY;
> -	} else {
> -		status = pcs + cfg->regs[QPHY_PCS_STATUS];
> -		mask = PHYSTATUS;
> -		ready = 0;
> -	}
> +	status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
> +	mask = cfg->mask_pcs_ready;
>  
> -	ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
> +	ret = readl_poll_timeout(status, val, val & mask, 10,
>  				 PHY_INIT_COMPLETE_TIMEOUT);
>  	if (ret) {
>  		dev_err(qmp->dev, "phy initialization timed-out\n");
> -- 
> 2.7.4
> 

Re: [PATCH 3/6] Revert "phy: qcom-qmp: Correct ready status, again"

[Paolo Pisati]

On Thu, Dec 05, 2019 at 11:07:05PM -0800, Bjorn Andersson wrote:
> On Thu 05 Dec 08:15 PST 2019, Paolo Pisati wrote:
> 
> > This reverts commit 14ced7e3a1ae9bed7051df3718c8c7b583854a5c.
> > 
> > Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
> 
> Thanks for the patch Paolo, but reverting this commit means we're
> checking for the wrong status bit and thereby relies on timing of that
> bit having an appropriate value again.
> 
> The problem at hand seems to be that some resources are missing while
> trying to initialize the PHY, which causes it to not become ready. I saw
> the same problem when bringing up PCIe on SDM845, but failed to validate
> MSM8996, as this was not booting since mid-summer.
> 
> I verified that this is the case by applying:
> https://lore.kernel.org/linux-arm-msm/20191107000917.1092409-4-bjorn.andersson@linaro.org/

Thanks Bjorn,

indeed replacing the revert and leaving the rest of the series intact, my db820c
boots fine.

One thing though - i removed the =y config changes, and now the board crash
while, it appears, powering on qmp-phy - no stacktrace, unfortunately:

...
[  OK  ] Reached target Local File Systems (Pre).
         Starting Flush Journal to Persistent Storage...
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Started udev Coldplug all Devices.
[  OK  ] Started udev Kernel Device Manager.
[   13.550757] dwc3 7600000.dwc3: Failed to get clk 'ref': -2
[   13.552251] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
[   13.580749] dwc3 7600000.dwc3: Failed to get clk 'ref': -2
[   13.582802] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
[   13.595811] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
[   13.596502] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
[   13.636319] ufshcd-qcom 624000.ufshc: ufshcd_variant_hba_init: variant qcom init failed err -517
[   13.638919] ufshcd-qcom 624000.ufshc: Initialization failed
[  OK  ] Found device /dev/ttyMSM0.
[   13.675328] ufshcd-qcom 624000.ufshc: ufshcd_pltfrm_init() failed -517
[   13.693300] qcom-qmp-phy 34000.phy: phy common block init timed-out
[   13.693390] phy phy-34000.phy.2: phy poweron failed --> -110
[   13.698831] qcom-pcie 600000.pcie: cannot initialize host

Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.0-00301
S - IMAGE_VARIANT_STRING=M8996LAB
S - OEM_IMAGE_VERSION_STRING=crm-ubuntu68
S - Boot Interface: UFS
S - Secure Boot: Off
...
- 
bye,
p.

Re: [PATCH 3/6] Revert "phy: qcom-qmp: Correct ready status, again"

[Bjorn Andersson]

On Fri 06 Dec 02:00 PST 2019, Paolo Pisati wrote:

> On Thu, Dec 05, 2019 at 11:07:05PM -0800, Bjorn Andersson wrote:
> > On Thu 05 Dec 08:15 PST 2019, Paolo Pisati wrote:
> > 
> > > This reverts commit 14ced7e3a1ae9bed7051df3718c8c7b583854a5c.
> > > 
> > > Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
> > 
> > Thanks for the patch Paolo, but reverting this commit means we're
> > checking for the wrong status bit and thereby relies on timing of that
> > bit having an appropriate value again.
> > 
> > The problem at hand seems to be that some resources are missing while
> > trying to initialize the PHY, which causes it to not become ready. I saw
> > the same problem when bringing up PCIe on SDM845, but failed to validate
> > MSM8996, as this was not booting since mid-summer.
> > 
> > I verified that this is the case by applying:
> > https://lore.kernel.org/linux-arm-msm/20191107000917.1092409-4-bjorn.andersson@linaro.org/
> 
> Thanks Bjorn,
> 
> indeed replacing the revert and leaving the rest of the series intact, my db820c
> boots fine.
> 
> One thing though - i removed the =y config changes, and now the board crash
> while, it appears, powering on qmp-phy - no stacktrace, unfortunately:
> 

Sorry, forgot to mention this part.

With this patch the PHY driver powers on nicely and I'm able to get PCIe
up and running, but only if both the host and phy drivers are builtin.

I also tried to revert the patch, as you suggest, but unless I make the
QMP driver builtin I simply get timeouts during initialization.

So we need to figure out what resource changes state between the two
cases (builtin vs module based probing).

Regards,
Bjorn

> ...
> [  OK  ] Reached target Local File Systems (Pre).
>          Starting Flush Journal to Persistent Storage...
> [  OK  ] Started Load/Save Random Seed.
> [  OK  ] Started udev Coldplug all Devices.
> [  OK  ] Started udev Kernel Device Manager.
> [   13.550757] dwc3 7600000.dwc3: Failed to get clk 'ref': -2
> [   13.552251] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
> [   13.580749] dwc3 7600000.dwc3: Failed to get clk 'ref': -2
> [   13.582802] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
> [   13.595811] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
> [   13.596502] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
> [   13.636319] ufshcd-qcom 624000.ufshc: ufshcd_variant_hba_init: variant qcom init failed err -517
> [   13.638919] ufshcd-qcom 624000.ufshc: Initialization failed
> [  OK  ] Found device /dev/ttyMSM0.
> [   13.675328] ufshcd-qcom 624000.ufshc: ufshcd_pltfrm_init() failed -517
> [   13.693300] qcom-qmp-phy 34000.phy: phy common block init timed-out
> [   13.693390] phy phy-34000.phy.2: phy poweron failed --> -110
> [   13.698831] qcom-pcie 600000.pcie: cannot initialize host
> 
> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.0-00301
> S - IMAGE_VARIANT_STRING=M8996LAB
> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu68
> S - Boot Interface: UFS
> S - Secure Boot: Off
> ...
> - 
> bye,
> p.

Re: [PATCH 3/6] Revert "phy: qcom-qmp: Correct ready status, again"

[Bjorn Andersson]

On Fri 06 Dec 02:00 PST 2019, Paolo Pisati wrote:

> On Thu, Dec 05, 2019 at 11:07:05PM -0800, Bjorn Andersson wrote:
> > On Thu 05 Dec 08:15 PST 2019, Paolo Pisati wrote:
> > 
> > > This reverts commit 14ced7e3a1ae9bed7051df3718c8c7b583854a5c.
> > > 
> > > Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
> > 
> > Thanks for the patch Paolo, but reverting this commit means we're
> > checking for the wrong status bit and thereby relies on timing of that
> > bit having an appropriate value again.
> > 
> > The problem at hand seems to be that some resources are missing while
> > trying to initialize the PHY, which causes it to not become ready. I saw
> > the same problem when bringing up PCIe on SDM845, but failed to validate
> > MSM8996, as this was not booting since mid-summer.
> > 
> > I verified that this is the case by applying:
> > https://lore.kernel.org/linux-arm-msm/20191107000917.1092409-4-bjorn.andersson@linaro.org/
> 
> Thanks Bjorn,
> 
> indeed replacing the revert and leaving the rest of the series intact, my db820c
> boots fine.
> 
> One thing though - i removed the =y config changes, and now the board crash
> while, it appears, powering on qmp-phy - no stacktrace, unfortunately:
> 

The sudden reboot is caused by UFS not being able to find it's PHY, in
which case it will disable RPM_SMD_LN_BB_CLK, which causes
GCC_PCIE_CLKREF_CLK to stop ticking, so we get an unclocked access.

Together with the patch above I get working PCIe and UFS with both =m.
I'll send out a patch that properly describes this dependency. 


I will also propose a set of patches that migrates the 8996 UFS PHY to
phy-qcom-qmp, instead of the UFS-specific QMP driver.

Regards,
Bjorn

> ...
> [  OK  ] Reached target Local File Systems (Pre).
>          Starting Flush Journal to Persistent Storage...
> [  OK  ] Started Load/Save Random Seed.
> [  OK  ] Started udev Coldplug all Devices.
> [  OK  ] Started udev Kernel Device Manager.
> [   13.550757] dwc3 7600000.dwc3: Failed to get clk 'ref': -2
> [   13.552251] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
> [   13.580749] dwc3 7600000.dwc3: Failed to get clk 'ref': -2
> [   13.582802] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
> [   13.595811] dwc3 6a00000.dwc3: Failed to get clk 'ref': -2
> [   13.596502] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
> [   13.636319] ufshcd-qcom 624000.ufshc: ufshcd_variant_hba_init: variant qcom init failed err -517
> [   13.638919] ufshcd-qcom 624000.ufshc: Initialization failed
> [  OK  ] Found device /dev/ttyMSM0.
> [   13.675328] ufshcd-qcom 624000.ufshc: ufshcd_pltfrm_init() failed -517
> [   13.693300] qcom-qmp-phy 34000.phy: phy common block init timed-out
> [   13.693390] phy phy-34000.phy.2: phy poweron failed --> -110
> [   13.698831] qcom-pcie 600000.pcie: cannot initialize host
> 
> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.0-00301
> S - IMAGE_VARIANT_STRING=M8996LAB
> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu68
> S - Boot Interface: UFS
> S - Secure Boot: Off
> ...
> - 
> bye,
> p.