[PATCH 0/2] Enable Display Port for Qualcomm QCS8300-ride platform

[PATCH 0/2] Enable Display Port for Qualcomm QCS8300-ride platform

[Yongxing Mou]

This series adds the DPTX0 node, as a part of mdss0 on Qualcomm QCS8300
SoC. It also enables Display Port on Qualcomm QCS8300-ride platform.

Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
---
Please note this patch depends on following series:
https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com/
https://lore.kernel.org/all/20241114-qcs8300-mm-cc-dt-patch-v1-1-7a974508c736@quicinc.com/
https://lore.kernel.org/all/20241127-mdss_qcs8300-v1-0-29b2c3ee95b8@quicinc.com/
https://lore.kernel.org/all/20241127-qcs8300_dp-v1-0-0d30065c8c58@quicinc.com/

---
Yongxing Mou (2):
      arm64: dts: qcom: qcs8300: add DisplayPort device nodes
      arm64: dts: qcom: qcs8300-ride: Enable Display Port

 arch/arm64/boot/dts/qcom/qcs8300-ride.dts |  44 ++++++++++++
 arch/arm64/boot/dts/qcom/qcs8300.dtsi     | 115 +++++++++++++++++++++++++++++-
 2 files changed, 158 insertions(+), 1 deletion(-)
---
base-commit: 414c97c966b69e4a6ea7b32970fa166b2f9b9ef0
change-id: 20241122-dp_dts_qcs8300-ee342df0ff37
prerequisite-message-id:20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com
prerequisite-patch-id: 73c78f31fa1d504124d4a82b578a6a14126cccd8
prerequisite-patch-id: 5a01283c8654ae7c696d9c69cb21505b71c5ca27
prerequisite-patch-id: dc633d5aaac790776a8a213ea2faa4890a3f665d
prerequisite-patch-id: 9ecf4cb8b5842ac64e51d6baa0e6c1fbe449ee66
prerequisite-message-id:20241114-qcs8300-mm-cc-dt-patch-v1-1-7a974508c736@quicinc.com
prerequisite-patch-id: 8faad5c6d8ca255935d3e4d317dcbcc32b8261ff
prerequisite-message-id:20241127-mdss_qcs8300-v1-0-29b2c3ee95b8@quicinc.com
prerequisite-patch-id: d13db448443d15d4c87329dbf8a20c2132ed3e65
prerequisite-patch-id: 93a9abef1fdabcc459688518ac5a563be0d723e9
prerequisite-patch-id: 7e65b4b4719b3955c1af0be922b86ec91a1db0e7
prerequisite-patch-id: c8be7acdd2ddc57b381de1dc886a50523af77974
prerequisite-patch-id: 646869c16608a54c66107a2e7e92af15be0fb1a2
prerequisite-message-id:20241127-qcs8300_dp-v1-0-0d30065c8c58@quicinc.com
prerequisite-patch-id: e9c4526e6b5f3f3c1eb8b4583df0ffccc6576581
prerequisite-patch-id: c016862828657b27feecccca34ad8552b42dd04d
prerequisite-patch-id: f49e5d4dc01a2e968751d294267f2a8d63360a85
prerequisite-patch-id: f24850d18c2d192673eb07efdae234dcf3e5a00c

Best regards,
-- 
Yongxing Mou <quic_yongmou@quicinc.com>

[PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Yongxing Mou]

Add device tree nodes for the DPTX0 controller with their
corresponding PHYs found on Qualcomm QCS8300 SoC.

Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++-
 1 file changed, 114 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 {
 				interrupt-parent = <&mdss>;
 				interrupts = <0>;
 
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						dpu_intf0_out: endpoint {
+							remote-endpoint = <&mdss_dp0_in>;
+						};
+					};
+				};
+
 				mdp_opp_table: opp-table {
 					compatible = "operating-points-v2";
 
@@ -1011,6 +1024,104 @@ opp-650000000 {
 					};
 				};
 			};
+
+			mdss_dp0_phy: phy@aec2a00 {
+				compatible = "qcom,qcs8300-edp-phy";
+
+				reg = <0x0 0x0aec2a00 0x0 0x200>,
+				      <0x0 0x0aec2200 0x0 0xd0>,
+				      <0x0 0x0aec2600 0x0 0xd0>,
+				      <0x0 0x0aec2000 0x0 0x1c8>;
+
+				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "aux",
+					      "cfg_ahb";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss_dp0: displayport-controller@af54000 {
+				compatible = "qcom,qcs8300-dp";
+
+				reg = <0x0 0x0af54000 0x0 0x104>,
+				      <0x0 0x0af54200 0x0 0x0c0>,
+				      <0x0 0x0af55000 0x0 0x770>,
+				      <0x0 0x0af56000 0x0 0x09c>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <12>;
+
+				clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+				clock-names = "core_iface",
+					      "core_aux",
+					      "ctrl_link",
+					      "ctrl_link_iface",
+					      "stream_pixel";
+				assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+						  <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dp0_phy 0>,
+							 <&mdss_dp0_phy 1>;
+				phys = <&mdss_dp0_phy>;
+				phy-names = "dp";
+
+				operating-points-v2 = <&dp_opp_table>;
+				power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+				#sound-dai-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss_dp0_in: endpoint {
+							remote-endpoint = <&dpu_intf0_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss_dp0_out: endpoint { };
+					};
+				};
+
+				dp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-160000000 {
+						opp-hz = /bits/ 64 <160000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
 		};
 
 		dispcc: clock-controller@af00000 {
@@ -1020,7 +1131,9 @@ dispcc: clock-controller@af00000 {
 				 <&rpmhcc RPMH_CXO_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK_A>,
 				 <&sleep_clk>,
-				 <0>, <0>, <0>, <0>,
+				 <&mdss_dp0_phy 0>,
+				 <&mdss_dp0_phy 1>,
+				 <0>, <0>,
 				 <0>, <0>, <0>, <0>;
 			power-domains = <&rpmhpd RPMHPD_MMCX>;
 			#clock-cells = <1>;

-- 
2.34.1

[PATCH 2/2] arm64: dts: qcom: qcs8300-ride: Enable Display Port

[Yongxing Mou]

Enable DPTX0 along with their corresponding PHYs for
qcs8300-ride platform.

Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 +++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 7eed19a694c39dbe791afb6a991db65acb37e597..5dc855d6a22c38d97a3071d3a3d88ec551eebd1b 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -35,6 +35,18 @@ sleep_clk: sleep-clk {
 			clock-frequency = <32000>;
 		};
 	};
+
+	dp0-connector {
+		compatible = "dp-connector";
+		label = "DP0";
+		type = "full-size";
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&mdss_dp0_out>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -223,6 +235,30 @@ &gcc {
 		 <0>;
 };
 
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+
+	pinctrl-0 = <&dp_hot_plug_det>;
+	pinctrl-names = "default";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+	remote-endpoint = <&dp0_connector_in>;
+};
+
+&mdss_dp0_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l4a>;
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -247,6 +283,14 @@ &rpmhcc {
 	clock-names = "xo";
 };
 
+&tlmm {
+	dp_hot_plug_det: dp-hot-plug-det-state {
+		pins = "gpio94";
+		function = "edp0_hot";
+		bias-disable;
+	};
+};
+
 &uart7 {
 	status = "okay";
 };

-- 
2.34.1

Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Konrad Dybcio]

On 27.11.2024 11:45 AM, Yongxing Mou wrote:
> Add device tree nodes for the DPTX0 controller with their
> corresponding PHYs found on Qualcomm QCS8300 SoC.
> 
> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++-
>  1 file changed, 114 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 {
>  				interrupt-parent = <&mdss>;
>  				interrupts = <0>;
>  
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						dpu_intf0_out: endpoint {
> +							remote-endpoint = <&mdss_dp0_in>;
> +						};
> +					};
> +				};
> +
>  				mdp_opp_table: opp-table {
>  					compatible = "operating-points-v2";
>  
> @@ -1011,6 +1024,104 @@ opp-650000000 {
>  					};
>  				};
>  			};
> +
> +			mdss_dp0_phy: phy@aec2a00 {
> +				compatible = "qcom,qcs8300-edp-phy";
> +
> +				reg = <0x0 0x0aec2a00 0x0 0x200>,

0x19c

> +				      <0x0 0x0aec2200 0x0 0xd0>,

0xec
> +				      <0x0 0x0aec2600 0x0 0xd0>,

0xec

For lengths

> +				      <0x0 0x0aec2000 0x0 0x1c8>;

This one's correct

> +
> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> +					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
> +				clock-names = "aux",
> +					      "cfg_ahb";

power-domains = <&rpmhpd RPMHPD_MX>;

(or maybe even MXC?)

> +
> +				#clock-cells = <1>;
> +				#phy-cells = <0>;
> +
> +				status = "disabled";
> +			};
> +
> +			mdss_dp0: displayport-controller@af54000 {
> +				compatible = "qcom,qcs8300-dp";
> +
> +				reg = <0x0 0x0af54000 0x0 0x104>,
0x200

> +				      <0x0 0x0af54200 0x0 0x0c0>,
0x200

> +				      <0x0 0x0af55000 0x0 0x770>,
0xc00

> +				      <0x0 0x0af56000 0x0 0x09c>;
0x400

for lengths

Konrad

Re: [PATCH 2/2] arm64: dts: qcom: qcs8300-ride: Enable Display Port

[Konrad Dybcio]

On 27.11.2024 11:45 AM, Yongxing Mou wrote:
> Enable DPTX0 along with their corresponding PHYs for
> qcs8300-ride platform.
> 
> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
> ---

[...]

> +
> +	dp0-connector {
> +		compatible = "dp-connector";
> +		label = "DP0";
> +		type = "full-size";

I was surprised to see it but yeah this is real

> +
> +		port {
> +			dp0_connector_in: endpoint {
> +				remote-endpoint = <&mdss_dp0_out>;
> +			};
> +		};
> +	};
>  };
>  
>  &apps_rsc {
> @@ -223,6 +235,30 @@ &gcc {
>  		 <0>;
>  };
>  
> +&mdss {
> +	status = "okay";
> +};
> +
> +&mdss_dp0 {
> +	status = "okay";
status should be the last property

> +
> +	pinctrl-0 = <&dp_hot_plug_det>;
> +	pinctrl-names = "default";
> +};
> +
> +&mdss_dp0_out {
> +	data-lanes = <0 1 2 3>;
> +	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
> +	remote-endpoint = <&dp0_connector_in>;
> +};
> +
> +&mdss_dp0_phy {
> +	status = "okay";
> +
> +	vdda-phy-supply = <&vreg_l5a>;
> +	vdda-pll-supply = <&vreg_l4a>;
I couldn't find the reference for these, so I have to trust you

Konrad

Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Yongxing Mou]

On 2024/12/6 5:36, Konrad Dybcio wrote:
> On 27.11.2024 11:45 AM, Yongxing Mou wrote:
>> Add device tree nodes for the DPTX0 controller with their
>> corresponding PHYs found on Qualcomm QCS8300 SoC.
>>
>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++-
>>   1 file changed, 114 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 {
>>   				interrupt-parent = <&mdss>;
>>   				interrupts = <0>;
>>   
>> +				ports {
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +
>> +					port@0 {
>> +						reg = <0>;
>> +
>> +						dpu_intf0_out: endpoint {
>> +							remote-endpoint = <&mdss_dp0_in>;
>> +						};
>> +					};
>> +				};
>> +
>>   				mdp_opp_table: opp-table {
>>   					compatible = "operating-points-v2";
>>   
>> @@ -1011,6 +1024,104 @@ opp-650000000 {
>>   					};
>>   				};
>>   			};
>> +
>> +			mdss_dp0_phy: phy@aec2a00 {
>> +				compatible = "qcom,qcs8300-edp-phy";
>> +
>> +				reg = <0x0 0x0aec2a00 0x0 0x200>,
> 
> 0x19c
> 
got it.thanks.
>> +				      <0x0 0x0aec2200 0x0 0xd0>,
> 
> 0xec
got it.thanks.
>> +				      <0x0 0x0aec2600 0x0 0xd0>,
> 
> 0xec
> 
> For lengths
got it.thanks.
> 
>> +				      <0x0 0x0aec2000 0x0 0x1c8>;
> 
> This one's correct
> 
>> +
>> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> +					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
>> +				clock-names = "aux",
>> +					      "cfg_ahb";
> 
> power-domains = <&rpmhpd RPMHPD_MX>;
> 
emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu..
> (or maybe even MXC?)
> 
>> +
>> +				#clock-cells = <1>;
>> +				#phy-cells = <0>;
>> +
>> +				status = "disabled";
>> +			};
>> +
>> +			mdss_dp0: displayport-controller@af54000 {
>> +				compatible = "qcom,qcs8300-dp";
>> +
>> +				reg = <0x0 0x0af54000 0x0 0x104>,
> 0x200
> 
got it. thanks.
>> +				      <0x0 0x0af54200 0x0 0x0c0>,
> 0x200
> 
got it. thanks.
>> +				      <0x0 0x0af55000 0x0 0x770>,
> 0xc00
> 
got it. thanks.
>> +				      <0x0 0x0af56000 0x0 0x09c>;
> 0x400
> 
will modify all the length in patch v2.
> for lengths
> 
> Konrad

Re: [PATCH 2/2] arm64: dts: qcom: qcs8300-ride: Enable Display Port

[Yongxing Mou]

On 2024/12/6 5:46, Konrad Dybcio wrote:
> On 27.11.2024 11:45 AM, Yongxing Mou wrote:
>> Enable DPTX0 along with their corresponding PHYs for
>> qcs8300-ride platform.
>>
>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
>> ---
> 
> [...]
> 
>> +
>> +	dp0-connector {
>> +		compatible = "dp-connector";
>> +		label = "DP0";
>> +		type = "full-size";
> 
> I was surprised to see it but yeah this is real
> 
>> +
>> +		port {
>> +			dp0_connector_in: endpoint {
>> +				remote-endpoint = <&mdss_dp0_out>;
>> +			};
>> +		};
>> +	};
>>   };
>>   
>>   &apps_rsc {
>> @@ -223,6 +235,30 @@ &gcc {
>>   		 <0>;
>>   };
>>   
>> +&mdss {
>> +	status = "okay";
>> +};
>> +
>> +&mdss_dp0 {
>> +	status = "okay";
> status should be the last property
> 
got it. thanks for ponit it.
>> +
>> +	pinctrl-0 = <&dp_hot_plug_det>;
>> +	pinctrl-names = "default";
>> +};
>> +
>> +&mdss_dp0_out {
>> +	data-lanes = <0 1 2 3>;
>> +	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
>> +	remote-endpoint = <&dp0_connector_in>;
>> +};
>> +
>> +&mdss_dp0_phy {
>> +	status = "okay";
>> +
>> +	vdda-phy-supply = <&vreg_l5a>;
>> +	vdda-pll-supply = <&vreg_l4a>;
> I couldn't find the reference for these, so I have to trust you
> 
yes, this two power can work for qcs8300.and we verify it.status also 
should be last property?
> Konrad
> 

Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Dmitry Baryshkov]

On Thu, Dec 26, 2024 at 03:03:46PM +0800, Yongxing Mou wrote:
> 
> 
> On 2024/12/6 5:36, Konrad Dybcio wrote:
> > On 27.11.2024 11:45 AM, Yongxing Mou wrote:
> > 
> > > +
> > > +				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> > > +					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
> > > +				clock-names = "aux",
> > > +					      "cfg_ahb";
> > 
> > power-domains = <&rpmhpd RPMHPD_MX>;
> > 
> emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu..
> > (or maybe even MXC?)

But it is a DP PHY, not a MDSS or DPU. Is the PLL being sourced by MMCX
or by MX?

-- 
With best wishes
Dmitry

Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Konrad Dybcio]

On 26.12.2024 8:03 AM, Yongxing Mou wrote:
> 
> 
> On 2024/12/6 5:36, Konrad Dybcio wrote:
>> On 27.11.2024 11:45 AM, Yongxing Mou wrote:
>>> Add device tree nodes for the DPTX0 controller with their
>>> corresponding PHYs found on Qualcomm QCS8300 SoC.
>>>
>>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
>>> ---

[...]

>>> +            mdss_dp0_phy: phy@aec2a00 {
>>> +                compatible = "qcom,qcs8300-edp-phy";
>>> +
>>> +                reg = <0x0 0x0aec2a00 0x0 0x200>,
>>
>> 0x19c
>>
> got it.thanks.
>>> +                      <0x0 0x0aec2200 0x0 0xd0>,
>>
>> 0xec
> got it.thanks.
>>> +                      <0x0 0x0aec2600 0x0 0xd0>,
>>
>> 0xec
>>
>> For lengths
> got it.thanks.
>>
>>> +                      <0x0 0x0aec2000 0x0 0x1c8>;
>>
>> This one's correct
>>
>>> +
>>> +                clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>>> +                     <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
>>> +                clock-names = "aux",
>>> +                          "cfg_ahb";
>>
>> power-domains = <&rpmhpd RPMHPD_MX>;
>>
> emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu..
>> (or maybe even MXC?)

Please verify what backs the PHY and update accordingly

Konrad

Re: [PATCH 2/2] arm64: dts: qcom: qcs8300-ride: Enable Display Port

[Konrad Dybcio]

On 26.12.2024 8:06 AM, Yongxing Mou wrote:
> 
> 
> On 2024/12/6 5:46, Konrad Dybcio wrote:
>> On 27.11.2024 11:45 AM, Yongxing Mou wrote:
>>> Enable DPTX0 along with their corresponding PHYs for
>>> qcs8300-ride platform.
>>>
>>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
>>> ---

[...]
>>> +
>>> +&mdss_dp0_out {
>>> +    data-lanes = <0 1 2 3>;
>>> +    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
>>> +    remote-endpoint = <&dp0_connector_in>;
>>> +};
>>> +
>>> +&mdss_dp0_phy {
>>> +    status = "okay";
>>> +
>>> +    vdda-phy-supply = <&vreg_l5a>;
>>> +    vdda-pll-supply = <&vreg_l4a>;
>> I couldn't find the reference for these, so I have to trust you
>>
> yes, this two power can work for qcs8300.and we verify it.status also should be last property?

Yep, it should be the last one, everywhere

Konrad

Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Bjorn Andersson]

On Wed, Nov 27, 2024 at 06:45:13PM +0800, Yongxing Mou wrote:
> Add device tree nodes for the DPTX0 controller with their
> corresponding PHYs found on Qualcomm QCS8300 SoC.
> 
> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>

Please rebase, test and resubmit this together, in the same series, with
the mdss patch.

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++-
>  1 file changed, 114 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 {
>  				interrupt-parent = <&mdss>;
>  				interrupts = <0>;
>  
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						dpu_intf0_out: endpoint {
> +							remote-endpoint = <&mdss_dp0_in>;
> +						};
> +					};
> +				};
> +
>  				mdp_opp_table: opp-table {
>  					compatible = "operating-points-v2";
>  
> @@ -1011,6 +1024,104 @@ opp-650000000 {
>  					};
>  				};
>  			};
> +
> +			mdss_dp0_phy: phy@aec2a00 {
> +				compatible = "qcom,qcs8300-edp-phy";
> +
> +				reg = <0x0 0x0aec2a00 0x0 0x200>,
> +				      <0x0 0x0aec2200 0x0 0xd0>,
> +				      <0x0 0x0aec2600 0x0 0xd0>,
> +				      <0x0 0x0aec2000 0x0 0x1c8>;
> +
> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> +					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
> +				clock-names = "aux",
> +					      "cfg_ahb";
> +
> +				#clock-cells = <1>;
> +				#phy-cells = <0>;
> +
> +				status = "disabled";
> +			};
> +
> +			mdss_dp0: displayport-controller@af54000 {
> +				compatible = "qcom,qcs8300-dp";
> +
> +				reg = <0x0 0x0af54000 0x0 0x104>,
> +				      <0x0 0x0af54200 0x0 0x0c0>,
> +				      <0x0 0x0af55000 0x0 0x770>,
> +				      <0x0 0x0af56000 0x0 0x09c>;
> +
> +				interrupt-parent = <&mdss>;
> +				interrupts = <12>;
> +
> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
> +					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> +					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
> +					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> +					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> +				clock-names = "core_iface",
> +					      "core_aux",
> +					      "ctrl_link",
> +					      "ctrl_link_iface",
> +					      "stream_pixel";
> +				assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> +						  <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> +				assigned-clock-parents = <&mdss_dp0_phy 0>,
> +							 <&mdss_dp0_phy 1>;
> +				phys = <&mdss_dp0_phy>;
> +				phy-names = "dp";
> +
> +				operating-points-v2 = <&dp_opp_table>;
> +				power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> +				#sound-dai-cells = <0>;
> +
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						mdss_dp0_in: endpoint {
> +							remote-endpoint = <&dpu_intf0_out>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +
> +						mdss_dp0_out: endpoint { };
> +					};
> +				};
> +
> +				dp_opp_table: opp-table {
> +					compatible = "operating-points-v2";
> +
> +					opp-160000000 {
> +						opp-hz = /bits/ 64 <160000000>;
> +						required-opps = <&rpmhpd_opp_low_svs>;
> +					};
> +
> +					opp-270000000 {
> +						opp-hz = /bits/ 64 <270000000>;
> +						required-opps = <&rpmhpd_opp_svs>;
> +					};
> +
> +					opp-540000000 {
> +						opp-hz = /bits/ 64 <540000000>;
> +						required-opps = <&rpmhpd_opp_svs_l1>;
> +					};
> +
> +					opp-810000000 {
> +						opp-hz = /bits/ 64 <810000000>;
> +						required-opps = <&rpmhpd_opp_nom>;
> +					};
> +				};
> +			};
>  		};
>  
>  		dispcc: clock-controller@af00000 {
> @@ -1020,7 +1131,9 @@ dispcc: clock-controller@af00000 {
>  				 <&rpmhcc RPMH_CXO_CLK>,
>  				 <&rpmhcc RPMH_CXO_CLK_A>,
>  				 <&sleep_clk>,
> -				 <0>, <0>, <0>, <0>,
> +				 <&mdss_dp0_phy 0>,
> +				 <&mdss_dp0_phy 1>,
> +				 <0>, <0>,
>  				 <0>, <0>, <0>, <0>;
>  			power-domains = <&rpmhpd RPMHPD_MMCX>;
>  			#clock-cells = <1>;
> 
> -- 
> 2.34.1
> 

Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Yongxing Mou]

On 2024/12/27 3:57, Dmitry Baryshkov wrote:
> On Thu, Dec 26, 2024 at 03:03:46PM +0800, Yongxing Mou wrote:
>>
>>
>> On 2024/12/6 5:36, Konrad Dybcio wrote:
>>> On 27.11.2024 11:45 AM, Yongxing Mou wrote:
>>>
>>>> +
>>>> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>>>> +					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
>>>> +				clock-names = "aux",
>>>> +					      "cfg_ahb";
>>>
>>> power-domains = <&rpmhpd RPMHPD_MX>;
>>>
>> emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu..
>>> (or maybe even MXC?)
> 
> But it is a DP PHY, not a MDSS or DPU. Is the PLL being sourced by MMCX
> or by MX?
> 
Hi, thank for pointing it.We confirm it, and this should use RPMHPD_MX 
not RPMHPD_MMCX.

Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Yongxing Mou]

On 2024/12/30 21:27, Konrad Dybcio wrote:
> On 26.12.2024 8:03 AM, Yongxing Mou wrote:
>>
>>
>> On 2024/12/6 5:36, Konrad Dybcio wrote:
>>> On 27.11.2024 11:45 AM, Yongxing Mou wrote:
>>>> Add device tree nodes for the DPTX0 controller with their
>>>> corresponding PHYs found on Qualcomm QCS8300 SoC.
>>>>
>>>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
>>>> ---
> 
> [...]
> 
>>>> +            mdss_dp0_phy: phy@aec2a00 {
>>>> +                compatible = "qcom,qcs8300-edp-phy";
>>>> +
>>>> +                reg = <0x0 0x0aec2a00 0x0 0x200>,
>>>
>>> 0x19c
>>>
>> got it.thanks.
>>>> +                      <0x0 0x0aec2200 0x0 0xd0>,
>>>
>>> 0xec
>> got it.thanks.
>>>> +                      <0x0 0x0aec2600 0x0 0xd0>,
>>>
>>> 0xec
>>>
>>> For lengths
>> got it.thanks.
>>>
>>>> +                      <0x0 0x0aec2000 0x0 0x1c8>;
>>>
>>> This one's correct
>>>
>>>> +
>>>> +                clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>>>> +                     <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
>>>> +                clock-names = "aux",
>>>> +                          "cfg_ahb";
>>>
>>> power-domains = <&rpmhpd RPMHPD_MX>;
>>>
>> emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu..
>>> (or maybe even MXC?)
> 
> Please verify what backs the PHY and update accordingly
> 
> Konrad

Thank you for the reminder. it should use RPMHPD_MX.My previous 
understanding that using MMCX was incorrect.

Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device nodes

[Yongxing Mou]

On 2025/1/9 7:06, Bjorn Andersson wrote:
> On Wed, Nov 27, 2024 at 06:45:13PM +0800, Yongxing Mou wrote:
>> Add device tree nodes for the DPTX0 controller with their
>> corresponding PHYs found on Qualcomm QCS8300 SoC.
>>
>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
> 
> Please rebase, test and resubmit this together, in the same series, with
> the mdss patch.
> 
> Regards,
> Bjorn
> 
sure. got it. I will integrate the mdss dts change with this and submit 
it together.thanks.
>> ---
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++-
>>   1 file changed, 114 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 {
>>   				interrupt-parent = <&mdss>;
>>   				interrupts = <0>;
>>   
>> +				ports {
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +
>> +					port@0 {
>> +						reg = <0>;
>> +
>> +						dpu_intf0_out: endpoint {
>> +							remote-endpoint = <&mdss_dp0_in>;
>> +						};
>> +					};
>> +				};
>> +
>>   				mdp_opp_table: opp-table {
>>   					compatible = "operating-points-v2";
>>   
>> @@ -1011,6 +1024,104 @@ opp-650000000 {
>>   					};
>>   				};
>>   			};
>> +
>> +			mdss_dp0_phy: phy@aec2a00 {
>> +				compatible = "qcom,qcs8300-edp-phy";
>> +
>> +				reg = <0x0 0x0aec2a00 0x0 0x200>,
>> +				      <0x0 0x0aec2200 0x0 0xd0>,
>> +				      <0x0 0x0aec2600 0x0 0xd0>,
>> +				      <0x0 0x0aec2000 0x0 0x1c8>;
>> +
>> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> +					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
>> +				clock-names = "aux",
>> +					      "cfg_ahb";
>> +
>> +				#clock-cells = <1>;
>> +				#phy-cells = <0>;
>> +
>> +				status = "disabled";
>> +			};
>> +
>> +			mdss_dp0: displayport-controller@af54000 {
>> +				compatible = "qcom,qcs8300-dp";
>> +
>> +				reg = <0x0 0x0af54000 0x0 0x104>,
>> +				      <0x0 0x0af54200 0x0 0x0c0>,
>> +				      <0x0 0x0af55000 0x0 0x770>,
>> +				      <0x0 0x0af56000 0x0 0x09c>;
>> +
>> +				interrupt-parent = <&mdss>;
>> +				interrupts = <12>;
>> +
>> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
>> +					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> +					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> +					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> +					 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> +				clock-names = "core_iface",
>> +					      "core_aux",
>> +					      "ctrl_link",
>> +					      "ctrl_link_iface",
>> +					      "stream_pixel";
>> +				assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> +						  <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> +				assigned-clock-parents = <&mdss_dp0_phy 0>,
>> +							 <&mdss_dp0_phy 1>;
>> +				phys = <&mdss_dp0_phy>;
>> +				phy-names = "dp";
>> +
>> +				operating-points-v2 = <&dp_opp_table>;
>> +				power-domains = <&rpmhpd RPMHPD_MMCX>;
>> +
>> +				#sound-dai-cells = <0>;
>> +
>> +				status = "disabled";
>> +
>> +				ports {
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +
>> +					port@0 {
>> +						reg = <0>;
>> +
>> +						mdss_dp0_in: endpoint {
>> +							remote-endpoint = <&dpu_intf0_out>;
>> +						};
>> +					};
>> +
>> +					port@1 {
>> +						reg = <1>;
>> +
>> +						mdss_dp0_out: endpoint { };
>> +					};
>> +				};
>> +
>> +				dp_opp_table: opp-table {
>> +					compatible = "operating-points-v2";
>> +
>> +					opp-160000000 {
>> +						opp-hz = /bits/ 64 <160000000>;
>> +						required-opps = <&rpmhpd_opp_low_svs>;
>> +					};
>> +
>> +					opp-270000000 {
>> +						opp-hz = /bits/ 64 <270000000>;
>> +						required-opps = <&rpmhpd_opp_svs>;
>> +					};
>> +
>> +					opp-540000000 {
>> +						opp-hz = /bits/ 64 <540000000>;
>> +						required-opps = <&rpmhpd_opp_svs_l1>;
>> +					};
>> +
>> +					opp-810000000 {
>> +						opp-hz = /bits/ 64 <810000000>;
>> +						required-opps = <&rpmhpd_opp_nom>;
>> +					};
>> +				};
>> +			};
>>   		};
>>   
>>   		dispcc: clock-controller@af00000 {
>> @@ -1020,7 +1131,9 @@ dispcc: clock-controller@af00000 {
>>   				 <&rpmhcc RPMH_CXO_CLK>,
>>   				 <&rpmhcc RPMH_CXO_CLK_A>,
>>   				 <&sleep_clk>,
>> -				 <0>, <0>, <0>, <0>,
>> +				 <&mdss_dp0_phy 0>,
>> +				 <&mdss_dp0_phy 1>,
>> +				 <0>, <0>,
>>   				 <0>, <0>, <0>, <0>;
>>   			power-domains = <&rpmhpd RPMHPD_MMCX>;
>>   			#clock-cells = <1>;
>>
>> -- 
>> 2.34.1
>>