[RFC PATCH 00/11] drm/msm: Add support for SM8750

[RFC PATCH 00/11] drm/msm: Add support for SM8750

[Krzysztof Kozlowski]

Hi,

RFC or WIP: support is not yet finished because of two important
differences not yet implemented.
1. DPU_CTL_NO_LAYER_EXT: see last commit
2. SDE_MIXER_X_SRC_SEL: LM crossbar: also hardware changes requiring
   each pipe rectangle to be programmed separately in X_SRC_SEL blend
   stage. Downstream patch is bigger than above (1).

Sending this early, to gather comments or maybe find volunteers for
implementing above missing pieces. :)

The hardware catalog and DSI parts should be finished.

Best regards,
Krzysztof

---
Krzysztof Kozlowski (11):
      dt-bindings: display/msm: dsi-controller-main: Combine if:then: entries
      dt-bindings: display/msm: dsi-controller-main: Add missing minItems
      dt-bindings: display/msm: dsi-phy-7nm: Add SM8750
      dt-bindings: display/msm: dsi-controller-main: Add SM8750
      dt-bindings: display/msm: dp-controller: Add SM8750
      dt-bindings: display/msm: qcom,sm8650-dpu: Add SM8750
      dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750
      drm/msm/dsi: Add support for SM8750
      drm/msm/dpu: Add support for SM8750
      drm/msm/mdss: Add support for SM8750
      [RFC / WIP] drm/msm/dpu: WIP: CTL_LAYER_EXT is gone

 .../bindings/display/msm/dp-controller.yaml        |   4 +
 .../bindings/display/msm/dsi-controller-main.yaml  | 124 +++--
 .../bindings/display/msm/dsi-phy-7nm.yaml          |   1 +
 .../bindings/display/msm/qcom,sm8650-dpu.yaml      |   1 +
 .../bindings/display/msm/qcom,sm8750-mdss.yaml     | 460 ++++++++++++++++++
 .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h    | 522 +++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  38 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         |  16 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   6 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
 drivers/gpu/drm/msm/dsi/dsi.h                      |   2 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  25 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
 drivers/gpu/drm/msm/dsi/dsi_host.c                 |  80 ++++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c          |  78 ++-
 drivers/gpu/drm/msm/msm_mdss.c                     |  33 ++
 drivers/gpu/drm/msm/msm_mdss.h                     |   1 +
 .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml  |  14 +
 21 files changed, 1335 insertions(+), 79 deletions(-)
---
base-commit: c38a35d266317199e72729fbbca5b2337c20a6d9
change-id: 20250109-b4-sm8750-display-6ea537754af1

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

[PATCH RFC 01/11] dt-bindings: display/msm: dsi-controller-main: Combine if:then: entries

[Krzysztof Kozlowski]

Several devices have the same clock inputs, thus they can be in the same
if:then: clause, making everything smaller.  No functional impact.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../bindings/display/msm/dsi-controller-main.yaml  | 64 ++--------------------
 1 file changed, 5 insertions(+), 59 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index a9636b76854d0f781923e06b90503dec11b25763..a90255f60d9e31c9c7ed94816284fa8f0d71d392 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -248,24 +248,6 @@ allOf:
           contains:
             enum:
               - qcom,msm8916-dsi-ctrl
-    then:
-      properties:
-        clocks:
-          maxItems: 6
-        clock-names:
-          items:
-            - const: mdp_core
-            - const: iface
-            - const: bus
-            - const: byte
-            - const: pixel
-            - const: core
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
               - qcom,msm8953-dsi-ctrl
               - qcom,msm8976-dsi-ctrl
     then:
@@ -328,28 +310,13 @@ allOf:
           contains:
             enum:
               - qcom,msm8998-dsi-ctrl
-              - qcom,sm6125-dsi-ctrl
-              - qcom,sm6350-dsi-ctrl
-    then:
-      properties:
-        clocks:
-          maxItems: 6
-        clock-names:
-          items:
-            - const: byte
-            - const: byte_intf
-            - const: pixel
-            - const: core
-            - const: iface
-            - const: bus
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
               - qcom,sc7180-dsi-ctrl
               - qcom,sc7280-dsi-ctrl
+              - qcom,sdm845-dsi-ctrl
+              - qcom,sm6115-dsi-ctrl
+              - qcom,sm6125-dsi-ctrl
+              - qcom,sm6350-dsi-ctrl
+              - qcom,sm6375-dsi-ctrl
               - qcom,sm6150-dsi-ctrl
               - qcom,sm7150-dsi-ctrl
               - qcom,sm8150-dsi-ctrl
@@ -393,27 +360,6 @@ allOf:
             - const: pixel
             - const: core
 
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sdm845-dsi-ctrl
-              - qcom,sm6115-dsi-ctrl
-              - qcom,sm6375-dsi-ctrl
-    then:
-      properties:
-        clocks:
-          maxItems: 6
-        clock-names:
-          items:
-            - const: byte
-            - const: byte_intf
-            - const: pixel
-            - const: core
-            - const: iface
-            - const: bus
-
 unevaluatedProperties: false
 
 examples:

-- 
2.43.0

[PATCH RFC 02/11] dt-bindings: display/msm: dsi-controller-main: Add missing minItems

[Krzysztof Kozlowski]

Specific constrain in if:then: blocks for variable lists, like clocks
and clock-names, should have a fixed upper and lower size.  Older
dtschema implied minItems, but that's not true since 2024 and missing
minItems means that lower bound is not set.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/display/msm/dsi-controller-main.yaml        | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index a90255f60d9e31c9c7ed94816284fa8f0d71d392..c99dd06f2db9a7a77665ab057d05d87fd3ec2ec2 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -231,6 +231,7 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 7
           maxItems: 7
         clock-names:
           items:
@@ -253,6 +254,7 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 6
           maxItems: 6
         clock-names:
           items:
@@ -273,6 +275,7 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 7
           maxItems: 7
         clock-names:
           items:
@@ -293,6 +296,7 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 7
           maxItems: 7
         clock-names:
           items:
@@ -328,6 +332,7 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 6
           maxItems: 6
         clock-names:
           items:
@@ -347,6 +352,7 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 9
           maxItems: 9
         clock-names:
           items:

-- 
2.43.0

[PATCH RFC 03/11] dt-bindings: display/msm: dsi-phy-7nm: Add SM8750

[Krzysztof Kozlowski]

Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
index 7e764eac3ef31829e745673ea91d4135921d61e5..e356a65a97e901104a29ffe8e5ac04dbaaad6bd3 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
@@ -23,6 +23,7 @@ properties:
       - qcom,sm8450-dsi-phy-5nm
       - qcom,sm8550-dsi-phy-4nm
       - qcom,sm8650-dsi-phy-4nm
+      - qcom,sm8750-dsi-phy-3nm
 
   reg:
     items:

-- 
2.43.0

[PATCH RFC 04/11] dt-bindings: display/msm: dsi-controller-main: Add SM8750

[Krzysztof Kozlowski]

Add DSI controller for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.

It does not allow the display clock controller clocks like "byte" and
"pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not
configured (not prepared, rate not set).  Therefore
assigned-clock-parents are not working here and driver is responsible
for reparenting clocks with proper procedure.  These clocks are now
inputs to the DSI controller device.

Except that SM8750 DSI comes with several differences, new blocks and
changes in registers, making it incompatible with SM8650.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../bindings/display/msm/dsi-controller-main.yaml  | 54 ++++++++++++++++++++--
 1 file changed, 49 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index c99dd06f2db9a7a77665ab057d05d87fd3ec2ec2..475b3b881c51c0bc526aed54955767a7149fb1d5 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -40,6 +40,7 @@ properties:
               - qcom,sm8450-dsi-ctrl
               - qcom,sm8550-dsi-ctrl
               - qcom,sm8650-dsi-ctrl
+              - qcom,sm8750-dsi-ctrl
           - const: qcom,mdss-dsi-ctrl
       - enum:
           - qcom,dsi-ctrl-6g-qcm2290
@@ -68,11 +69,11 @@ properties:
        - mnoc:: MNOC clock
        - pixel:: Display pixel clock.
     minItems: 3
-    maxItems: 9
+    maxItems: 12
 
   clock-names:
     minItems: 3
-    maxItems: 9
+    maxItems: 12
 
   phys:
     maxItems: 1
@@ -107,7 +108,8 @@ properties:
     minItems: 2
     maxItems: 4
     description: |
-      Parents of "byte" and "pixel" for the given platform.
+      For DSI on SM8650 and older: parents of "byte" and "pixel" for the given
+      platform.
       For DSIv2 platforms this should contain "byte", "esc", "src" and
       "pixel_src" clocks.
 
@@ -216,8 +218,6 @@ required:
   - clocks
   - clock-names
   - phys
-  - assigned-clocks
-  - assigned-clock-parents
   - ports
 
 allOf:
@@ -242,6 +242,9 @@ allOf:
             - const: byte
             - const: pixel
             - const: core
+      required:
+        - assigned-clocks
+        - assigned-clock-parents
 
   - if:
       properties:
@@ -264,6 +267,9 @@ allOf:
             - const: byte
             - const: pixel
             - const: core
+      required:
+        - assigned-clocks
+        - assigned-clock-parents
 
   - if:
       properties:
@@ -286,6 +292,9 @@ allOf:
             - const: pixel
             - const: core
             - const: core_mmss
+      required:
+        - assigned-clocks
+        - assigned-clock-parents
 
   - if:
       properties:
@@ -307,6 +316,9 @@ allOf:
             - const: core_mmss
             - const: pixel
             - const: core
+      required:
+        - assigned-clocks
+        - assigned-clock-parents
 
   - if:
       properties:
@@ -342,6 +354,35 @@ allOf:
             - const: core
             - const: iface
             - const: bus
+      required:
+        - assigned-clocks
+        - assigned-clock-parents
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-dsi-ctrl
+    then:
+      properties:
+        clocks:
+          minItems: 12
+          maxItems: 12
+        clock-names:
+          items:
+            - const: byte
+            - const: byte_intf
+            - const: pixel
+            - const: core
+            - const: iface
+            - const: bus
+            - const: dsi_pll_pixel
+            - const: dsi_pll_byte
+            - const: esync
+            - const: osc
+            - const: byte_src
+            - const: pixel_src
 
   - if:
       properties:
@@ -365,6 +406,9 @@ allOf:
             - const: core_mmss
             - const: pixel
             - const: core
+      required:
+        - assigned-clocks
+        - assigned-clock-parents
 
 unevaluatedProperties: false
 

-- 
2.43.0

[PATCH RFC 05/11] dt-bindings: display/msm: dp-controller: Add SM8750

[Krzysztof Kozlowski]

Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
fully compatible with earlier SM8650 variant.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index e00b88332f2fed2fc33f6d72c5cc3d827cd7594e..a4bf9e07a28355c0391d1757fab16ebe5ff14a44 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -37,6 +37,10 @@ properties:
               - qcom,sm8450-dp
               - qcom,sm8550-dp
           - const: qcom,sm8350-dp
+      - items:
+          - enum:
+              - qcom,sm8750-dp
+          - const: qcom,sm8650-dp
 
   reg:
     minItems: 4

-- 
2.43.0

[PATCH RFC 06/11] dt-bindings: display/msm: qcom,sm8650-dpu: Add SM8750

[Krzysztof Kozlowski]

Add DPU for Qualcomm SM8750 SoC which has several differences, new
blocks and changes in registers, making it incompatible with SM8650.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
index 01cf79bd754b491349c52c5aef49ba06e835d0bf..0a46120dd8680371ed031f7773859716f49c3aa1 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
@@ -16,6 +16,7 @@ properties:
     enum:
       - qcom,sa8775p-dpu
       - qcom,sm8650-dpu
+      - qcom,sm8750-dpu
       - qcom,x1e80100-dpu
 
   reg:

-- 
2.43.0

[PATCH RFC 07/11] dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750

[Krzysztof Kozlowski]

Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation
with two revisions up of the IP block comparing to SM8650.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../bindings/display/msm/qcom,sm8750-mdss.yaml     | 460 +++++++++++++++++++++
 1 file changed, 460 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..cfa21b0d081338f1b94779594798f86284ba0677
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
@@ -0,0 +1,460 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8750-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8750 Display MDSS
+
+maintainers:
+  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+  SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+  DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sm8750-mdss
+
+  clocks:
+    items:
+      - description: Display AHB
+      - description: Display hf AXI
+      - description: Display core
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    maxItems: 2
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        const: qcom,sm8750-dpu
+
+  "^displayport-controller@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        items:
+          - const: qcom,sm8750-dp
+          - const: qcom,sm8650-dp
+
+  "^dsi@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        items:
+          - const: qcom,sm8750-dsi-ctrl
+          - const: qcom,mdss-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        const: qcom,sm8750-dsi-phy-3nm
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/phy/phy-qcom-qmp.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    display-subsystem@ae00000 {
+            compatible = "qcom,sm8750-mdss";
+            reg = <0x0ae00000 0x1000>;
+            reg-names = "mdss";
+
+            interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+            clocks = <&disp_cc_mdss_ahb_clk>,
+                     <&gcc_disp_hf_axi_clk>,
+                     <&disp_cc_mdss_mdp_clk>;
+
+            resets = <&disp_cc_mdss_core_bcr>;
+
+            power-domains = <&mdss_gdsc>;
+
+            iommus = <&apps_smmu 0x800 0x2>;
+
+            interrupt-controller;
+            #interrupt-cells = <1>;
+
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges;
+
+            display-controller@ae01000 {
+                compatible = "qcom,sm8750-dpu";
+                reg = <0x0ae01000 0x93000>,
+                      <0x0aeb0000 0x2008>;
+                reg-names = "mdp",
+                            "vbif";
+
+                interrupts-extended = <&mdss 0>;
+
+                clocks = <&gcc_disp_hf_axi_clk>,
+                         <&disp_cc_mdss_ahb_clk>,
+                         <&disp_cc_mdss_mdp_lut_clk>,
+                         <&disp_cc_mdss_mdp_clk>,
+                         <&disp_cc_mdss_vsync_clk>;
+                clock-names = "nrt_bus",
+                              "iface",
+                              "lut",
+                              "core",
+                              "vsync";
+
+                assigned-clocks = <&disp_cc_mdss_vsync_clk>;
+                assigned-clock-rates = <19200000>;
+
+                operating-points-v2 = <&mdp_opp_table>;
+
+                power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        dpu_intf1_out: endpoint {
+                            remote-endpoint = <&mdss_dsi0_in>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        dpu_intf2_out: endpoint {
+                            remote-endpoint = <&mdss_dsi1_in>;
+                        };
+                    };
+
+                    port@2 {
+                        reg = <2>;
+
+                        dpu_intf0_out: endpoint {
+                            remote-endpoint = <&mdss_dp0_in>;
+                        };
+                    };
+                };
+
+                mdp_opp_table: opp-table {
+                    compatible = "operating-points-v2";
+
+                    opp-207000000 {
+                        opp-hz = /bits/ 64 <207000000>;
+                        required-opps = <&rpmhpd_opp_low_svs>;
+                    };
+
+                    opp-337000000 {
+                        opp-hz = /bits/ 64 <337000000>;
+                        required-opps = <&rpmhpd_opp_svs>;
+                    };
+
+                    opp-417000000 {
+                        opp-hz = /bits/ 64 <417000000>;
+                        required-opps = <&rpmhpd_opp_svs_l1>;
+                    };
+
+                    opp-532000000 {
+                        opp-hz = /bits/ 64 <532000000>;
+                        required-opps = <&rpmhpd_opp_nom>;
+                    };
+
+                    opp-575000000 {
+                        opp-hz = /bits/ 64 <575000000>;
+                        required-opps = <&rpmhpd_opp_nom_l1>;
+                    };
+                };
+            };
+
+            dsi@ae94000 {
+                compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+                reg = <0x0ae94000 0x400>;
+                reg-names = "dsi_ctrl";
+
+                interrupts-extended = <&mdss 4>;
+
+                clocks = <&disp_cc_mdss_byte0_clk>,
+                         <&disp_cc_mdss_byte0_intf_clk>,
+                         <&disp_cc_mdss_pclk0_clk>,
+                         <&disp_cc_mdss_esc0_clk>,
+                         <&disp_cc_mdss_ahb_clk>,
+                         <&gcc_disp_hf_axi_clk>,
+                         <&mdss_dsi0_phy 1>,
+                         <&mdss_dsi0_phy 0>,
+                         <&disp_cc_esync0_clk>,
+                         <&disp_cc_osc_clk>,
+                         <&disp_cc_mdss_byte0_clk_src>,
+                         <&disp_cc_mdss_pclk0_clk_src>;
+                clock-names = "byte",
+                              "byte_intf",
+                              "pixel",
+                              "core",
+                              "iface",
+                              "bus",
+                              "dsi_pll_pixel",
+                              "dsi_pll_byte",
+                              "esync",
+                              "osc",
+                              "byte_src",
+                              "pixel_src";
+
+                operating-points-v2 = <&mdss_dsi_opp_table>;
+
+                power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+                phys = <&mdss_dsi0_phy>;
+                phy-names = "dsi";
+
+                vdda-supply = <&vreg_l3g_1p2>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        mdss_dsi0_in: endpoint {
+                            remote-endpoint = <&dpu_intf1_out>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        mdss_dsi0_out: endpoint {
+                            remote-endpoint = <&panel0_in>;
+                            data-lanes = <0 1 2 3>;
+                        };
+                    };
+                };
+
+                mdss_dsi_opp_table: opp-table {
+                    compatible = "operating-points-v2";
+
+                    opp-187500000 {
+                        opp-hz = /bits/ 64 <187500000>;
+                        required-opps = <&rpmhpd_opp_low_svs>;
+                    };
+
+                    opp-300000000 {
+                        opp-hz = /bits/ 64 <300000000>;
+                        required-opps = <&rpmhpd_opp_svs>;
+                    };
+
+                    opp-358000000 {
+                        opp-hz = /bits/ 64 <358000000>;
+                        required-opps = <&rpmhpd_opp_svs_l1>;
+                    };
+                };
+            };
+
+            mdss_dsi0_phy: phy@ae95000 {
+                compatible = "qcom,sm8750-dsi-phy-3nm";
+                reg = <0x0ae95000 0x200>,
+                      <0x0ae95200 0x280>,
+                      <0x0ae95500 0x400>;
+                reg-names = "dsi_phy",
+                            "dsi_phy_lane",
+                            "dsi_pll";
+
+                clocks = <&disp_cc_mdss_ahb_clk>,
+                         <&rpmhcc RPMH_CXO_CLK>;
+                clock-names = "iface",
+                              "ref";
+
+                vdds-supply = <&vreg_l3i_0p88>;
+
+                #clock-cells = <1>;
+                #phy-cells = <0>;
+            };
+
+            dsi@ae96000 {
+                compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+                reg = <0x0ae96000 0x400>;
+                reg-names = "dsi_ctrl";
+
+                interrupts-extended = <&mdss 5>;
+
+                clocks = <&disp_cc_mdss_byte1_clk>,
+                         <&disp_cc_mdss_byte1_intf_clk>,
+                         <&disp_cc_mdss_pclk1_clk>,
+                         <&disp_cc_mdss_esc1_clk>,
+                         <&disp_cc_mdss_ahb_clk>,
+                         <&gcc_disp_hf_axi_clk>,
+                         <&mdss_dsi1_phy 1>,
+                         <&mdss_dsi1_phy 0>,
+                         <&disp_cc_esync1_clk>,
+                         <&disp_cc_osc_clk>,
+                         <&disp_cc_mdss_byte1_clk_src>,
+                         <&disp_cc_mdss_pclk1_clk_src>;
+                clock-names = "byte",
+                              "byte_intf",
+                              "pixel",
+                              "core",
+                              "iface",
+                              "bus",
+                              "dsi_pll_pixel",
+                              "dsi_pll_byte",
+                              "esync",
+                              "osc",
+                              "byte_src",
+                              "pixel_src";
+
+                operating-points-v2 = <&mdss_dsi_opp_table>;
+
+                power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+                phys = <&mdss_dsi1_phy>;
+                phy-names = "dsi";
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        mdss_dsi1_in: endpoint {
+                            remote-endpoint = <&dpu_intf2_out>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        mdss_dsi1_out: endpoint {
+                        };
+                    };
+                };
+            };
+
+            mdss_dsi1_phy: phy@ae97000 {
+                compatible = "qcom,sm8750-dsi-phy-3nm";
+                reg = <0x0ae97000 0x200>,
+                      <0x0ae97200 0x280>,
+                      <0x0ae97500 0x400>;
+                reg-names = "dsi_phy",
+                            "dsi_phy_lane",
+                            "dsi_pll";
+
+                clocks = <&disp_cc_mdss_ahb_clk>,
+                         <&rpmhcc RPMH_CXO_CLK>;
+                clock-names = "iface",
+                              "ref";
+
+                #clock-cells = <1>;
+                #phy-cells = <0>;
+            };
+
+            displayport-controller@af54000 {
+                compatible = "qcom,sm8750-dp", "qcom,sm8650-dp";
+                reg = <0xaf54000 0x104>,
+                      <0xaf54200 0xc0>,
+                      <0xaf55000 0x770>,
+                      <0xaf56000 0x9c>,
+                      <0xaf57000 0x9c>;
+
+                interrupts-extended = <&mdss 12>;
+
+                clocks = <&disp_cc_mdss_ahb_clk>,
+                         <&disp_cc_mdss_dptx0_aux_clk>,
+                         <&disp_cc_mdss_dptx0_link_clk>,
+                         <&disp_cc_mdss_dptx0_link_intf_clk>,
+                         <&disp_cc_mdss_dptx0_pixel0_clk>;
+                clock-names = "core_iface",
+                              "core_aux",
+                              "ctrl_link",
+                              "ctrl_link_iface",
+                              "stream_pixel";
+
+                assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,
+                                  <&disp_cc_mdss_dptx0_pixel0_clk_src>;
+                assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                                         <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+                operating-points-v2 = <&dp_opp_table>;
+
+                power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+                phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
+                phy-names = "dp";
+
+                #sound-dai-cells = <0>;
+
+                dp_opp_table: opp-table {
+                    compatible = "operating-points-v2";
+
+                    opp-192000000 {
+                        opp-hz = /bits/ 64 <192000000>;
+                        required-opps = <&rpmhpd_opp_low_svs_d1>;
+                    };
+
+                    opp-270000000 {
+                        opp-hz = /bits/ 64 <270000000>;
+                        required-opps = <&rpmhpd_opp_low_svs>;
+                    };
+
+                    opp-540000000 {
+                        opp-hz = /bits/ 64 <540000000>;
+                        required-opps = <&rpmhpd_opp_svs_l1>;
+                    };
+
+                    opp-810000000 {
+                        opp-hz = /bits/ 64 <810000000>;
+                        required-opps = <&rpmhpd_opp_nom>;
+                    };
+                };
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        mdss_dp0_in: endpoint {
+                            remote-endpoint = <&dpu_intf0_out>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        mdss_dp0_out: endpoint {
+                            remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+                        };
+                    };
+                };
+            };
+        };

-- 
2.43.0

[PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Krzysztof Kozlowski]

Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
differences worth noting:

1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
   offsets were just switched.  Currently these registers are not used
   in the driver, so the easiest is to document both but keep them
   commented out to avoid conflict.

2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
   parents before they are prepared and initial rate is set.  Therefore
   assigned-clock-parents are not working here and driver is responsible
   for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/gpu/drm/msm/dsi/dsi.h                      |  2 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.c                  | 25 +++++++
 drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |  1 +
 drivers/gpu/drm/msm/dsi/dsi_host.c                 | 80 ++++++++++++++++++++++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |  2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |  1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c          | 78 +++++++++++++++++++--
 .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml  | 14 ++++
 8 files changed, 197 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 87496db203d6c7582eadcb74e94eb56a219df292..93c028a122f3a59b1632da76472e0a3e781c6ae8 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -98,6 +98,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi);
 int msm_dsi_runtime_suspend(struct device *dev);
 int msm_dsi_runtime_resume(struct device *dev);
 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host);
+int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host);
 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host);
 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host);
 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host);
@@ -115,6 +116,7 @@ int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *iova);
 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova);
 int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
+int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host);
 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 7754dcec33d06e3d6eb8a9d55e53f24af073adb9..e2a8d6fcc45b6c207a3018ea7c8744fcf34dabd2 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -205,6 +205,17 @@ static const struct msm_dsi_config sm8650_dsi_cfg = {
 	},
 };
 
+static const struct msm_dsi_config sm8750_dsi_cfg = {
+	.io_offset = DSI_6G_REG_SHIFT,
+	.regulator_data = sm8650_dsi_regulators,
+	.num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
+	.bus_clk_names = dsi_v2_4_clk_names,
+	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
+	.io_start = {
+		{ 0xae94000, 0xae96000 },
+	},
+};
+
 static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
 	{ .supply = "vdda", .init_load_uA = 8350 },	/* 1.2 V */
 	{ .supply = "refgen" },
@@ -257,6 +268,18 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
 	.calc_clk_rate = dsi_calc_clk_rate_6g,
 };
 
+static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops = {
+	.link_clk_set_rate = dsi_link_clk_set_rate_6g_v2_9,
+	.link_clk_enable = dsi_link_clk_enable_6g,
+	.link_clk_disable = dsi_link_clk_disable_6g,
+	.clk_init_ver = dsi_clk_init_6g_v2_9,
+	.tx_buf_alloc = dsi_tx_buf_alloc_6g,
+	.tx_buf_get = dsi_tx_buf_get_6g,
+	.tx_buf_put = dsi_tx_buf_put_6g,
+	.dma_base_get = dsi_dma_base_get_6g,
+	.calc_clk_rate = dsi_calc_clk_rate_6g,
+};
+
 static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
 	{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
 		&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
@@ -300,6 +323,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
 		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
 		&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0,
+		&sm8750_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
 };
 
 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 120cb65164c1ba1deb9acb513e5f073bd560c496..859c279afbb0377d16f8406f3e6b083640aff5a1 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -30,6 +30,7 @@
 #define MSM_DSI_6G_VER_MINOR_V2_6_0	0x20060000
 #define MSM_DSI_6G_VER_MINOR_V2_7_0	0x20070000
 #define MSM_DSI_6G_VER_MINOR_V2_8_0	0x20080000
+#define MSM_DSI_6G_VER_MINOR_V2_9_0	0x20090000
 
 #define MSM_DSI_V2_VER_MINOR_8064	0x0
 
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 2218d4f0c5130a0b13f428e89aa30ba2921da572..ced28ee61eedc0a82da9f1d0792f17ee2a5538c4 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -119,6 +119,15 @@ struct msm_dsi_host {
 	struct clk *pixel_clk;
 	struct clk *byte_intf_clk;
 
+	/*
+	 * Clocks which needs to be properly parented between DISPCC and DSI PHY
+	 * PLL:
+	 */
+	struct clk *byte_src_clk;
+	struct clk *pixel_src_clk;
+	struct clk *dsi_pll_byte_clk;
+	struct clk *dsi_pll_pixel_clk;
+
 	unsigned long byte_clk_rate;
 	unsigned long byte_intf_clk_rate;
 	unsigned long pixel_clk_rate;
@@ -269,6 +278,38 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
 	return ret;
 }
 
+int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host)
+{
+	struct device *dev = &msm_host->pdev->dev;
+	int ret;
+
+	ret = dsi_clk_init_6g_v2(msm_host);
+	if (ret)
+		return ret;
+
+	msm_host->byte_src_clk = devm_clk_get(dev, "byte_src");
+	if (IS_ERR(msm_host->byte_src_clk))
+		return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk),
+				     "can't get byte_src clock\n");
+
+	msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte");
+	if (IS_ERR(msm_host->dsi_pll_byte_clk))
+		return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk),
+				     "can't get dsi_pll_byte clock\n");
+
+	msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src");
+	if (IS_ERR(msm_host->pixel_src_clk))
+		return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk),
+				     "can't get pixel_src clock\n");
+
+	msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel");
+	if (IS_ERR(msm_host->dsi_pll_pixel_clk))
+		return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk),
+				     "can't get dsi_pll_pixel clock\n");
+
+	return 0;
+}
+
 static int dsi_clk_init(struct msm_dsi_host *msm_host)
 {
 	struct platform_device *pdev = msm_host->pdev;
@@ -370,6 +411,45 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
 	return 0;
 }
 
+int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host)
+{
+	struct device *dev = &msm_host->pdev->dev;
+	int ret;
+
+	/*
+	 * DSI PHY PLLs have to be enabled to allow reparenting to them and
+	 * setting the rates of pixel/byte clocks.
+	 */
+	ret = clk_prepare_enable(msm_host->dsi_pll_byte_clk);
+	if (ret) {
+		dev_err(dev, "Failed to enable dsi_pll_byte: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(msm_host->dsi_pll_pixel_clk);
+	if (ret) {
+		dev_err(dev, "Failed to enable dsi_pll_byte: %d\n", ret);
+		goto out_disable_byte_clk;
+	}
+
+	ret = clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk);
+	if (ret)
+		dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret);
+
+	ret = clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_clk);
+	if (ret)
+		dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret);
+
+	ret = dsi_link_clk_set_rate_6g(msm_host);
+
+	clk_disable_unprepare(msm_host->dsi_pll_pixel_clk);
+
+out_disable_byte_clk:
+	clk_disable_unprepare(msm_host->dsi_pll_byte_clk);
+
+	return ret;
+}
+
 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
 {
 	int ret;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index c0bcc68289633fd7506ce4f1f963655d862e8f08..60571237efc4d332959ac76ff1d6d6245f688469 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -593,6 +593,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
 	  .data = &dsi_phy_4nm_8550_cfgs },
 	{ .compatible = "qcom,sm8650-dsi-phy-4nm",
 	  .data = &dsi_phy_4nm_8650_cfgs },
+	{ .compatible = "qcom,sm8750-dsi-phy-3nm",
+	  .data = &dsi_phy_3nm_8750_cfgs },
 #endif
 	{}
 };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 8985818bb2e0934e9084a420c90e2269c2e1c414..fdb6c648e16f25812a2948053f31186d4c0d4413 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -60,6 +60,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs;
 
 struct msm_dsi_dphy_timing {
 	u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 031446c87daec0af3f81df324158311f5a80014e..8074eab2956315174c4e503ff94dcd89f9614364 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -49,6 +49,8 @@
 #define DSI_PHY_7NM_QUIRK_V4_3		BIT(3)
 /* Hardware is V5.2 */
 #define DSI_PHY_7NM_QUIRK_V5_2		BIT(4)
+/* Hardware is V7.0 */
+#define DSI_PHY_7NM_QUIRK_V7_0		BIT(5)
 
 struct dsi_pll_config {
 	bool enable_ssc;
@@ -124,9 +126,30 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
 	dec_multiple = div_u64(pll_freq * multiplier, divider);
 	dec = div_u64_rem(dec_multiple, multiplier, &frac);
 
-	if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
+	if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) {
 		config->pll_clock_inverters = 0x28;
-	else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+	} else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
+		if (pll_freq < 160000000ULL)
+			config->pll_clock_inverters = 0xa0;
+		else if (pll_freq < 175000000ULL)
+			config->pll_clock_inverters = 0x20;
+		else if (pll_freq < 325000000ULL)
+			config->pll_clock_inverters = 0xa0;
+		else if (pll_freq < 350000000ULL)
+			config->pll_clock_inverters = 0x20;
+		else if (pll_freq < 650000000ULL)
+			config->pll_clock_inverters = 0xa0;
+		else if (pll_freq < 700000000ULL)
+			config->pll_clock_inverters = 0x20;
+		else if (pll_freq < 1300000000ULL)
+			config->pll_clock_inverters = 0xa0;
+		else if (pll_freq < 2500000000ULL)
+			config->pll_clock_inverters = 0x20;
+		else if (pll_freq < 4000000000ULL)
+			config->pll_clock_inverters = 0x00;
+		else
+			config->pll_clock_inverters = 0x40;
+	} else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
 		if (pll_freq <= 1300000000ULL)
 			config->pll_clock_inverters = 0xa0;
 		else if (pll_freq <= 2500000000ULL)
@@ -245,7 +268,8 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
 			vco_config_1 = 0x01;
 	}
 
-	if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+	if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
+	    (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
 		if (pll->vco_current_rate < 1557000000ULL)
 			vco_config_1 = 0x08;
 		else
@@ -609,6 +633,9 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
 		break;
 	case MSM_DSI_PHY_MASTER:
 		pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
+		/* v7.0: Enable ATB_EN0 and alternate clock output to external phy */
+		if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)
+			writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5);
 		break;
 	case MSM_DSI_PHY_SLAVE:
 		data = 0x1; /* external PLL */
@@ -887,7 +914,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
 
 	/* Request for REFGEN READY */
 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
-	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
+	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
 		writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
 		udelay(500);
 	}
@@ -921,7 +949,20 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
 		lane_ctrl0 = 0x1f;
 	}
 
-	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
+		if (phy->cphy_mode) {
+			/* TODO: different for second phy */
+			vreg_ctrl_0 = 0x57;
+			vreg_ctrl_1 = 0x41;
+			glbl_rescode_top_ctrl = 0x3d;
+			glbl_rescode_bot_ctrl = 0x38;
+		} else {
+			vreg_ctrl_0 = 0x56;
+			vreg_ctrl_1 = 0x19;
+			glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c :  0x03;
+			glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 :  0x3c;
+		}
+	} else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
 		if (phy->cphy_mode) {
 			vreg_ctrl_0 = 0x45;
 			vreg_ctrl_1 = 0x41;
@@ -983,6 +1024,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
 
 	/* program CMN_CTRL_4 for minor_ver 2 chipsets*/
 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
+	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) ||
 	    (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
 		writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4);
 
@@ -1097,7 +1139,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
 
 	/* Turn off REFGEN Vote */
 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
-	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
+	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
 		writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
 		wmb();
 		/* Delay to ensure HW removes vote before PHY shut down */
@@ -1314,3 +1357,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {
 	.num_dsi_phy = 2,
 	.quirks = DSI_PHY_7NM_QUIRK_V5_2,
 };
+
+const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = {
+	.has_phy_lane = true,
+	.regulator_data = dsi_phy_7nm_98000uA_regulators,
+	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
+	.ops = {
+		.enable = dsi_7nm_phy_enable,
+		.disable = dsi_7nm_phy_disable,
+		.pll_init = dsi_pll_7nm_init,
+		.save_pll_state = dsi_7nm_pll_save_state,
+		.restore_pll_state = dsi_7nm_pll_restore_state,
+		.set_continuous_clock = dsi_7nm_set_continuous_clock,
+	},
+	.min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+	.max_pll_rate = 5000000000UL,
+#else
+	.max_pll_rate = ULONG_MAX,
+#endif
+	.io_start = { 0xae95000, 0xae97000 },
+	.num_dsi_phy = 2,
+	.quirks = DSI_PHY_7NM_QUIRK_V7_0,
+};
diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
index d54b72f924493b4bf0925c287366f7b1e18eb46b..f1402c67dda10d149af08ee9ff489e5e7e7099b7 100644
--- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
@@ -18,6 +18,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
 	<reg32 offset="0x00028" name="CTRL_1"/>
 	<reg32 offset="0x0002c" name="CTRL_2"/>
 	<reg32 offset="0x00030" name="CTRL_3"/>
+	<reg32 offset="0x001b0" name="CTRL_5"/>
 	<reg32 offset="0x00034" name="LANE_CFG0"/>
 	<reg32 offset="0x00038" name="LANE_CFG1"/>
 	<reg32 offset="0x0003c" name="PLL_CNTRL"/>
@@ -183,11 +184,24 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
 	<reg32 offset="0x01b0" name="COMMON_STATUS_ONE"/>
 	<reg32 offset="0x01b4" name="COMMON_STATUS_TWO"/>
 	<reg32 offset="0x01b8" name="BAND_SEL_CAL"/>
+	<!--
+	Starting from SM8750, offset moved from 0x01bc to 0x01cc, however
+	we keep only one register map.  That's not a problem, so far,
+        because this register is not used.  The register map should be split
+        once it is going to be used.  Comment out the code to prevent
+	any misuse due to the change in the offset.
 	<reg32 offset="0x01bc" name="ICODE_ACCUM_STATUS_LOW"/>
+	<reg32 offset="0x01cc" name="ICODE_ACCUM_STATUS_LOW"/>
+	-->
 	<reg32 offset="0x01c0" name="ICODE_ACCUM_STATUS_HIGH"/>
 	<reg32 offset="0x01c4" name="FD_OUT_LOW"/>
 	<reg32 offset="0x01c8" name="FD_OUT_HIGH"/>
+	<!--
+	Starting from SM8750, offset moved from 0x01cc to 0x01bc, however
+	we keep only one register map.  See above comment.
 	<reg32 offset="0x01cc" name="ALOG_OBSV_BUS_STATUS_1"/>
+	<reg32 offset="0x01bc" name="ALOG_OBSV_BUS_STATUS_1"/>
+	-->
 	<reg32 offset="0x01d0" name="PLL_MISC_CONFIG"/>
 	<reg32 offset="0x01d4" name="FLL_CONFIG"/>
 	<reg32 offset="0x01d8" name="FLL_FREQ_ACQ_TIME"/>

-- 
2.43.0

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Dmitry Baryshkov]

On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
> differences worth noting:
> 
> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>    offsets were just switched.  Currently these registers are not used
>    in the driver, so the easiest is to document both but keep them
>    commented out to avoid conflict.
> 
> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>    parents before they are prepared and initial rate is set.  Therefore
>    assigned-clock-parents are not working here and driver is responsible
>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().

Isn't it a description of CLK_SET_PARENT_GATE and/or
CLK_OPS_PARENT_ENABLE ?

> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  drivers/gpu/drm/msm/dsi/dsi.h                      |  2 +
>  drivers/gpu/drm/msm/dsi/dsi_cfg.c                  | 25 +++++++
>  drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |  1 +
>  drivers/gpu/drm/msm/dsi/dsi_host.c                 | 80 ++++++++++++++++++++++
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |  2 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |  1 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c          | 78 +++++++++++++++++++--
>  .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml  | 14 ++++

Please separate DSI and PHY changes.

>  8 files changed, 197 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> index 7754dcec33d06e3d6eb8a9d55e53f24af073adb9..e2a8d6fcc45b6c207a3018ea7c8744fcf34dabd2 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> @@ -205,6 +205,17 @@ static const struct msm_dsi_config sm8650_dsi_cfg = {
>  	},
>  };
>  
> +static const struct msm_dsi_config sm8750_dsi_cfg = {
> +	.io_offset = DSI_6G_REG_SHIFT,
> +	.regulator_data = sm8650_dsi_regulators,
> +	.num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
> +	.bus_clk_names = dsi_v2_4_clk_names,
> +	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
> +	.io_start = {
> +		{ 0xae94000, 0xae96000 },
> +	},
> +};
> +
>  static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
>  	{ .supply = "vdda", .init_load_uA = 8350 },	/* 1.2 V */
>  	{ .supply = "refgen" },
> @@ -257,6 +268,18 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
>  	.calc_clk_rate = dsi_calc_clk_rate_6g,
>  };
>  
> +static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops = {
> +	.link_clk_set_rate = dsi_link_clk_set_rate_6g_v2_9,
> +	.link_clk_enable = dsi_link_clk_enable_6g,
> +	.link_clk_disable = dsi_link_clk_disable_6g,
> +	.clk_init_ver = dsi_clk_init_6g_v2_9,
> +	.tx_buf_alloc = dsi_tx_buf_alloc_6g,
> +	.tx_buf_get = dsi_tx_buf_get_6g,
> +	.tx_buf_put = dsi_tx_buf_put_6g,
> +	.dma_base_get = dsi_dma_base_get_6g,
> +	.calc_clk_rate = dsi_calc_clk_rate_6g,
> +};
> +
>  static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>  	{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
>  		&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
> @@ -300,6 +323,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>  		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>  	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
>  		&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> +	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0,
> +		&sm8750_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
>  };
>  
>  const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> index 120cb65164c1ba1deb9acb513e5f073bd560c496..859c279afbb0377d16f8406f3e6b083640aff5a1 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> @@ -30,6 +30,7 @@
>  #define MSM_DSI_6G_VER_MINOR_V2_6_0	0x20060000
>  #define MSM_DSI_6G_VER_MINOR_V2_7_0	0x20070000
>  #define MSM_DSI_6G_VER_MINOR_V2_8_0	0x20080000
> +#define MSM_DSI_6G_VER_MINOR_V2_9_0	0x20090000
>  
>  #define MSM_DSI_V2_VER_MINOR_8064	0x0
>  
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 2218d4f0c5130a0b13f428e89aa30ba2921da572..ced28ee61eedc0a82da9f1d0792f17ee2a5538c4 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -119,6 +119,15 @@ struct msm_dsi_host {
>  	struct clk *pixel_clk;
>  	struct clk *byte_intf_clk;
>  
> +	/*
> +	 * Clocks which needs to be properly parented between DISPCC and DSI PHY
> +	 * PLL:
> +	 */
> +	struct clk *byte_src_clk;
> +	struct clk *pixel_src_clk;
> +	struct clk *dsi_pll_byte_clk;
> +	struct clk *dsi_pll_pixel_clk;
> +
>  	unsigned long byte_clk_rate;
>  	unsigned long byte_intf_clk_rate;
>  	unsigned long pixel_clk_rate;
> @@ -269,6 +278,38 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
>  	return ret;
>  }
>  
> +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host)
> +{
> +	struct device *dev = &msm_host->pdev->dev;
> +	int ret;
> +
> +	ret = dsi_clk_init_6g_v2(msm_host);
> +	if (ret)
> +		return ret;
> +
> +	msm_host->byte_src_clk = devm_clk_get(dev, "byte_src");
> +	if (IS_ERR(msm_host->byte_src_clk))
> +		return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk),
> +				     "can't get byte_src clock\n");
> +
> +	msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte");
> +	if (IS_ERR(msm_host->dsi_pll_byte_clk))
> +		return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk),
> +				     "can't get dsi_pll_byte clock\n");
> +
> +	msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src");
> +	if (IS_ERR(msm_host->pixel_src_clk))
> +		return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk),
> +				     "can't get pixel_src clock\n");
> +
> +	msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel");
> +	if (IS_ERR(msm_host->dsi_pll_pixel_clk))
> +		return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk),
> +				     "can't get dsi_pll_pixel clock\n");

How is this going to work in the bonded DSI mode when DSI1 is being fed
by the DSI0 PLL? For existing platforms this is being handled by
changing the parents in DT.

> +
> +	return 0;
> +}
> +
>  static int dsi_clk_init(struct msm_dsi_host *msm_host)
>  {
>  	struct platform_device *pdev = msm_host->pdev;
> @@ -370,6 +411,45 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
>  	return 0;
>  }
>  
> +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host)
> +{
> +	struct device *dev = &msm_host->pdev->dev;
> +	int ret;
> +
> +	/*
> +	 * DSI PHY PLLs have to be enabled to allow reparenting to them and
> +	 * setting the rates of pixel/byte clocks.
> +	 */
> +	ret = clk_prepare_enable(msm_host->dsi_pll_byte_clk);
> +	if (ret) {
> +		dev_err(dev, "Failed to enable dsi_pll_byte: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_prepare_enable(msm_host->dsi_pll_pixel_clk);
> +	if (ret) {
> +		dev_err(dev, "Failed to enable dsi_pll_byte: %d\n", ret);
> +		goto out_disable_byte_clk;
> +	}
> +
> +	ret = clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk);
> +	if (ret)
> +		dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret);
> +
> +	ret = clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_clk);
> +	if (ret)
> +		dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret);
> +
> +	ret = dsi_link_clk_set_rate_6g(msm_host);
> +
> +	clk_disable_unprepare(msm_host->dsi_pll_pixel_clk);
> +
> +out_disable_byte_clk:
> +	clk_disable_unprepare(msm_host->dsi_pll_byte_clk);
> +
> +	return ret;
> +}
> +
>  int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
>  {
>  	int ret;

-- 
With best wishes
Dmitry

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Krzysztof Kozlowski]

On 10/01/2025 00:18, Dmitry Baryshkov wrote:
> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
>> differences worth noting:
>>
>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>>    offsets were just switched.  Currently these registers are not used
>>    in the driver, so the easiest is to document both but keep them
>>    commented out to avoid conflict.
>>
>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>>    parents before they are prepared and initial rate is set.  Therefore
>>    assigned-clock-parents are not working here and driver is responsible
>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
> 
> Isn't it a description of CLK_SET_PARENT_GATE and/or

No - must be gated accross reparent - so opposite.

> CLK_OPS_PARENT_ENABLE ?

Yes, but does not work. Probably enabling parent, before
assigned-clocks-parents, happens still too early:

[    1.623554] DSI PLL(0) lock failed, status=0x00000000
[    1.623556] PLL(0) lock failed
[    1.624650] ------------[ cut here ]------------
[    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
configuration.

Or maybe something is missing in the DSI PHY PLL driver?

> 
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>>  drivers/gpu/drm/msm/dsi/dsi.h                      |  2 +
>>  drivers/gpu/drm/msm/dsi/dsi_cfg.c                  | 25 +++++++
>>  drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |  1 +
>>  drivers/gpu/drm/msm/dsi/dsi_host.c                 | 80 ++++++++++++++++++++++
>>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |  2 +
>>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |  1 +
>>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c          | 78 +++++++++++++++++++--
>>  .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml  | 14 ++++
> 
> Please separate DSI and PHY changes.
> 
>>  8 files changed, 197 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> index 7754dcec33d06e3d6eb8a9d55e53f24af073adb9..e2a8d6fcc45b6c207a3018ea7c8744fcf34dabd2 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>> @@ -205,6 +205,17 @@ static const struct msm_dsi_config sm8650_dsi_cfg = {
>>  	},
>>  };
>>  
>> +static const struct msm_dsi_config sm8750_dsi_cfg = {
>> +	.io_offset = DSI_6G_REG_SHIFT,
>> +	.regulator_data = sm8650_dsi_regulators,
>> +	.num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
>> +	.bus_clk_names = dsi_v2_4_clk_names,
>> +	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
>> +	.io_start = {
>> +		{ 0xae94000, 0xae96000 },
>> +	},
>> +};
>> +
>>  static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
>>  	{ .supply = "vdda", .init_load_uA = 8350 },	/* 1.2 V */
>>  	{ .supply = "refgen" },
>> @@ -257,6 +268,18 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
>>  	.calc_clk_rate = dsi_calc_clk_rate_6g,
>>  };
>>  
>> +static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops = {
>> +	.link_clk_set_rate = dsi_link_clk_set_rate_6g_v2_9,
>> +	.link_clk_enable = dsi_link_clk_enable_6g,
>> +	.link_clk_disable = dsi_link_clk_disable_6g,
>> +	.clk_init_ver = dsi_clk_init_6g_v2_9,
>> +	.tx_buf_alloc = dsi_tx_buf_alloc_6g,
>> +	.tx_buf_get = dsi_tx_buf_get_6g,
>> +	.tx_buf_put = dsi_tx_buf_put_6g,
>> +	.dma_base_get = dsi_dma_base_get_6g,
>> +	.calc_clk_rate = dsi_calc_clk_rate_6g,
>> +};
>> +
>>  static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>>  	{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
>>  		&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
>> @@ -300,6 +323,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>>  		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>>  	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
>>  		&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>> +	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0,
>> +		&sm8750_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
>>  };
>>  
>>  const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> index 120cb65164c1ba1deb9acb513e5f073bd560c496..859c279afbb0377d16f8406f3e6b083640aff5a1 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
>> @@ -30,6 +30,7 @@
>>  #define MSM_DSI_6G_VER_MINOR_V2_6_0	0x20060000
>>  #define MSM_DSI_6G_VER_MINOR_V2_7_0	0x20070000
>>  #define MSM_DSI_6G_VER_MINOR_V2_8_0	0x20080000
>> +#define MSM_DSI_6G_VER_MINOR_V2_9_0	0x20090000
>>  
>>  #define MSM_DSI_V2_VER_MINOR_8064	0x0
>>  
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index 2218d4f0c5130a0b13f428e89aa30ba2921da572..ced28ee61eedc0a82da9f1d0792f17ee2a5538c4 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -119,6 +119,15 @@ struct msm_dsi_host {
>>  	struct clk *pixel_clk;
>>  	struct clk *byte_intf_clk;
>>  
>> +	/*
>> +	 * Clocks which needs to be properly parented between DISPCC and DSI PHY
>> +	 * PLL:
>> +	 */
>> +	struct clk *byte_src_clk;
>> +	struct clk *pixel_src_clk;
>> +	struct clk *dsi_pll_byte_clk;
>> +	struct clk *dsi_pll_pixel_clk;
>> +
>>  	unsigned long byte_clk_rate;
>>  	unsigned long byte_intf_clk_rate;
>>  	unsigned long pixel_clk_rate;
>> @@ -269,6 +278,38 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
>>  	return ret;
>>  }
>>  
>> +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host)
>> +{
>> +	struct device *dev = &msm_host->pdev->dev;
>> +	int ret;
>> +
>> +	ret = dsi_clk_init_6g_v2(msm_host);
>> +	if (ret)
>> +		return ret;
>> +
>> +	msm_host->byte_src_clk = devm_clk_get(dev, "byte_src");
>> +	if (IS_ERR(msm_host->byte_src_clk))
>> +		return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk),
>> +				     "can't get byte_src clock\n");
>> +
>> +	msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte");
>> +	if (IS_ERR(msm_host->dsi_pll_byte_clk))
>> +		return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk),
>> +				     "can't get dsi_pll_byte clock\n");
>> +
>> +	msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src");
>> +	if (IS_ERR(msm_host->pixel_src_clk))
>> +		return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk),
>> +				     "can't get pixel_src clock\n");
>> +
>> +	msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel");
>> +	if (IS_ERR(msm_host->dsi_pll_pixel_clk))
>> +		return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk),
>> +				     "can't get dsi_pll_pixel clock\n");
> 
> How is this going to work in the bonded DSI mode when DSI1 is being fed
> by the DSI0 PLL? For existing platforms this is being handled by
> changing the parents in DT.

I don't see the problem - you just put different clock as input in DTS?

Please trim your replies, so we won't need to keep scrolling to figure
out that there is nothing more to read.

Best regards,
Krzysztof

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Dmitry Baryshkov]

On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
> > On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
> >> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
> >> differences worth noting:
> >>
> >> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
> >>    offsets were just switched.  Currently these registers are not used
> >>    in the driver, so the easiest is to document both but keep them
> >>    commented out to avoid conflict.
> >>
> >> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
> >>    parents before they are prepared and initial rate is set.  Therefore
> >>    assigned-clock-parents are not working here and driver is responsible
> >>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
> > 
> > Isn't it a description of CLK_SET_PARENT_GATE and/or
> 
> No - must be gated accross reparent - so opposite.
> 
> > CLK_OPS_PARENT_ENABLE ?
> 
> Yes, but does not work. Probably enabling parent, before
> assigned-clocks-parents, happens still too early:
> 
> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
> [    1.623556] PLL(0) lock failed
> [    1.624650] ------------[ cut here ]------------
> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
> configuration.
> 
> Or maybe something is missing in the DSI PHY PLL driver?

Do you have the no-zero-freq workaround?

> 
> > 
> >>
> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >> ---
> >>  drivers/gpu/drm/msm/dsi/dsi.h                      |  2 +
> >>  drivers/gpu/drm/msm/dsi/dsi_cfg.c                  | 25 +++++++
> >>  drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |  1 +
> >>  drivers/gpu/drm/msm/dsi/dsi_host.c                 | 80 ++++++++++++++++++++++
> >>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |  2 +
> >>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |  1 +
> >>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c          | 78 +++++++++++++++++++--
> >>  .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml  | 14 ++++
> > 
> > Please separate DSI and PHY changes.
> > 
> >>  8 files changed, 197 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> >> index 7754dcec33d06e3d6eb8a9d55e53f24af073adb9..e2a8d6fcc45b6c207a3018ea7c8744fcf34dabd2 100644
> >> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> >> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> >> @@ -205,6 +205,17 @@ static const struct msm_dsi_config sm8650_dsi_cfg = {
> >>  	},
> >>  };
> >>  
> >> +static const struct msm_dsi_config sm8750_dsi_cfg = {
> >> +	.io_offset = DSI_6G_REG_SHIFT,
> >> +	.regulator_data = sm8650_dsi_regulators,
> >> +	.num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
> >> +	.bus_clk_names = dsi_v2_4_clk_names,
> >> +	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
> >> +	.io_start = {
> >> +		{ 0xae94000, 0xae96000 },
> >> +	},
> >> +};
> >> +
> >>  static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
> >>  	{ .supply = "vdda", .init_load_uA = 8350 },	/* 1.2 V */
> >>  	{ .supply = "refgen" },
> >> @@ -257,6 +268,18 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
> >>  	.calc_clk_rate = dsi_calc_clk_rate_6g,
> >>  };
> >>  
> >> +static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops = {
> >> +	.link_clk_set_rate = dsi_link_clk_set_rate_6g_v2_9,
> >> +	.link_clk_enable = dsi_link_clk_enable_6g,
> >> +	.link_clk_disable = dsi_link_clk_disable_6g,
> >> +	.clk_init_ver = dsi_clk_init_6g_v2_9,
> >> +	.tx_buf_alloc = dsi_tx_buf_alloc_6g,
> >> +	.tx_buf_get = dsi_tx_buf_get_6g,
> >> +	.tx_buf_put = dsi_tx_buf_put_6g,
> >> +	.dma_base_get = dsi_dma_base_get_6g,
> >> +	.calc_clk_rate = dsi_calc_clk_rate_6g,
> >> +};
> >> +
> >>  static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
> >>  	{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
> >>  		&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
> >> @@ -300,6 +323,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
> >>  		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> >>  	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
> >>  		&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> >> +	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0,
> >> +		&sm8750_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
> >>  };
> >>  
> >>  const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
> >> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> >> index 120cb65164c1ba1deb9acb513e5f073bd560c496..859c279afbb0377d16f8406f3e6b083640aff5a1 100644
> >> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> >> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> >> @@ -30,6 +30,7 @@
> >>  #define MSM_DSI_6G_VER_MINOR_V2_6_0	0x20060000
> >>  #define MSM_DSI_6G_VER_MINOR_V2_7_0	0x20070000
> >>  #define MSM_DSI_6G_VER_MINOR_V2_8_0	0x20080000
> >> +#define MSM_DSI_6G_VER_MINOR_V2_9_0	0x20090000
> >>  
> >>  #define MSM_DSI_V2_VER_MINOR_8064	0x0
> >>  
> >> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> >> index 2218d4f0c5130a0b13f428e89aa30ba2921da572..ced28ee61eedc0a82da9f1d0792f17ee2a5538c4 100644
> >> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> >> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> >> @@ -119,6 +119,15 @@ struct msm_dsi_host {
> >>  	struct clk *pixel_clk;
> >>  	struct clk *byte_intf_clk;
> >>  
> >> +	/*
> >> +	 * Clocks which needs to be properly parented between DISPCC and DSI PHY
> >> +	 * PLL:
> >> +	 */
> >> +	struct clk *byte_src_clk;
> >> +	struct clk *pixel_src_clk;
> >> +	struct clk *dsi_pll_byte_clk;
> >> +	struct clk *dsi_pll_pixel_clk;
> >> +
> >>  	unsigned long byte_clk_rate;
> >>  	unsigned long byte_intf_clk_rate;
> >>  	unsigned long pixel_clk_rate;
> >> @@ -269,6 +278,38 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
> >>  	return ret;
> >>  }
> >>  
> >> +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host)
> >> +{
> >> +	struct device *dev = &msm_host->pdev->dev;
> >> +	int ret;
> >> +
> >> +	ret = dsi_clk_init_6g_v2(msm_host);
> >> +	if (ret)
> >> +		return ret;
> >> +
> >> +	msm_host->byte_src_clk = devm_clk_get(dev, "byte_src");
> >> +	if (IS_ERR(msm_host->byte_src_clk))
> >> +		return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk),
> >> +				     "can't get byte_src clock\n");
> >> +
> >> +	msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte");
> >> +	if (IS_ERR(msm_host->dsi_pll_byte_clk))
> >> +		return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk),
> >> +				     "can't get dsi_pll_byte clock\n");
> >> +
> >> +	msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src");
> >> +	if (IS_ERR(msm_host->pixel_src_clk))
> >> +		return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk),
> >> +				     "can't get pixel_src clock\n");
> >> +
> >> +	msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel");
> >> +	if (IS_ERR(msm_host->dsi_pll_pixel_clk))
> >> +		return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk),
> >> +				     "can't get dsi_pll_pixel clock\n");
> > 
> > How is this going to work in the bonded DSI mode when DSI1 is being fed
> > by the DSI0 PLL? For existing platforms this is being handled by
> > changing the parents in DT.
> 
> I don't see the problem - you just put different clock as input in DTS?
> 
> Please trim your replies, so we won't need to keep scrolling to figure
> out that there is nothing more to read.
> 
> Best regards,
> Krzysztof

-- 
With best wishes
Dmitry

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Krzysztof Kozlowski]

On 10/01/2025 10:17, Dmitry Baryshkov wrote:
> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
>>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
>>>> differences worth noting:
>>>>
>>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>>>>    offsets were just switched.  Currently these registers are not used
>>>>    in the driver, so the easiest is to document both but keep them
>>>>    commented out to avoid conflict.
>>>>
>>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>>>>    parents before they are prepared and initial rate is set.  Therefore
>>>>    assigned-clock-parents are not working here and driver is responsible
>>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
>>>
>>> Isn't it a description of CLK_SET_PARENT_GATE and/or
>>
>> No - must be gated accross reparent - so opposite.
>>
>>> CLK_OPS_PARENT_ENABLE ?
>>
>> Yes, but does not work. Probably enabling parent, before
>> assigned-clocks-parents, happens still too early:
>>
>> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
>> [    1.623556] PLL(0) lock failed
>> [    1.624650] ------------[ cut here ]------------
>> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
>> configuration.
>>
>> Or maybe something is missing in the DSI PHY PLL driver?
> 
> Do you have the no-zero-freq workaround?

Yes, it is necessary also for my variant. I did not include it here, but
I should mention it in the cover letter.

Best regards,
Krzysztof

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Dmitry Baryshkov]

On Fri, Jan 10, 2025 at 01:43:28PM +0100, Krzysztof Kozlowski wrote:
> On 10/01/2025 10:17, Dmitry Baryshkov wrote:
> > On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
> >> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
> >>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
> >>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
> >>>> differences worth noting:
> >>>>
> >>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
> >>>>    offsets were just switched.  Currently these registers are not used
> >>>>    in the driver, so the easiest is to document both but keep them
> >>>>    commented out to avoid conflict.
> >>>>
> >>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
> >>>>    parents before they are prepared and initial rate is set.  Therefore
> >>>>    assigned-clock-parents are not working here and driver is responsible
> >>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
> >>>
> >>> Isn't it a description of CLK_SET_PARENT_GATE and/or
> >>
> >> No - must be gated accross reparent - so opposite.
> >>
> >>> CLK_OPS_PARENT_ENABLE ?
> >>
> >> Yes, but does not work. Probably enabling parent, before
> >> assigned-clocks-parents, happens still too early:
> >>
> >> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
> >> [    1.623556] PLL(0) lock failed
> >> [    1.624650] ------------[ cut here ]------------
> >> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
> >> configuration.
> >>
> >> Or maybe something is missing in the DSI PHY PLL driver?
> > 
> > Do you have the no-zero-freq workaround?
> 
> Yes, it is necessary also for my variant. I did not include it here, but
> I should mention it in the cover letter.

Could you please possibly backtrace the corresponding enable() calls?
I'd let Stephen and/or Bjorn or Konrad to correct me, but I think that
such requirement should be handled by the framework instead of having
the drivers to manually reparent the clocks.

-- 
With best wishes
Dmitry

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Krzysztof Kozlowski]

On 13/01/2025 09:29, Dmitry Baryshkov wrote:
> On Fri, Jan 10, 2025 at 01:43:28PM +0100, Krzysztof Kozlowski wrote:
>> On 10/01/2025 10:17, Dmitry Baryshkov wrote:
>>> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
>>>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
>>>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
>>>>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
>>>>>> differences worth noting:
>>>>>>
>>>>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>>>>>>    offsets were just switched.  Currently these registers are not used
>>>>>>    in the driver, so the easiest is to document both but keep them
>>>>>>    commented out to avoid conflict.
>>>>>>
>>>>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>>>>>>    parents before they are prepared and initial rate is set.  Therefore
>>>>>>    assigned-clock-parents are not working here and driver is responsible
>>>>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
>>>>>
>>>>> Isn't it a description of CLK_SET_PARENT_GATE and/or
>>>>
>>>> No - must be gated accross reparent - so opposite.
>>>>
>>>>> CLK_OPS_PARENT_ENABLE ?
>>>>
>>>> Yes, but does not work. Probably enabling parent, before
>>>> assigned-clocks-parents, happens still too early:
>>>>
>>>> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
>>>> [    1.623556] PLL(0) lock failed
>>>> [    1.624650] ------------[ cut here ]------------
>>>> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
>>>> configuration.
>>>>
>>>> Or maybe something is missing in the DSI PHY PLL driver?
>>>
>>> Do you have the no-zero-freq workaround?
>>
>> Yes, it is necessary also for my variant. I did not include it here, but
>> I should mention it in the cover letter.
> 
> Could you please possibly backtrace the corresponding enable() calls?


It's the same backtrace I shared some time ago in internal discussions:
https://pastebin.com/kxUFgzD9
Unless you ask for some other backtrace?

> I'd let Stephen and/or Bjorn or Konrad to correct me, but I think that
> such requirement should be handled by the framework instead of having
> the drivers to manually reparent the clocks.

I don't know how exactly you would like to solve it. The clocks can be
reparented only after some other device specific enable sequence. It's
the third device here, but not reflected in the clocks hierarchy. Maybe
it's the result how entire Display device nodes were designed in the
first place?

Assigned clocks are between DSI PHY and DISP cc, but they are a property
of DSI controller. This looks exactly too specific for core to handle
and drivers, not framework, should manually reparent such clocks.
Otherwise we need
"clk_pre_prepare_callback_if_we_are_called_when_phy_is_disabled" sort of
callback.





Best regards,
Krzysztof

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Dmitry Baryshkov]

On Mon, Jan 13, 2025 at 12:02:54PM +0100, Krzysztof Kozlowski wrote:
> On 13/01/2025 09:29, Dmitry Baryshkov wrote:
> > On Fri, Jan 10, 2025 at 01:43:28PM +0100, Krzysztof Kozlowski wrote:
> >> On 10/01/2025 10:17, Dmitry Baryshkov wrote:
> >>> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
> >>>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
> >>>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
> >>>>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
> >>>>>> differences worth noting:
> >>>>>>
> >>>>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
> >>>>>>    offsets were just switched.  Currently these registers are not used
> >>>>>>    in the driver, so the easiest is to document both but keep them
> >>>>>>    commented out to avoid conflict.
> >>>>>>
> >>>>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
> >>>>>>    parents before they are prepared and initial rate is set.  Therefore
> >>>>>>    assigned-clock-parents are not working here and driver is responsible
> >>>>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
> >>>>>
> >>>>> Isn't it a description of CLK_SET_PARENT_GATE and/or
> >>>>
> >>>> No - must be gated accross reparent - so opposite.
> >>>>
> >>>>> CLK_OPS_PARENT_ENABLE ?
> >>>>
> >>>> Yes, but does not work. Probably enabling parent, before
> >>>> assigned-clocks-parents, happens still too early:
> >>>>
> >>>> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
> >>>> [    1.623556] PLL(0) lock failed
> >>>> [    1.624650] ------------[ cut here ]------------
> >>>> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
> >>>> configuration.
> >>>>
> >>>> Or maybe something is missing in the DSI PHY PLL driver?
> >>>
> >>> Do you have the no-zero-freq workaround?
> >>
> >> Yes, it is necessary also for my variant. I did not include it here, but
> >> I should mention it in the cover letter.
> > 
> > Could you please possibly backtrace the corresponding enable() calls?
> 
> 
> It's the same backtrace I shared some time ago in internal discussions:
> https://pastebin.com/kxUFgzD9
> Unless you ask for some other backtrace?
> 
> > I'd let Stephen and/or Bjorn or Konrad to correct me, but I think that
> > such requirement should be handled by the framework instead of having
> > the drivers to manually reparent the clocks.
> 
> I don't know how exactly you would like to solve it. The clocks can be
> reparented only after some other device specific enable sequence. It's
> the third device here, but not reflected in the clocks hierarchy. Maybe
> it's the result how entire Display device nodes were designed in the
> first place?
> 
> Assigned clocks are between DSI PHY and DISP cc, but they are a property
> of DSI controller. This looks exactly too specific for core to handle
> and drivers, not framework, should manually reparent such clocks.
> Otherwise we need
> "clk_pre_prepare_callback_if_we_are_called_when_phy_is_disabled" sort of
> callback.

What kind of PHY programming is required? Is enabling the PLL enough or
does it need anything else? Are the PLL supplies properly enabled at
this point?

-- 
With best wishes
Dmitry

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Krzysztof Kozlowski]

On 13/01/2025 13:13, Dmitry Baryshkov wrote:
> On Mon, Jan 13, 2025 at 12:02:54PM +0100, Krzysztof Kozlowski wrote:
>> On 13/01/2025 09:29, Dmitry Baryshkov wrote:
>>> On Fri, Jan 10, 2025 at 01:43:28PM +0100, Krzysztof Kozlowski wrote:
>>>> On 10/01/2025 10:17, Dmitry Baryshkov wrote:
>>>>> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
>>>>>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
>>>>>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
>>>>>>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
>>>>>>>> differences worth noting:
>>>>>>>>
>>>>>>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>>>>>>>>    offsets were just switched.  Currently these registers are not used
>>>>>>>>    in the driver, so the easiest is to document both but keep them
>>>>>>>>    commented out to avoid conflict.
>>>>>>>>
>>>>>>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>>>>>>>>    parents before they are prepared and initial rate is set.  Therefore
>>>>>>>>    assigned-clock-parents are not working here and driver is responsible
>>>>>>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
>>>>>>>
>>>>>>> Isn't it a description of CLK_SET_PARENT_GATE and/or
>>>>>>
>>>>>> No - must be gated accross reparent - so opposite.
>>>>>>
>>>>>>> CLK_OPS_PARENT_ENABLE ?
>>>>>>
>>>>>> Yes, but does not work. Probably enabling parent, before
>>>>>> assigned-clocks-parents, happens still too early:
>>>>>>
>>>>>> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
>>>>>> [    1.623556] PLL(0) lock failed
>>>>>> [    1.624650] ------------[ cut here ]------------
>>>>>> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
>>>>>> configuration.
>>>>>>
>>>>>> Or maybe something is missing in the DSI PHY PLL driver?
>>>>>
>>>>> Do you have the no-zero-freq workaround?
>>>>
>>>> Yes, it is necessary also for my variant. I did not include it here, but
>>>> I should mention it in the cover letter.
>>>
>>> Could you please possibly backtrace the corresponding enable() calls?
>>
>>
>> It's the same backtrace I shared some time ago in internal discussions:
>> https://pastebin.com/kxUFgzD9
>> Unless you ask for some other backtrace?
>>
>>> I'd let Stephen and/or Bjorn or Konrad to correct me, but I think that
>>> such requirement should be handled by the framework instead of having
>>> the drivers to manually reparent the clocks.
>>
>> I don't know how exactly you would like to solve it. The clocks can be
>> reparented only after some other device specific enable sequence. It's
>> the third device here, but not reflected in the clocks hierarchy. Maybe
>> it's the result how entire Display device nodes were designed in the
>> first place?
>>
>> Assigned clocks are between DSI PHY and DISP cc, but they are a property
>> of DSI controller. This looks exactly too specific for core to handle
>> and drivers, not framework, should manually reparent such clocks.
>> Otherwise we need
>> "clk_pre_prepare_callback_if_we_are_called_when_phy_is_disabled" sort of
>> callback.
> 
> What kind of PHY programming is required? Is enabling the PLL enough or
> does it need anything else? Are the PLL supplies properly enabled at
> this point?
> 

I don't know exactly and checking is tricky. I tried to use
CLK_OPS_PARENT_ENABLE - with equivalent code, setting proper parents but
without enabling the DSI PHY PLL manually just with
CLK_OPS_PARENT_ENABLE - but then you have multiple:

dsi0_pll_bit_clk: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set

So how do you supposed to test it? Any assigned-clocks-xxx will be way
too early. Moving code around? Well, if I move preparing the DSI PLL
clocks out of dsi_link_clk_set_rate_6g, then dsi_link_clk_set_rate_6g()
will fail. Always and CLK_OPS_PARENT_ENABLE does not help because of above.

If you have specific code in mind, I can try it, but I don't see easy
methods to see what has to be enabled exactly because of how everything
is entangled together.

Best regards,
Krzysztof

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Dmitry Baryshkov]

On Thu, Jan 23, 2025 at 12:34:28PM +0100, Krzysztof Kozlowski wrote:
> On 13/01/2025 13:13, Dmitry Baryshkov wrote:
> > On Mon, Jan 13, 2025 at 12:02:54PM +0100, Krzysztof Kozlowski wrote:
> >> On 13/01/2025 09:29, Dmitry Baryshkov wrote:
> >>> On Fri, Jan 10, 2025 at 01:43:28PM +0100, Krzysztof Kozlowski wrote:
> >>>> On 10/01/2025 10:17, Dmitry Baryshkov wrote:
> >>>>> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
> >>>>>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
> >>>>>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
> >>>>>>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
> >>>>>>>> differences worth noting:
> >>>>>>>>
> >>>>>>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
> >>>>>>>>    offsets were just switched.  Currently these registers are not used
> >>>>>>>>    in the driver, so the easiest is to document both but keep them
> >>>>>>>>    commented out to avoid conflict.
> >>>>>>>>
> >>>>>>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
> >>>>>>>>    parents before they are prepared and initial rate is set.  Therefore
> >>>>>>>>    assigned-clock-parents are not working here and driver is responsible
> >>>>>>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
> >>>>>>>
> >>>>>>> Isn't it a description of CLK_SET_PARENT_GATE and/or
> >>>>>>
> >>>>>> No - must be gated accross reparent - so opposite.
> >>>>>>
> >>>>>>> CLK_OPS_PARENT_ENABLE ?
> >>>>>>
> >>>>>> Yes, but does not work. Probably enabling parent, before
> >>>>>> assigned-clocks-parents, happens still too early:
> >>>>>>
> >>>>>> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
> >>>>>> [    1.623556] PLL(0) lock failed
> >>>>>> [    1.624650] ------------[ cut here ]------------
> >>>>>> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
> >>>>>> configuration.
> >>>>>>
> >>>>>> Or maybe something is missing in the DSI PHY PLL driver?
> >>>>>
> >>>>> Do you have the no-zero-freq workaround?
> >>>>
> >>>> Yes, it is necessary also for my variant. I did not include it here, but
> >>>> I should mention it in the cover letter.
> >>>
> >>> Could you please possibly backtrace the corresponding enable() calls?
> >>
> >>
> >> It's the same backtrace I shared some time ago in internal discussions:
> >> https://pastebin.com/kxUFgzD9
> >> Unless you ask for some other backtrace?
> >>
> >>> I'd let Stephen and/or Bjorn or Konrad to correct me, but I think that
> >>> such requirement should be handled by the framework instead of having
> >>> the drivers to manually reparent the clocks.
> >>
> >> I don't know how exactly you would like to solve it. The clocks can be
> >> reparented only after some other device specific enable sequence. It's
> >> the third device here, but not reflected in the clocks hierarchy. Maybe
> >> it's the result how entire Display device nodes were designed in the
> >> first place?
> >>
> >> Assigned clocks are between DSI PHY and DISP cc, but they are a property
> >> of DSI controller. This looks exactly too specific for core to handle
> >> and drivers, not framework, should manually reparent such clocks.
> >> Otherwise we need
> >> "clk_pre_prepare_callback_if_we_are_called_when_phy_is_disabled" sort of
> >> callback.
> > 
> > What kind of PHY programming is required? Is enabling the PLL enough or
> > does it need anything else? Are the PLL supplies properly enabled at
> > this point?
> > 
> 
> I don't know exactly and checking is tricky. I tried to use
> CLK_OPS_PARENT_ENABLE - with equivalent code, setting proper parents but
> without enabling the DSI PHY PLL manually just with
> CLK_OPS_PARENT_ENABLE - but then you have multiple:
> 
> dsi0_pll_bit_clk: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set

This really looks as if a part of the DSI PHY is unpowered. If you are
sure about your DSI and DSI PHY supplies (and power domains) then I also
have no other ideas.

Abhinav? Any input from your side? Or from Taniya Das?

> 
> So how do you supposed to test it? Any assigned-clocks-xxx will be way
> too early. Moving code around? Well, if I move preparing the DSI PLL
> clocks out of dsi_link_clk_set_rate_6g, then dsi_link_clk_set_rate_6g()
> will fail. Always and CLK_OPS_PARENT_ENABLE does not help because of above.
> 
> If you have specific code in mind, I can try it, but I don't see easy
> methods to see what has to be enabled exactly because of how everything
> is entangled together.
> 
> Best regards,
> Krzysztof

-- 
With best wishes
Dmitry

Re: [PATCH RFC 08/11] drm/msm/dsi: Add support for SM8750

[Krzysztof Kozlowski]

On 23/01/2025 12:42, Dmitry Baryshkov wrote:
> On Thu, Jan 23, 2025 at 12:34:28PM +0100, Krzysztof Kozlowski wrote:
>> On 13/01/2025 13:13, Dmitry Baryshkov wrote:
>>> On Mon, Jan 13, 2025 at 12:02:54PM +0100, Krzysztof Kozlowski wrote:
>>>> On 13/01/2025 09:29, Dmitry Baryshkov wrote:
>>>>> On Fri, Jan 10, 2025 at 01:43:28PM +0100, Krzysztof Kozlowski wrote:
>>>>>> On 10/01/2025 10:17, Dmitry Baryshkov wrote:
>>>>>>> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
>>>>>>>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
>>>>>>>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
>>>>>>>>>> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
>>>>>>>>>> differences worth noting:
>>>>>>>>>>
>>>>>>>>>> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>>>>>>>>>>    offsets were just switched.  Currently these registers are not used
>>>>>>>>>>    in the driver, so the easiest is to document both but keep them
>>>>>>>>>>    commented out to avoid conflict.
>>>>>>>>>>
>>>>>>>>>> 2. DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>>>>>>>>>>    parents before they are prepared and initial rate is set.  Therefore
>>>>>>>>>>    assigned-clock-parents are not working here and driver is responsible
>>>>>>>>>>    for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9().
>>>>>>>>>
>>>>>>>>> Isn't it a description of CLK_SET_PARENT_GATE and/or
>>>>>>>>
>>>>>>>> No - must be gated accross reparent - so opposite.
>>>>>>>>
>>>>>>>>> CLK_OPS_PARENT_ENABLE ?
>>>>>>>>
>>>>>>>> Yes, but does not work. Probably enabling parent, before
>>>>>>>> assigned-clocks-parents, happens still too early:
>>>>>>>>
>>>>>>>> [    1.623554] DSI PLL(0) lock failed, status=0x00000000
>>>>>>>> [    1.623556] PLL(0) lock failed
>>>>>>>> [    1.624650] ------------[ cut here ]------------
>>>>>>>> [    1.624651] disp_cc_mdss_byte0_clk_src: rcg didn't update its
>>>>>>>> configuration.
>>>>>>>>
>>>>>>>> Or maybe something is missing in the DSI PHY PLL driver?
>>>>>>>
>>>>>>> Do you have the no-zero-freq workaround?
>>>>>>
>>>>>> Yes, it is necessary also for my variant. I did not include it here, but
>>>>>> I should mention it in the cover letter.
>>>>>
>>>>> Could you please possibly backtrace the corresponding enable() calls?
>>>>
>>>>
>>>> It's the same backtrace I shared some time ago in internal discussions:
>>>> https://pastebin.com/kxUFgzD9
>>>> Unless you ask for some other backtrace?
>>>>
>>>>> I'd let Stephen and/or Bjorn or Konrad to correct me, but I think that
>>>>> such requirement should be handled by the framework instead of having
>>>>> the drivers to manually reparent the clocks.
>>>>
>>>> I don't know how exactly you would like to solve it. The clocks can be
>>>> reparented only after some other device specific enable sequence. It's
>>>> the third device here, but not reflected in the clocks hierarchy. Maybe
>>>> it's the result how entire Display device nodes were designed in the
>>>> first place?
>>>>
>>>> Assigned clocks are between DSI PHY and DISP cc, but they are a property
>>>> of DSI controller. This looks exactly too specific for core to handle
>>>> and drivers, not framework, should manually reparent such clocks.
>>>> Otherwise we need
>>>> "clk_pre_prepare_callback_if_we_are_called_when_phy_is_disabled" sort of
>>>> callback.
>>>
>>> What kind of PHY programming is required? Is enabling the PLL enough or
>>> does it need anything else? Are the PLL supplies properly enabled at
>>> this point?
>>>
>>
>> I don't know exactly and checking is tricky. I tried to use
>> CLK_OPS_PARENT_ENABLE - with equivalent code, setting proper parents but
>> without enabling the DSI PHY PLL manually just with
>> CLK_OPS_PARENT_ENABLE - but then you have multiple:
>>
>> dsi0_pll_bit_clk: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> 
> This really looks as if a part of the DSI PHY is unpowered. If you are
> sure about your DSI and DSI PHY supplies (and power domains) then I also
> have no other ideas.

Yes, I triple checked them with downstream and with schematics.

The rate setting - which is being discussed/fixed here - is in:
msm_dsi_host_power_on()
which does:

    regulator_bulk_enable()
    pm_runtime_get_sync(&msm_host->pdev->dev);
    ret = cfg_hnd->ops->link_clk_set_rate(msm_host);


If I refactor this code into:

    regulator_bulk_enable()
    pm_runtime_get_sync(&msm_host->pdev->dev);
    MY_NEW_PREPARE_REPARENT_UNPREPARE()
    ret = cfg_hnd->ops->link_clk_set_rate(msm_host);

and use CLK_OPS_PARENT_ENABLE, I still got mentioned errors with calltrace:

dev_pm_opp_set_rate (drivers/opp/core.c:1357)
    ^^^^^^^^ line numbers won't help you, so explaining:
             this is exactly in dsi_link_clk_set_rate_6g
dsi_link_clk_set_rate_6g (drivers/gpu/drm/msm/dsi/dsi_host.c:391)
msm_dsi_host_power_on (drivers/gpu/drm/msm/dsi/dsi_host.c:2520)

This is actually weird, because PHY is powered in this case. I would
consider CLK_OPS_PARENT_ENABLE() to be equal to my clk_prepare_enable
from this patch, but somehow it is not equivalent.

> 
> Abhinav? Any input from your side? Or from Taniya Das?
> 
>>
Best regards,
Krzysztof

[PATCH RFC 09/11] drm/msm/dpu: Add support for SM8750

[Krzysztof Kozlowski]

Add DPU version v12.0 support for the Qualcomm SM8750 platform.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h    | 522 +++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  35 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         |   6 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   6 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
 6 files changed, 564 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
new file mode 100644
index 0000000000000000000000000000000000000000..b093f6e529f6d5f4a4b600d766cefb509619a3c1
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
@@ -0,0 +1,522 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Linaro Limited
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_12_0_SM8750_H
+#define _DPU_12_0_SM8750_H
+
+static const struct dpu_caps sm8750_dpu_caps = {
+	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+	.max_mixer_blendstages = 0xb,
+	.has_src_split = true,
+	.has_dim_layer = true,
+	.has_idle_pc = true,
+	.has_3d_merge = true,
+	.max_linewidth = 8192,
+	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sm8750_mdp = {
+	.name = "top_0",
+	.base = 0, .len = 0x494,
+	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+	.clk_ctrls = {
+		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+	},
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
+static const struct dpu_ctl_cfg sm8750_ctl[] = {
+	{
+		.name = "ctl_0", .id = CTL_0,
+		.base = 0x15000, .len = 0x1000,
+		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+	}, {
+		.name = "ctl_1", .id = CTL_1,
+		.base = 0x16000, .len = 0x1000,
+		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+	}, {
+		.name = "ctl_2", .id = CTL_2,
+		.base = 0x17000, .len = 0x1000,
+		.features = CTL_SM8550_MASK,
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+	}, {
+		.name = "ctl_3", .id = CTL_3,
+		.base = 0x18000, .len = 0x1000,
+		.features = CTL_SM8550_MASK,
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+	}, {
+		.name = "ctl_4", .id = CTL_4,
+		.base = 0x19000, .len = 0x1000,
+		.features = CTL_SM8550_MASK,
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+	}, {
+		.name = "ctl_5", .id = CTL_5,
+		.base = 0x1a000, .len = 0x1000,
+		.features = CTL_SM8550_MASK,
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+	},
+};
+
+static const struct dpu_sspp_cfg sm8750_sspp[] = {
+	{
+		.name = "sspp_0", .id = SSPP_VIG0,
+		.base = 0x4000, .len = 0x344,
+		.features = VIG_SDM845_MASK_SDMA,
+		.sblk = &dpu_vig_sblk_qseed3_3_4,
+		.xin_id = 0,
+		.type = SSPP_TYPE_VIG,
+	}, {
+		.name = "sspp_1", .id = SSPP_VIG1,
+		.base = 0x6000, .len = 0x344,
+		.features = VIG_SDM845_MASK_SDMA,
+		.sblk = &dpu_vig_sblk_qseed3_3_4,
+		.xin_id = 4,
+		.type = SSPP_TYPE_VIG,
+	}, {
+		.name = "sspp_2", .id = SSPP_VIG2,
+		.base = 0x8000, .len = 0x344,
+		.features = VIG_SDM845_MASK_SDMA,
+		.sblk = &dpu_vig_sblk_qseed3_3_4,
+		.xin_id = 8,
+		.type = SSPP_TYPE_VIG,
+	}, {
+		.name = "sspp_3", .id = SSPP_VIG3,
+		.base = 0xa000, .len = 0x344,
+		.features = VIG_SDM845_MASK_SDMA,
+		.sblk = &dpu_vig_sblk_qseed3_3_4,
+		.xin_id = 12,
+		.type = SSPP_TYPE_VIG,
+	}, {
+		/* TODO: Indices/code for SSPP_VIG4 overlaps with SSPP_RGB0 */
+		.name = "sspp_8", .id = SSPP_DMA0,
+		.base = 0x24000, .len = 0x344,
+		.features = DMA_SDM845_MASK_SDMA,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 1,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_9", .id = SSPP_DMA1,
+		.base = 0x26000, .len = 0x344,
+		.features = DMA_SDM845_MASK_SDMA,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 5,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_10", .id = SSPP_DMA2,
+		.base = 0x28000, .len = 0x344,
+		.features = DMA_SDM845_MASK_SDMA,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 9,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_11", .id = SSPP_DMA3,
+		.base = 0x2a000, .len = 0x344,
+		.features = DMA_SDM845_MASK_SDMA,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 13,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_12", .id = SSPP_DMA4,
+		.base = 0x2c000, .len = 0x344,
+		.features = DMA_CURSOR_SDM845_MASK_SDMA,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 14,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_13", .id = SSPP_DMA5,
+		.base = 0x2e000, .len = 0x344,
+		.features = DMA_CURSOR_SDM845_MASK_SDMA,
+		.sblk = &dpu_dma_sblk,
+		.xin_id = 15,
+		.type = SSPP_TYPE_DMA,
+	},
+};
+
+static const struct dpu_lm_cfg sm8750_lm[] = {
+	{
+		.name = "lm_0", .id = LM_0,
+		.base = 0x44000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sm8750_lm_sblk,
+		.lm_pair = LM_1,
+		.pingpong = PINGPONG_0,
+		.dspp = DSPP_0,
+	}, {
+		.name = "lm_1", .id = LM_1,
+		.base = 0x45000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sm8750_lm_sblk,
+		.lm_pair = LM_0,
+		.pingpong = PINGPONG_1,
+		.dspp = DSPP_1,
+	}, {
+		.name = "lm_2", .id = LM_2,
+		.base = 0x46000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sm8750_lm_sblk,
+		.lm_pair = LM_3,
+		.pingpong = PINGPONG_2,
+		.dspp = DSPP_2,
+	}, {
+		.name = "lm_3", .id = LM_3,
+		.base = 0x47000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sm8750_lm_sblk,
+		.lm_pair = LM_2,
+		.pingpong = PINGPONG_3,
+		.dspp = DSPP_3,
+	}, {
+		.name = "lm_4", .id = LM_4,
+		.base = 0x48000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sm8750_lm_sblk,
+		.lm_pair = LM_5,
+		.pingpong = PINGPONG_4,
+	}, {
+		.name = "lm_5", .id = LM_5,
+		.base = 0x49000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sm8750_lm_sblk,
+		.lm_pair = LM_4,
+		.pingpong = PINGPONG_5,
+	}, {
+		.name = "lm_6", .id = LM_6,
+		.base = 0x4a000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sm8750_lm_sblk,
+		.lm_pair = LM_7,
+		.pingpong = PINGPONG_6,
+	}, {
+		.name = "lm_7", .id = LM_7,
+		.base = 0x4b000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sm8750_lm_sblk,
+		.lm_pair = LM_6,
+		.pingpong = PINGPONG_7,
+	},
+};
+
+static const struct dpu_dspp_cfg sm8750_dspp[] = {
+	{
+		.name = "dspp_0", .id = DSPP_0,
+		.base = 0x54000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sm8750_dspp_sblk,
+	}, {
+		.name = "dspp_1", .id = DSPP_1,
+		.base = 0x56000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sm8750_dspp_sblk,
+	}, {
+		.name = "dspp_2", .id = DSPP_2,
+		.base = 0x58000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sm8750_dspp_sblk,
+	}, {
+		.name = "dspp_3", .id = DSPP_3,
+		.base = 0x5a000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sm8750_dspp_sblk,
+	},
+};
+
+static const struct dpu_pingpong_cfg sm8750_pp[] = {
+	{
+		.name = "pingpong_0", .id = PINGPONG_0,
+		.base = 0x69000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_0,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+	}, {
+		.name = "pingpong_1", .id = PINGPONG_1,
+		.base = 0x6a000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_0,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+	}, {
+		.name = "pingpong_2", .id = PINGPONG_2,
+		.base = 0x6b000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_1,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+	}, {
+		.name = "pingpong_3", .id = PINGPONG_3,
+		.base = 0x6c000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_1,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+	}, {
+		.name = "pingpong_4", .id = PINGPONG_4,
+		.base = 0x6d000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_2,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+	}, {
+		.name = "pingpong_5", .id = PINGPONG_5,
+		.base = 0x6e000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_2,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+	}, {
+		.name = "pingpong_6", .id = PINGPONG_6,
+		.base = 0x6f000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_3,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
+	}, {
+		.name = "pingpong_7", .id = PINGPONG_7,
+		.base = 0x70000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_3,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
+	}, {
+		.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
+		.base = 0x66000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_4,
+	}, {
+		.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
+		.base = 0x66400, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_4,
+	}, {
+		.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
+		.base = 0x7e000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_5,
+	}, {
+		.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
+		.base = 0x7e400, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_5,
+	},
+};
+
+static const struct dpu_merge_3d_cfg sm8750_merge_3d[] = {
+	{
+		.name = "merge_3d_0", .id = MERGE_3D_0,
+		.base = 0x4e000, .len = 0x1c,
+	}, {
+		.name = "merge_3d_1", .id = MERGE_3D_1,
+		.base = 0x4f000, .len = 0x1c,
+	}, {
+		.name = "merge_3d_2", .id = MERGE_3D_2,
+		.base = 0x50000, .len = 0x1c,
+	}, {
+		.name = "merge_3d_3", .id = MERGE_3D_3,
+		.base = 0x51000, .len = 0x1c,
+	}, {
+		.name = "merge_3d_4", .id = MERGE_3D_4,
+		.base = 0x66700, .len = 0x1c,
+	}, {
+		.name = "merge_3d_5", .id = MERGE_3D_5,
+		.base = 0x7e700, .len = 0x1c,
+	},
+};
+
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
+ * slice DSC encoders so both share same base address but with
+ * its own different sub block address.
+ */
+static const struct dpu_dsc_cfg sm8750_dsc[] = {
+	{
+		.name = "dce_0_0", .id = DSC_0,
+		.base = 0x80000, .len = 0x8,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &sm8750_dsc_sblk_0,
+	}, {
+		.name = "dce_0_1", .id = DSC_1,
+		.base = 0x80000, .len = 0x8,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &sm8750_dsc_sblk_1,
+	}, {
+		.name = "dce_1_0", .id = DSC_2,
+		.base = 0x81000, .len = 0x8,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &sm8750_dsc_sblk_0,
+	}, {
+		.name = "dce_1_1", .id = DSC_3,
+		.base = 0x81000, .len = 0x8,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &sm8750_dsc_sblk_1,
+	}, {
+		.name = "dce_2_0", .id = DSC_4,
+		.base = 0x82000, .len = 0x8,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &sm8750_dsc_sblk_0,
+	}, {
+		.name = "dce_2_1", .id = DSC_5,
+		.base = 0x82000, .len = 0x8,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &sm8750_dsc_sblk_1,
+	}, {
+		.name = "dce_3_0", .id = DSC_6,
+		.base = 0x83000, .len = 0x8,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &sm8750_dsc_sblk_0,
+	}, {
+		.name = "dce_3_1", .id = DSC_7,
+		.base = 0x83000, .len = 0x8,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &sm8750_dsc_sblk_1,
+	},
+};
+
+static const struct dpu_wb_cfg sm8750_wb[] = {
+	{
+		.name = "wb_2", .id = WB_2,
+		.base = 0x65000, .len = 0x2c8,
+		.features = WB_SM8250_MASK,
+		.format_list = wb2_formats_rgb,
+		.num_formats = ARRAY_SIZE(wb2_formats_rgb),
+		.xin_id = 6,
+		.vbif_idx = VBIF_RT,
+		.maxlinewidth = 4096,
+		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+	},
+};
+
+static const struct dpu_cwb_cfg sm8750_cwb[] = {
+	{
+		.name = "cwb_0", .id = CWB_0,
+		.base = 0x66200, .len = 0x20,
+	},
+	{
+		.name = "cwb_1", .id = CWB_1,
+		.base = 0x66600, .len = 0x20,
+	},
+	{
+		.name = "cwb_2", .id = CWB_2,
+		.base = 0x7e200, .len = 0x20,
+	},
+	{
+		.name = "cwb_3", .id = CWB_3,
+		.base = 0x7e600, .len = 0x20,
+	},
+};
+
+static const struct dpu_intf_cfg sm8750_intf[] = {
+	{
+		.name = "intf_0", .id = INTF_0,
+		.base = 0x34000, .len = 0x4bc,
+		.features = INTF_SC7280_MASK,
+		.type = INTF_DP,
+		.controller_id = MSM_DP_CONTROLLER_0,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+	}, {
+		.name = "intf_1", .id = INTF_1,
+		.base = 0x35000, .len = 0x4bc,
+		.features = INTF_SC7280_MASK,
+		.type = INTF_DSI,
+		.controller_id = MSM_DSI_CONTROLLER_0,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+	}, {
+		.name = "intf_2", .id = INTF_2,
+		.base = 0x36000, .len = 0x4bc,
+		.features = INTF_SC7280_MASK,
+		.type = INTF_DSI,
+		.controller_id = MSM_DSI_CONTROLLER_1,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
+	}, {
+		.name = "intf_3", .id = INTF_3,
+		.base = 0x37000, .len = 0x4bc,
+		.features = INTF_SC7280_MASK,
+		.type = INTF_DP,
+		.controller_id = MSM_DP_CONTROLLER_1,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+	},
+};
+
+static const struct dpu_perf_cfg sm8750_perf_data = {
+	.max_bw_low = 18900000,
+	.max_bw_high = 28500000,
+	.min_core_ib = 2500000,
+	.min_llcc_ib = 0,
+	.min_dram_ib = 800000,
+	.min_prefill_lines = 35,
+	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
+	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
+	.qos_lut_tbl = {
+		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
+		.entries = sc7180_qos_linear
+		},
+		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+		.entries = sc7180_qos_macrotile
+		},
+		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+		.entries = sc7180_qos_nrt
+		},
+		/* TODO: macrotile-qseed is different from macrotile */
+	},
+	.cdp_cfg = {
+		{.rd_enable = 1, .wr_enable = 1},
+		{.rd_enable = 1, .wr_enable = 0}
+	},
+	.clk_inefficiency_factor = 105,
+	.bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version sm8750_mdss_ver = {
+	.core_major_ver = 12,
+	.core_minor_ver = 0,
+};
+
+const struct dpu_mdss_cfg dpu_sm8750_cfg = {
+	.mdss_ver = &sm8750_mdss_ver,
+	.caps = &sm8750_dpu_caps,
+	.mdp = &sm8750_mdp,
+	.ctl_count = ARRAY_SIZE(sm8750_ctl),
+	.ctl = sm8750_ctl,
+	.sspp_count = ARRAY_SIZE(sm8750_sspp),
+	.sspp = sm8750_sspp,
+	.mixer_count = ARRAY_SIZE(sm8750_lm),
+	.mixer = sm8750_lm,
+	.dspp_count = ARRAY_SIZE(sm8750_dspp),
+	.dspp = sm8750_dspp,
+	.pingpong_count = ARRAY_SIZE(sm8750_pp),
+	.pingpong = sm8750_pp,
+	.dsc_count = ARRAY_SIZE(sm8750_dsc),
+	.dsc = sm8750_dsc,
+	.merge_3d_count = ARRAY_SIZE(sm8750_merge_3d),
+	.merge_3d = sm8750_merge_3d,
+	.wb_count = ARRAY_SIZE(sm8750_wb),
+	.wb = sm8750_wb,
+	.cwb_count = ARRAY_SIZE(sm8750_cwb),
+	.cwb = sm8650_cwb,
+	.intf_count = ARRAY_SIZE(sm8750_intf),
+	.intf = sm8750_intf,
+	.vbif_count = ARRAY_SIZE(sm8650_vbif),
+	.vbif = sm8650_vbif,
+	.perf = &sm8750_perf_data,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 0b342c043875f3329a9f71c5e751b2244f9f5ef7..40966ab6283e666d1f113a62ada50298de68833b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -399,6 +399,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 =
 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =
 				_VIG_SBLK(SSPP_SCALER_VER(3, 3));
 
+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =
+				_VIG_SBLK(SSPP_SCALER_VER(3, 4));
+
 static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK();
 
 static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
@@ -407,8 +410,6 @@ static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
  * MIXER sub blocks config
  *************************************************************/
 
-/* MSM8998 */
-
 static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 	.maxblendstages = 7, /* excluding base layer */
@@ -418,8 +419,6 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
 	},
 };
 
-/* SDM845 */
-
 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 	.maxblendstages = 11, /* excluding base layer */
@@ -429,8 +428,6 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
 	},
 };
 
-/* SC7180 */
-
 static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 	.maxblendstages = 7, /* excluding base layer */
@@ -439,7 +436,15 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
 	},
 };
 
-/* QCM2290 */
+static const struct dpu_lm_sub_blks sm8750_lm_sblk = {
+	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+	.maxblendstages = 11, /* excluding base layer */
+	.blendstage_base = { /* offsets relative to mixer base */
+		/* 0x40 + n*0x30 */
+		0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0,
+		0x1f0, 0x220
+	},
+};
 
 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
 	.maxwidth = DEFAULT_DPU_LINE_WIDTH,
@@ -462,6 +467,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
 		.len = 0x90, .version = 0x40000},
 };
 
+static const struct dpu_dspp_sub_blks sm8750_dspp_sblk = {
+	.pcc = {.name = "pcc", .base = 0x1700,
+		.len = 0x90, .version = 0x60000},
+};
+
 /*************************************************************
  * PINGPONG sub blocks config
  *************************************************************/
@@ -504,6 +514,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
 	.ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
 };
 
+static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 = {
+	.enc = {.name = "enc", .base = 0x100, .len = 0x100},
+	.ctl = {.name = "ctl", .base = 0xF00, .len = 0x24},
+};
+
+static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 = {
+	.enc = {.name = "enc", .base = 0x200, .len = 0x100},
+	.ctl = {.name = "ctl", .base = 0xF80, .len = 0x24},
+};
+
 /*************************************************************
  * CDM block config
  *************************************************************/
@@ -787,3 +807,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
 #include "catalog/dpu_9_2_x1e80100.h"
 
 #include "catalog/dpu_10_0_sm8650.h"
+#include "catalog/dpu_12_0_sm8750.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4cea19e1a20380c56ae014f2d33a6884a72e0ca0..1bd313f2c6f199d5eefcdaa5f7c18ea512d48684 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -863,6 +863,7 @@ extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
 extern const struct dpu_mdss_cfg dpu_sa8775p_cfg;
 extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
 extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
+extern const struct dpu_mdss_cfg dpu_sm8750_cfg;
 extern const struct dpu_mdss_cfg dpu_x1e80100_cfg;
 
 #endif /* _DPU_HW_CATALOG_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 4893f10d6a5832521808c0f4d8b231c356dbdc41..06b01cd36ce2442ee6e1b85be227851a234cc96b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -254,6 +254,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx,
 	case LM_5:
 		ctx->pending_flush_mask |= BIT(20);
 		break;
+	case LM_6:
+		ctx->pending_flush_mask |= BIT(21);
+		break;
+	case LM_7:
+		ctx->pending_flush_mask |= BIT(27);
+		break;
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index ba7bb05efe9b8cac01a908e53121117e130f91ec..440a327c64eb83a944289c6ce9ef9a5bfacc25f3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -123,6 +123,7 @@ enum dpu_lm {
 	LM_4,
 	LM_5,
 	LM_6,
+	LM_7,
 	LM_MAX
 };
 
@@ -167,6 +168,8 @@ enum dpu_dsc {
 	DSC_3,
 	DSC_4,
 	DSC_5,
+	DSC_6,
+	DSC_7,
 	DSC_MAX
 };
 
@@ -183,6 +186,8 @@ enum dpu_pingpong {
 	PINGPONG_3,
 	PINGPONG_4,
 	PINGPONG_5,
+	PINGPONG_6,
+	PINGPONG_7,
 	PINGPONG_CWB_0,
 	PINGPONG_CWB_1,
 	PINGPONG_CWB_2,
@@ -197,6 +202,7 @@ enum dpu_merge_3d {
 	MERGE_3D_2,
 	MERGE_3D_3,
 	MERGE_3D_4,
+	MERGE_3D_5,
 	MERGE_3D_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 97e9cb8c2b099f4757169cadf7e941148d2bfb16..ac131a01dc2bd99a2a54986ae1e3f7c324c9da50 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1515,6 +1515,7 @@ static const struct of_device_id dpu_dt_match[] = {
 	{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
 	{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
 	{ .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
+	{ .compatible = "qcom,sm8750-dpu", .data = &dpu_sm8750_cfg, },
 	{ .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
 	{}
 };

-- 
2.43.0

Re: [PATCH RFC 09/11] drm/msm/dpu: Add support for SM8750

[Dmitry Baryshkov]

On Thu, Jan 09, 2025 at 02:08:36PM +0100, Krzysztof Kozlowski wrote:
> Add DPU version v12.0 support for the Qualcomm SM8750 platform.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h    | 522 +++++++++++++++++++++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  35 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         |   6 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   6 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>  6 files changed, 564 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..b093f6e529f6d5f4a4b600d766cefb509619a3c1
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
> @@ -0,0 +1,522 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 Linaro Limited
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DPU_12_0_SM8750_H
> +#define _DPU_12_0_SM8750_H
> +
> +static const struct dpu_caps sm8750_dpu_caps = {
> +	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> +	.max_mixer_blendstages = 0xb,
> +	.has_src_split = true,
> +	.has_dim_layer = true,
> +	.has_idle_pc = true,
> +	.has_3d_merge = true,
> +	.max_linewidth = 8192,
> +	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_mdp_cfg sm8750_mdp = {
> +	.name = "top_0",
> +	.base = 0, .len = 0x494,
> +	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> +	.clk_ctrls = {
> +		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> +	},
> +};
> +
> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> +static const struct dpu_ctl_cfg sm8750_ctl[] = {
> +	{
> +		.name = "ctl_0", .id = CTL_0,
> +		.base = 0x15000, .len = 0x1000,
> +		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> +	}, {
> +		.name = "ctl_1", .id = CTL_1,
> +		.base = 0x16000, .len = 0x1000,
> +		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> +	}, {
> +		.name = "ctl_2", .id = CTL_2,
> +		.base = 0x17000, .len = 0x1000,
> +		.features = CTL_SM8550_MASK,
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> +	}, {
> +		.name = "ctl_3", .id = CTL_3,
> +		.base = 0x18000, .len = 0x1000,
> +		.features = CTL_SM8550_MASK,
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> +	}, {
> +		.name = "ctl_4", .id = CTL_4,
> +		.base = 0x19000, .len = 0x1000,
> +		.features = CTL_SM8550_MASK,
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> +	}, {
> +		.name = "ctl_5", .id = CTL_5,
> +		.base = 0x1a000, .len = 0x1000,
> +		.features = CTL_SM8550_MASK,
> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> +	},
> +};
> +
> +static const struct dpu_sspp_cfg sm8750_sspp[] = {
> +	{
> +		.name = "sspp_0", .id = SSPP_VIG0,
> +		.base = 0x4000, .len = 0x344,
> +		.features = VIG_SDM845_MASK_SDMA,
> +		.sblk = &dpu_vig_sblk_qseed3_3_4,
> +		.xin_id = 0,
> +		.type = SSPP_TYPE_VIG,
> +	}, {
> +		.name = "sspp_1", .id = SSPP_VIG1,
> +		.base = 0x6000, .len = 0x344,
> +		.features = VIG_SDM845_MASK_SDMA,
> +		.sblk = &dpu_vig_sblk_qseed3_3_4,
> +		.xin_id = 4,
> +		.type = SSPP_TYPE_VIG,
> +	}, {
> +		.name = "sspp_2", .id = SSPP_VIG2,
> +		.base = 0x8000, .len = 0x344,
> +		.features = VIG_SDM845_MASK_SDMA,
> +		.sblk = &dpu_vig_sblk_qseed3_3_4,
> +		.xin_id = 8,
> +		.type = SSPP_TYPE_VIG,
> +	}, {
> +		.name = "sspp_3", .id = SSPP_VIG3,
> +		.base = 0xa000, .len = 0x344,
> +		.features = VIG_SDM845_MASK_SDMA,
> +		.sblk = &dpu_vig_sblk_qseed3_3_4,
> +		.xin_id = 12,
> +		.type = SSPP_TYPE_VIG,
> +	}, {
> +		/* TODO: Indices/code for SSPP_VIG4 overlaps with SSPP_RGB0 */

Hmm, how can it overlap? SSPP_foo are just internal indices, they should
not be programmed into the hardware.

> +		.name = "sspp_8", .id = SSPP_DMA0,
> +		.base = 0x24000, .len = 0x344,
> +		.features = DMA_SDM845_MASK_SDMA,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 1,
> +		.type = SSPP_TYPE_DMA,
> +	}, {
> +		.name = "sspp_9", .id = SSPP_DMA1,
> +		.base = 0x26000, .len = 0x344,
> +		.features = DMA_SDM845_MASK_SDMA,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 5,
> +		.type = SSPP_TYPE_DMA,
> +	}, {
> +		.name = "sspp_10", .id = SSPP_DMA2,
> +		.base = 0x28000, .len = 0x344,
> +		.features = DMA_SDM845_MASK_SDMA,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 9,
> +		.type = SSPP_TYPE_DMA,
> +	}, {
> +		.name = "sspp_11", .id = SSPP_DMA3,
> +		.base = 0x2a000, .len = 0x344,
> +		.features = DMA_SDM845_MASK_SDMA,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 13,
> +		.type = SSPP_TYPE_DMA,
> +	}, {
> +		.name = "sspp_12", .id = SSPP_DMA4,
> +		.base = 0x2c000, .len = 0x344,
> +		.features = DMA_CURSOR_SDM845_MASK_SDMA,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 14,
> +		.type = SSPP_TYPE_DMA,
> +	}, {
> +		.name = "sspp_13", .id = SSPP_DMA5,
> +		.base = 0x2e000, .len = 0x344,
> +		.features = DMA_CURSOR_SDM845_MASK_SDMA,
> +		.sblk = &dpu_dma_sblk,
> +		.xin_id = 15,
> +		.type = SSPP_TYPE_DMA,
> +	},
> +};
> +
> +static const struct dpu_lm_cfg sm8750_lm[] = {
> +	{
> +		.name = "lm_0", .id = LM_0,
> +		.base = 0x44000, .len = 0x400,
> +		.features = MIXER_SDM845_MASK,
> +		.sblk = &sm8750_lm_sblk,
> +		.lm_pair = LM_1,
> +		.pingpong = PINGPONG_0,
> +		.dspp = DSPP_0,
> +	}, {
> +		.name = "lm_1", .id = LM_1,
> +		.base = 0x45000, .len = 0x400,
> +		.features = MIXER_SDM845_MASK,
> +		.sblk = &sm8750_lm_sblk,
> +		.lm_pair = LM_0,
> +		.pingpong = PINGPONG_1,
> +		.dspp = DSPP_1,
> +	}, {
> +		.name = "lm_2", .id = LM_2,
> +		.base = 0x46000, .len = 0x400,
> +		.features = MIXER_SDM845_MASK,
> +		.sblk = &sm8750_lm_sblk,
> +		.lm_pair = LM_3,
> +		.pingpong = PINGPONG_2,
> +		.dspp = DSPP_2,
> +	}, {
> +		.name = "lm_3", .id = LM_3,
> +		.base = 0x47000, .len = 0x400,
> +		.features = MIXER_SDM845_MASK,
> +		.sblk = &sm8750_lm_sblk,
> +		.lm_pair = LM_2,
> +		.pingpong = PINGPONG_3,
> +		.dspp = DSPP_3,
> +	}, {
> +		.name = "lm_4", .id = LM_4,
> +		.base = 0x48000, .len = 0x400,
> +		.features = MIXER_SDM845_MASK,
> +		.sblk = &sm8750_lm_sblk,
> +		.lm_pair = LM_5,
> +		.pingpong = PINGPONG_4,
> +	}, {
> +		.name = "lm_5", .id = LM_5,
> +		.base = 0x49000, .len = 0x400,
> +		.features = MIXER_SDM845_MASK,
> +		.sblk = &sm8750_lm_sblk,
> +		.lm_pair = LM_4,
> +		.pingpong = PINGPONG_5,
> +	}, {
> +		.name = "lm_6", .id = LM_6,
> +		.base = 0x4a000, .len = 0x400,
> +		.features = MIXER_SDM845_MASK,
> +		.sblk = &sm8750_lm_sblk,
> +		.lm_pair = LM_7,
> +		.pingpong = PINGPONG_6,
> +	}, {
> +		.name = "lm_7", .id = LM_7,
> +		.base = 0x4b000, .len = 0x400,
> +		.features = MIXER_SDM845_MASK,
> +		.sblk = &sm8750_lm_sblk,
> +		.lm_pair = LM_6,
> +		.pingpong = PINGPONG_7,
> +	},
> +};
> +
> +static const struct dpu_dspp_cfg sm8750_dspp[] = {
> +	{
> +		.name = "dspp_0", .id = DSPP_0,
> +		.base = 0x54000, .len = 0x1800,
> +		.features = DSPP_SC7180_MASK,
> +		.sblk = &sm8750_dspp_sblk,
> +	}, {
> +		.name = "dspp_1", .id = DSPP_1,
> +		.base = 0x56000, .len = 0x1800,
> +		.features = DSPP_SC7180_MASK,
> +		.sblk = &sm8750_dspp_sblk,
> +	}, {
> +		.name = "dspp_2", .id = DSPP_2,
> +		.base = 0x58000, .len = 0x1800,
> +		.features = DSPP_SC7180_MASK,
> +		.sblk = &sm8750_dspp_sblk,
> +	}, {
> +		.name = "dspp_3", .id = DSPP_3,
> +		.base = 0x5a000, .len = 0x1800,
> +		.features = DSPP_SC7180_MASK,
> +		.sblk = &sm8750_dspp_sblk,
> +	},
> +};
> +
> +static const struct dpu_pingpong_cfg sm8750_pp[] = {
> +	{
> +		.name = "pingpong_0", .id = PINGPONG_0,
> +		.base = 0x69000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_0,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> +	}, {
> +		.name = "pingpong_1", .id = PINGPONG_1,
> +		.base = 0x6a000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_0,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> +	}, {
> +		.name = "pingpong_2", .id = PINGPONG_2,
> +		.base = 0x6b000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_1,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> +	}, {
> +		.name = "pingpong_3", .id = PINGPONG_3,
> +		.base = 0x6c000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_1,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> +	}, {
> +		.name = "pingpong_4", .id = PINGPONG_4,
> +		.base = 0x6d000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_2,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> +	}, {
> +		.name = "pingpong_5", .id = PINGPONG_5,
> +		.base = 0x6e000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_2,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> +	}, {
> +		.name = "pingpong_6", .id = PINGPONG_6,
> +		.base = 0x6f000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_3,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
> +	}, {
> +		.name = "pingpong_7", .id = PINGPONG_7,
> +		.base = 0x70000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_3,
> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
> +	}, {
> +		.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
> +		.base = 0x66000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_4,
> +	}, {
> +		.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
> +		.base = 0x66400, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_4,
> +	}, {
> +		.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
> +		.base = 0x7e000, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_5,
> +	}, {
> +		.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
> +		.base = 0x7e400, .len = 0,
> +		.features = BIT(DPU_PINGPONG_DITHER),
> +		.sblk = &sc7280_pp_sblk,
> +		.merge_3d = MERGE_3D_5,
> +	},
> +};
> +
> +static const struct dpu_merge_3d_cfg sm8750_merge_3d[] = {
> +	{
> +		.name = "merge_3d_0", .id = MERGE_3D_0,
> +		.base = 0x4e000, .len = 0x1c,
> +	}, {
> +		.name = "merge_3d_1", .id = MERGE_3D_1,
> +		.base = 0x4f000, .len = 0x1c,
> +	}, {
> +		.name = "merge_3d_2", .id = MERGE_3D_2,
> +		.base = 0x50000, .len = 0x1c,
> +	}, {
> +		.name = "merge_3d_3", .id = MERGE_3D_3,
> +		.base = 0x51000, .len = 0x1c,
> +	}, {
> +		.name = "merge_3d_4", .id = MERGE_3D_4,
> +		.base = 0x66700, .len = 0x1c,
> +	}, {
> +		.name = "merge_3d_5", .id = MERGE_3D_5,
> +		.base = 0x7e700, .len = 0x1c,
> +	},
> +};
> +
> +/*
> + * NOTE: Each display compression engine (DCE) contains dual hard
> + * slice DSC encoders so both share same base address but with
> + * its own different sub block address.
> + */
> +static const struct dpu_dsc_cfg sm8750_dsc[] = {
> +	{
> +		.name = "dce_0_0", .id = DSC_0,
> +		.base = 0x80000, .len = 0x8,
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.sblk = &sm8750_dsc_sblk_0,
> +	}, {
> +		.name = "dce_0_1", .id = DSC_1,
> +		.base = 0x80000, .len = 0x8,
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.sblk = &sm8750_dsc_sblk_1,
> +	}, {
> +		.name = "dce_1_0", .id = DSC_2,
> +		.base = 0x81000, .len = 0x8,
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.sblk = &sm8750_dsc_sblk_0,
> +	}, {
> +		.name = "dce_1_1", .id = DSC_3,
> +		.base = 0x81000, .len = 0x8,
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.sblk = &sm8750_dsc_sblk_1,
> +	}, {
> +		.name = "dce_2_0", .id = DSC_4,
> +		.base = 0x82000, .len = 0x8,
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.sblk = &sm8750_dsc_sblk_0,
> +	}, {
> +		.name = "dce_2_1", .id = DSC_5,
> +		.base = 0x82000, .len = 0x8,
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.sblk = &sm8750_dsc_sblk_1,
> +	}, {
> +		.name = "dce_3_0", .id = DSC_6,
> +		.base = 0x83000, .len = 0x8,
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.sblk = &sm8750_dsc_sblk_0,
> +	}, {
> +		.name = "dce_3_1", .id = DSC_7,
> +		.base = 0x83000, .len = 0x8,
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.sblk = &sm8750_dsc_sblk_1,
> +	},
> +};
> +
> +static const struct dpu_wb_cfg sm8750_wb[] = {
> +	{
> +		.name = "wb_2", .id = WB_2,
> +		.base = 0x65000, .len = 0x2c8,
> +		.features = WB_SM8250_MASK,
> +		.format_list = wb2_formats_rgb,
> +		.num_formats = ARRAY_SIZE(wb2_formats_rgb),
> +		.xin_id = 6,
> +		.vbif_idx = VBIF_RT,
> +		.maxlinewidth = 4096,
> +		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
> +	},
> +};
> +
> +static const struct dpu_cwb_cfg sm8750_cwb[] = {
> +	{
> +		.name = "cwb_0", .id = CWB_0,
> +		.base = 0x66200, .len = 0x20,
> +	},
> +	{
> +		.name = "cwb_1", .id = CWB_1,
> +		.base = 0x66600, .len = 0x20,
> +	},
> +	{
> +		.name = "cwb_2", .id = CWB_2,
> +		.base = 0x7e200, .len = 0x20,
> +	},
> +	{
> +		.name = "cwb_3", .id = CWB_3,
> +		.base = 0x7e600, .len = 0x20,
> +	},
> +};
> +
> +static const struct dpu_intf_cfg sm8750_intf[] = {
> +	{
> +		.name = "intf_0", .id = INTF_0,
> +		.base = 0x34000, .len = 0x4bc,
> +		.features = INTF_SC7280_MASK,
> +		.type = INTF_DP,
> +		.controller_id = MSM_DP_CONTROLLER_0,
> +		.prog_fetch_lines_worst_case = 24,
> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> +	}, {
> +		.name = "intf_1", .id = INTF_1,
> +		.base = 0x35000, .len = 0x4bc,
> +		.features = INTF_SC7280_MASK,
> +		.type = INTF_DSI,
> +		.controller_id = MSM_DSI_CONTROLLER_0,
> +		.prog_fetch_lines_worst_case = 24,
> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> +		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> +	}, {
> +		.name = "intf_2", .id = INTF_2,
> +		.base = 0x36000, .len = 0x4bc,
> +		.features = INTF_SC7280_MASK,
> +		.type = INTF_DSI,
> +		.controller_id = MSM_DSI_CONTROLLER_1,
> +		.prog_fetch_lines_worst_case = 24,
> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> +		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
> +	}, {
> +		.name = "intf_3", .id = INTF_3,
> +		.base = 0x37000, .len = 0x4bc,
> +		.features = INTF_SC7280_MASK,
> +		.type = INTF_DP,
> +		.controller_id = MSM_DP_CONTROLLER_1,
> +		.prog_fetch_lines_worst_case = 24,
> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> +	},
> +};
> +
> +static const struct dpu_perf_cfg sm8750_perf_data = {
> +	.max_bw_low = 18900000,
> +	.max_bw_high = 28500000,
> +	.min_core_ib = 2500000,
> +	.min_llcc_ib = 0,
> +	.min_dram_ib = 800000,
> +	.min_prefill_lines = 35,
> +	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
> +	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
> +	.qos_lut_tbl = {
> +		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
> +		.entries = sc7180_qos_linear
> +		},
> +		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> +		.entries = sc7180_qos_macrotile
> +		},
> +		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> +		.entries = sc7180_qos_nrt
> +		},
> +		/* TODO: macrotile-qseed is different from macrotile */
> +	},
> +	.cdp_cfg = {
> +		{.rd_enable = 1, .wr_enable = 1},
> +		{.rd_enable = 1, .wr_enable = 0}
> +	},
> +	.clk_inefficiency_factor = 105,
> +	.bw_inefficiency_factor = 120,
> +};
> +
> +static const struct dpu_mdss_version sm8750_mdss_ver = {
> +	.core_major_ver = 12,
> +	.core_minor_ver = 0,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm8750_cfg = {
> +	.mdss_ver = &sm8750_mdss_ver,
> +	.caps = &sm8750_dpu_caps,
> +	.mdp = &sm8750_mdp,

no CDM block?

> +	.ctl_count = ARRAY_SIZE(sm8750_ctl),
> +	.ctl = sm8750_ctl,
> +	.sspp_count = ARRAY_SIZE(sm8750_sspp),
> +	.sspp = sm8750_sspp,
> +	.mixer_count = ARRAY_SIZE(sm8750_lm),
> +	.mixer = sm8750_lm,
> +	.dspp_count = ARRAY_SIZE(sm8750_dspp),
> +	.dspp = sm8750_dspp,
> +	.pingpong_count = ARRAY_SIZE(sm8750_pp),
> +	.pingpong = sm8750_pp,
> +	.dsc_count = ARRAY_SIZE(sm8750_dsc),
> +	.dsc = sm8750_dsc,
> +	.merge_3d_count = ARRAY_SIZE(sm8750_merge_3d),
> +	.merge_3d = sm8750_merge_3d,
> +	.wb_count = ARRAY_SIZE(sm8750_wb),
> +	.wb = sm8750_wb,
> +	.cwb_count = ARRAY_SIZE(sm8750_cwb),
> +	.cwb = sm8650_cwb,
> +	.intf_count = ARRAY_SIZE(sm8750_intf),
> +	.intf = sm8750_intf,
> +	.vbif_count = ARRAY_SIZE(sm8650_vbif),
> +	.vbif = sm8650_vbif,
> +	.perf = &sm8750_perf_data,
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 0b342c043875f3329a9f71c5e751b2244f9f5ef7..40966ab6283e666d1f113a62ada50298de68833b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -399,6 +399,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 =
>  static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =
>  				_VIG_SBLK(SSPP_SCALER_VER(3, 3));
>  
> +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =
> +				_VIG_SBLK(SSPP_SCALER_VER(3, 4));
> +
>  static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK();
>  
>  static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
> @@ -407,8 +410,6 @@ static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
>   * MIXER sub blocks config
>   *************************************************************/
>  
> -/* MSM8998 */
> -

This and the following changes: okay, but irrelevant, please split to a
separate commit.

>  static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
>  	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>  	.maxblendstages = 7, /* excluding base layer */
> @@ -418,8 +419,6 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
>  	},
>  };
>  
> -/* SDM845 */
> -
>  static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
>  	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>  	.maxblendstages = 11, /* excluding base layer */
> @@ -429,8 +428,6 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
>  	},
>  };
>  
> -/* SC7180 */
> -
>  static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
>  	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>  	.maxblendstages = 7, /* excluding base layer */
> @@ -439,7 +436,15 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
>  	},
>  };
>  
> -/* QCM2290 */
> +static const struct dpu_lm_sub_blks sm8750_lm_sblk = {
> +	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> +	.maxblendstages = 11, /* excluding base layer */
> +	.blendstage_base = { /* offsets relative to mixer base */
> +		/* 0x40 + n*0x30 */
> +		0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0,
> +		0x1f0, 0x220
> +	},
> +};
>  
>  static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
>  	.maxwidth = DEFAULT_DPU_LINE_WIDTH,
> @@ -462,6 +467,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
>  		.len = 0x90, .version = 0x40000},
>  };
>  
> +static const struct dpu_dspp_sub_blks sm8750_dspp_sblk = {
> +	.pcc = {.name = "pcc", .base = 0x1700,
> +		.len = 0x90, .version = 0x60000},
> +};
> +
>  /*************************************************************
>   * PINGPONG sub blocks config
>   *************************************************************/
> @@ -504,6 +514,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
>  	.ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
>  };
>  
> +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 = {
> +	.enc = {.name = "enc", .base = 0x100, .len = 0x100},
> +	.ctl = {.name = "ctl", .base = 0xF00, .len = 0x24},
> +};
> +
> +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 = {
> +	.enc = {.name = "enc", .base = 0x200, .len = 0x100},
> +	.ctl = {.name = "ctl", .base = 0xF80, .len = 0x24},
> +};
> +
>  /*************************************************************
>   * CDM block config
>   *************************************************************/
> @@ -787,3 +807,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>  #include "catalog/dpu_9_2_x1e80100.h"
>  
>  #include "catalog/dpu_10_0_sm8650.h"
> +#include "catalog/dpu_12_0_sm8750.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 4cea19e1a20380c56ae014f2d33a6884a72e0ca0..1bd313f2c6f199d5eefcdaa5f7c18ea512d48684 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -863,6 +863,7 @@ extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
>  extern const struct dpu_mdss_cfg dpu_sa8775p_cfg;
>  extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
>  extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm8750_cfg;
>  extern const struct dpu_mdss_cfg dpu_x1e80100_cfg;
>  
>  #endif /* _DPU_HW_CATALOG_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 4893f10d6a5832521808c0f4d8b231c356dbdc41..06b01cd36ce2442ee6e1b85be227851a234cc96b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -254,6 +254,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx,
>  	case LM_5:
>  		ctx->pending_flush_mask |= BIT(20);
>  		break;
> +	case LM_6:
> +		ctx->pending_flush_mask |= BIT(21);
> +		break;
> +	case LM_7:
> +		ctx->pending_flush_mask |= BIT(27);
> +		break;
>  	default:
>  		break;
>  	}

Please make functional changes first (new LMs, etc), keep catalog
limited to just catalog changes.

> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index ba7bb05efe9b8cac01a908e53121117e130f91ec..440a327c64eb83a944289c6ce9ef9a5bfacc25f3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -123,6 +123,7 @@ enum dpu_lm {
>  	LM_4,
>  	LM_5,
>  	LM_6,
> +	LM_7,
>  	LM_MAX
>  };
>  
> @@ -167,6 +168,8 @@ enum dpu_dsc {
>  	DSC_3,
>  	DSC_4,
>  	DSC_5,
> +	DSC_6,
> +	DSC_7,
>  	DSC_MAX
>  };
>  
> @@ -183,6 +186,8 @@ enum dpu_pingpong {
>  	PINGPONG_3,
>  	PINGPONG_4,
>  	PINGPONG_5,
> +	PINGPONG_6,
> +	PINGPONG_7,
>  	PINGPONG_CWB_0,
>  	PINGPONG_CWB_1,
>  	PINGPONG_CWB_2,
> @@ -197,6 +202,7 @@ enum dpu_merge_3d {
>  	MERGE_3D_2,
>  	MERGE_3D_3,
>  	MERGE_3D_4,
> +	MERGE_3D_5,
>  	MERGE_3D_MAX
>  };
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 97e9cb8c2b099f4757169cadf7e941148d2bfb16..ac131a01dc2bd99a2a54986ae1e3f7c324c9da50 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1515,6 +1515,7 @@ static const struct of_device_id dpu_dt_match[] = {
>  	{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
>  	{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
>  	{ .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
> +	{ .compatible = "qcom,sm8750-dpu", .data = &dpu_sm8750_cfg, },
>  	{ .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
>  	{}
>  };
> 
> -- 
> 2.43.0
> 

-- 
With best wishes
Dmitry

Re: [PATCH RFC 09/11] drm/msm/dpu: Add support for SM8750

[Krzysztof Kozlowski]

On 09/01/2025 23:18, Dmitry Baryshkov wrote:
> On Thu, Jan 09, 2025 at 02:08:36PM +0100, Krzysztof Kozlowski wrote:
>> Add DPU version v12.0 support for the Qualcomm SM8750 platform.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>>  .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h    | 522 +++++++++++++++++++++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  35 +-
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         |   6 +
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   6 +
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>>  6 files changed, 564 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..b093f6e529f6d5f4a4b600d766cefb509619a3c1
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
>> @@ -0,0 +1,522 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2024 Linaro Limited
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DPU_12_0_SM8750_H
>> +#define _DPU_12_0_SM8750_H
>> +
>> +static const struct dpu_caps sm8750_dpu_caps = {
>> +	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> +	.max_mixer_blendstages = 0xb,
>> +	.has_src_split = true,
>> +	.has_dim_layer = true,
>> +	.has_idle_pc = true,
>> +	.has_3d_merge = true,
>> +	.max_linewidth = 8192,
>> +	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
>> +
>> +static const struct dpu_mdp_cfg sm8750_mdp = {
>> +	.name = "top_0",
>> +	.base = 0, .len = 0x494,
>> +	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
>> +	.clk_ctrls = {
>> +		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
>> +	},
>> +};
>> +
>> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
>> +static const struct dpu_ctl_cfg sm8750_ctl[] = {
>> +	{
>> +		.name = "ctl_0", .id = CTL_0,
>> +		.base = 0x15000, .len = 0x1000,
>> +		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> +	}, {
>> +		.name = "ctl_1", .id = CTL_1,
>> +		.base = 0x16000, .len = 0x1000,
>> +		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> +	}, {
>> +		.name = "ctl_2", .id = CTL_2,
>> +		.base = 0x17000, .len = 0x1000,
>> +		.features = CTL_SM8550_MASK,
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> +	}, {
>> +		.name = "ctl_3", .id = CTL_3,
>> +		.base = 0x18000, .len = 0x1000,
>> +		.features = CTL_SM8550_MASK,
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> +	}, {
>> +		.name = "ctl_4", .id = CTL_4,
>> +		.base = 0x19000, .len = 0x1000,
>> +		.features = CTL_SM8550_MASK,
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> +	}, {
>> +		.name = "ctl_5", .id = CTL_5,
>> +		.base = 0x1a000, .len = 0x1000,
>> +		.features = CTL_SM8550_MASK,
>> +		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> +	},
>> +};
>> +
>> +static const struct dpu_sspp_cfg sm8750_sspp[] = {
>> +	{
>> +		.name = "sspp_0", .id = SSPP_VIG0,
>> +		.base = 0x4000, .len = 0x344,
>> +		.features = VIG_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_vig_sblk_qseed3_3_4,
>> +		.xin_id = 0,
>> +		.type = SSPP_TYPE_VIG,
>> +	}, {
>> +		.name = "sspp_1", .id = SSPP_VIG1,
>> +		.base = 0x6000, .len = 0x344,
>> +		.features = VIG_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_vig_sblk_qseed3_3_4,
>> +		.xin_id = 4,
>> +		.type = SSPP_TYPE_VIG,
>> +	}, {
>> +		.name = "sspp_2", .id = SSPP_VIG2,
>> +		.base = 0x8000, .len = 0x344,
>> +		.features = VIG_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_vig_sblk_qseed3_3_4,
>> +		.xin_id = 8,
>> +		.type = SSPP_TYPE_VIG,
>> +	}, {
>> +		.name = "sspp_3", .id = SSPP_VIG3,
>> +		.base = 0xa000, .len = 0x344,
>> +		.features = VIG_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_vig_sblk_qseed3_3_4,
>> +		.xin_id = 12,
>> +		.type = SSPP_TYPE_VIG,
>> +	}, {
>> +		/* TODO: Indices/code for SSPP_VIG4 overlaps with SSPP_RGB0 */
> 
> Hmm, how can it overlap? SSPP_foo are just internal indices, they should
> not be programmed into the hardware.

My own note, I'll just drop it.

> 
>> +		.name = "sspp_8", .id = SSPP_DMA0,
>> +		.base = 0x24000, .len = 0x344,
>> +		.features = DMA_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 1,
>> +		.type = SSPP_TYPE_DMA,
>> +	}, {
>> +		.name = "sspp_9", .id = SSPP_DMA1,
>> +		.base = 0x26000, .len = 0x344,
>> +		.features = DMA_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 5,
>> +		.type = SSPP_TYPE_DMA,
>> +	}, {
>> +		.name = "sspp_10", .id = SSPP_DMA2,
>> +		.base = 0x28000, .len = 0x344,
>> +		.features = DMA_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 9,
>> +		.type = SSPP_TYPE_DMA,
>> +	}, {
>> +		.name = "sspp_11", .id = SSPP_DMA3,
>> +		.base = 0x2a000, .len = 0x344,
>> +		.features = DMA_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 13,
>> +		.type = SSPP_TYPE_DMA,
>> +	}, {
>> +		.name = "sspp_12", .id = SSPP_DMA4,
>> +		.base = 0x2c000, .len = 0x344,
>> +		.features = DMA_CURSOR_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 14,
>> +		.type = SSPP_TYPE_DMA,
>> +	}, {
>> +		.name = "sspp_13", .id = SSPP_DMA5,
>> +		.base = 0x2e000, .len = 0x344,
>> +		.features = DMA_CURSOR_SDM845_MASK_SDMA,
>> +		.sblk = &dpu_dma_sblk,
>> +		.xin_id = 15,
>> +		.type = SSPP_TYPE_DMA,
>> +	},
>> +};
>> +
>> +static const struct dpu_lm_cfg sm8750_lm[] = {
>> +	{
>> +		.name = "lm_0", .id = LM_0,
>> +		.base = 0x44000, .len = 0x400,
>> +		.features = MIXER_SDM845_MASK,
>> +		.sblk = &sm8750_lm_sblk,
>> +		.lm_pair = LM_1,
>> +		.pingpong = PINGPONG_0,
>> +		.dspp = DSPP_0,
>> +	}, {
>> +		.name = "lm_1", .id = LM_1,
>> +		.base = 0x45000, .len = 0x400,
>> +		.features = MIXER_SDM845_MASK,
>> +		.sblk = &sm8750_lm_sblk,
>> +		.lm_pair = LM_0,
>> +		.pingpong = PINGPONG_1,
>> +		.dspp = DSPP_1,
>> +	}, {
>> +		.name = "lm_2", .id = LM_2,
>> +		.base = 0x46000, .len = 0x400,
>> +		.features = MIXER_SDM845_MASK,
>> +		.sblk = &sm8750_lm_sblk,
>> +		.lm_pair = LM_3,
>> +		.pingpong = PINGPONG_2,
>> +		.dspp = DSPP_2,
>> +	}, {
>> +		.name = "lm_3", .id = LM_3,
>> +		.base = 0x47000, .len = 0x400,
>> +		.features = MIXER_SDM845_MASK,
>> +		.sblk = &sm8750_lm_sblk,
>> +		.lm_pair = LM_2,
>> +		.pingpong = PINGPONG_3,
>> +		.dspp = DSPP_3,
>> +	}, {
>> +		.name = "lm_4", .id = LM_4,
>> +		.base = 0x48000, .len = 0x400,
>> +		.features = MIXER_SDM845_MASK,
>> +		.sblk = &sm8750_lm_sblk,
>> +		.lm_pair = LM_5,
>> +		.pingpong = PINGPONG_4,
>> +	}, {
>> +		.name = "lm_5", .id = LM_5,
>> +		.base = 0x49000, .len = 0x400,
>> +		.features = MIXER_SDM845_MASK,
>> +		.sblk = &sm8750_lm_sblk,
>> +		.lm_pair = LM_4,
>> +		.pingpong = PINGPONG_5,
>> +	}, {
>> +		.name = "lm_6", .id = LM_6,
>> +		.base = 0x4a000, .len = 0x400,
>> +		.features = MIXER_SDM845_MASK,
>> +		.sblk = &sm8750_lm_sblk,
>> +		.lm_pair = LM_7,
>> +		.pingpong = PINGPONG_6,
>> +	}, {
>> +		.name = "lm_7", .id = LM_7,
>> +		.base = 0x4b000, .len = 0x400,
>> +		.features = MIXER_SDM845_MASK,
>> +		.sblk = &sm8750_lm_sblk,
>> +		.lm_pair = LM_6,
>> +		.pingpong = PINGPONG_7,
>> +	},
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm8750_dspp[] = {
>> +	{
>> +		.name = "dspp_0", .id = DSPP_0,
>> +		.base = 0x54000, .len = 0x1800,
>> +		.features = DSPP_SC7180_MASK,
>> +		.sblk = &sm8750_dspp_sblk,
>> +	}, {
>> +		.name = "dspp_1", .id = DSPP_1,
>> +		.base = 0x56000, .len = 0x1800,
>> +		.features = DSPP_SC7180_MASK,
>> +		.sblk = &sm8750_dspp_sblk,
>> +	}, {
>> +		.name = "dspp_2", .id = DSPP_2,
>> +		.base = 0x58000, .len = 0x1800,
>> +		.features = DSPP_SC7180_MASK,
>> +		.sblk = &sm8750_dspp_sblk,
>> +	}, {
>> +		.name = "dspp_3", .id = DSPP_3,
>> +		.base = 0x5a000, .len = 0x1800,
>> +		.features = DSPP_SC7180_MASK,
>> +		.sblk = &sm8750_dspp_sblk,
>> +	},
>> +};
>> +
>> +static const struct dpu_pingpong_cfg sm8750_pp[] = {
>> +	{
>> +		.name = "pingpong_0", .id = PINGPONG_0,
>> +		.base = 0x69000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_0,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> +	}, {
>> +		.name = "pingpong_1", .id = PINGPONG_1,
>> +		.base = 0x6a000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_0,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> +	}, {
>> +		.name = "pingpong_2", .id = PINGPONG_2,
>> +		.base = 0x6b000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_1,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
>> +	}, {
>> +		.name = "pingpong_3", .id = PINGPONG_3,
>> +		.base = 0x6c000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_1,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
>> +	}, {
>> +		.name = "pingpong_4", .id = PINGPONG_4,
>> +		.base = 0x6d000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_2,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
>> +	}, {
>> +		.name = "pingpong_5", .id = PINGPONG_5,
>> +		.base = 0x6e000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_2,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
>> +	}, {
>> +		.name = "pingpong_6", .id = PINGPONG_6,
>> +		.base = 0x6f000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_3,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
>> +	}, {
>> +		.name = "pingpong_7", .id = PINGPONG_7,
>> +		.base = 0x70000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_3,
>> +		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
>> +	}, {
>> +		.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
>> +		.base = 0x66000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_4,
>> +	}, {
>> +		.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
>> +		.base = 0x66400, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_4,
>> +	}, {
>> +		.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
>> +		.base = 0x7e000, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_5,
>> +	}, {
>> +		.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
>> +		.base = 0x7e400, .len = 0,
>> +		.features = BIT(DPU_PINGPONG_DITHER),
>> +		.sblk = &sc7280_pp_sblk,
>> +		.merge_3d = MERGE_3D_5,
>> +	},
>> +};
>> +
>> +static const struct dpu_merge_3d_cfg sm8750_merge_3d[] = {
>> +	{
>> +		.name = "merge_3d_0", .id = MERGE_3D_0,
>> +		.base = 0x4e000, .len = 0x1c,
>> +	}, {
>> +		.name = "merge_3d_1", .id = MERGE_3D_1,
>> +		.base = 0x4f000, .len = 0x1c,
>> +	}, {
>> +		.name = "merge_3d_2", .id = MERGE_3D_2,
>> +		.base = 0x50000, .len = 0x1c,
>> +	}, {
>> +		.name = "merge_3d_3", .id = MERGE_3D_3,
>> +		.base = 0x51000, .len = 0x1c,
>> +	}, {
>> +		.name = "merge_3d_4", .id = MERGE_3D_4,
>> +		.base = 0x66700, .len = 0x1c,
>> +	}, {
>> +		.name = "merge_3d_5", .id = MERGE_3D_5,
>> +		.base = 0x7e700, .len = 0x1c,
>> +	},
>> +};
>> +
>> +/*
>> + * NOTE: Each display compression engine (DCE) contains dual hard
>> + * slice DSC encoders so both share same base address but with
>> + * its own different sub block address.
>> + */
>> +static const struct dpu_dsc_cfg sm8750_dsc[] = {
>> +	{
>> +		.name = "dce_0_0", .id = DSC_0,
>> +		.base = 0x80000, .len = 0x8,
>> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +		.sblk = &sm8750_dsc_sblk_0,
>> +	}, {
>> +		.name = "dce_0_1", .id = DSC_1,
>> +		.base = 0x80000, .len = 0x8,
>> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +		.sblk = &sm8750_dsc_sblk_1,
>> +	}, {
>> +		.name = "dce_1_0", .id = DSC_2,
>> +		.base = 0x81000, .len = 0x8,
>> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +		.sblk = &sm8750_dsc_sblk_0,
>> +	}, {
>> +		.name = "dce_1_1", .id = DSC_3,
>> +		.base = 0x81000, .len = 0x8,
>> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +		.sblk = &sm8750_dsc_sblk_1,
>> +	}, {
>> +		.name = "dce_2_0", .id = DSC_4,
>> +		.base = 0x82000, .len = 0x8,
>> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +		.sblk = &sm8750_dsc_sblk_0,
>> +	}, {
>> +		.name = "dce_2_1", .id = DSC_5,
>> +		.base = 0x82000, .len = 0x8,
>> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +		.sblk = &sm8750_dsc_sblk_1,
>> +	}, {
>> +		.name = "dce_3_0", .id = DSC_6,
>> +		.base = 0x83000, .len = 0x8,
>> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +		.sblk = &sm8750_dsc_sblk_0,
>> +	}, {
>> +		.name = "dce_3_1", .id = DSC_7,
>> +		.base = 0x83000, .len = 0x8,
>> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +		.sblk = &sm8750_dsc_sblk_1,
>> +	},
>> +};
>> +
>> +static const struct dpu_wb_cfg sm8750_wb[] = {
>> +	{
>> +		.name = "wb_2", .id = WB_2,
>> +		.base = 0x65000, .len = 0x2c8,
>> +		.features = WB_SM8250_MASK,
>> +		.format_list = wb2_formats_rgb,
>> +		.num_formats = ARRAY_SIZE(wb2_formats_rgb),
>> +		.xin_id = 6,
>> +		.vbif_idx = VBIF_RT,
>> +		.maxlinewidth = 4096,
>> +		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
>> +	},
>> +};
>> +
>> +static const struct dpu_cwb_cfg sm8750_cwb[] = {
>> +	{
>> +		.name = "cwb_0", .id = CWB_0,
>> +		.base = 0x66200, .len = 0x20,
>> +	},
>> +	{
>> +		.name = "cwb_1", .id = CWB_1,
>> +		.base = 0x66600, .len = 0x20,
>> +	},
>> +	{
>> +		.name = "cwb_2", .id = CWB_2,
>> +		.base = 0x7e200, .len = 0x20,
>> +	},
>> +	{
>> +		.name = "cwb_3", .id = CWB_3,
>> +		.base = 0x7e600, .len = 0x20,
>> +	},
>> +};
>> +
>> +static const struct dpu_intf_cfg sm8750_intf[] = {
>> +	{
>> +		.name = "intf_0", .id = INTF_0,
>> +		.base = 0x34000, .len = 0x4bc,
>> +		.features = INTF_SC7280_MASK,
>> +		.type = INTF_DP,
>> +		.controller_id = MSM_DP_CONTROLLER_0,
>> +		.prog_fetch_lines_worst_case = 24,
>> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
>> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
>> +	}, {
>> +		.name = "intf_1", .id = INTF_1,
>> +		.base = 0x35000, .len = 0x4bc,
>> +		.features = INTF_SC7280_MASK,
>> +		.type = INTF_DSI,
>> +		.controller_id = MSM_DSI_CONTROLLER_0,
>> +		.prog_fetch_lines_worst_case = 24,
>> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> +		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
>> +	}, {
>> +		.name = "intf_2", .id = INTF_2,
>> +		.base = 0x36000, .len = 0x4bc,
>> +		.features = INTF_SC7280_MASK,
>> +		.type = INTF_DSI,
>> +		.controller_id = MSM_DSI_CONTROLLER_1,
>> +		.prog_fetch_lines_worst_case = 24,
>> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
>> +		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
>> +	}, {
>> +		.name = "intf_3", .id = INTF_3,
>> +		.base = 0x37000, .len = 0x4bc,
>> +		.features = INTF_SC7280_MASK,
>> +		.type = INTF_DP,
>> +		.controller_id = MSM_DP_CONTROLLER_1,
>> +		.prog_fetch_lines_worst_case = 24,
>> +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>> +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
>> +	},
>> +};
>> +
>> +static const struct dpu_perf_cfg sm8750_perf_data = {
>> +	.max_bw_low = 18900000,
>> +	.max_bw_high = 28500000,
>> +	.min_core_ib = 2500000,
>> +	.min_llcc_ib = 0,
>> +	.min_dram_ib = 800000,
>> +	.min_prefill_lines = 35,
>> +	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
>> +	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
>> +	.qos_lut_tbl = {
>> +		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
>> +		.entries = sc7180_qos_linear
>> +		},
>> +		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
>> +		.entries = sc7180_qos_macrotile
>> +		},
>> +		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> +		.entries = sc7180_qos_nrt
>> +		},
>> +		/* TODO: macrotile-qseed is different from macrotile */
>> +	},
>> +	.cdp_cfg = {
>> +		{.rd_enable = 1, .wr_enable = 1},
>> +		{.rd_enable = 1, .wr_enable = 0}
>> +	},
>> +	.clk_inefficiency_factor = 105,
>> +	.bw_inefficiency_factor = 120,
>> +};
>> +
>> +static const struct dpu_mdss_version sm8750_mdss_ver = {
>> +	.core_major_ver = 12,
>> +	.core_minor_ver = 0,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_sm8750_cfg = {
>> +	.mdss_ver = &sm8750_mdss_ver,
>> +	.caps = &sm8750_dpu_caps,
>> +	.mdp = &sm8750_mdp,
> 
> no CDM block?

I can add it. This builts on top of previous support, so what was
missing there will be missing here.

So now we all gonna quote entire irrelevant context so finding our
answers will be difficult, great.

> 
>> +	.ctl_count = ARRAY_SIZE(sm8750_ctl),
>> +	.ctl = sm8750_ctl,
>> +	.sspp_count = ARRAY_SIZE(sm8750_sspp),
>> +	.sspp = sm8750_sspp,
>> +	.mixer_count = ARRAY_SIZE(sm8750_lm),
>> +	.mixer = sm8750_lm,
>> +	.dspp_count = ARRAY_SIZE(sm8750_dspp),
>> +	.dspp = sm8750_dspp,
>> +	.pingpong_count = ARRAY_SIZE(sm8750_pp),
>> +	.pingpong = sm8750_pp,
>> +	.dsc_count = ARRAY_SIZE(sm8750_dsc),
>> +	.dsc = sm8750_dsc,
>> +	.merge_3d_count = ARRAY_SIZE(sm8750_merge_3d),
>> +	.merge_3d = sm8750_merge_3d,
>> +	.wb_count = ARRAY_SIZE(sm8750_wb),
>> +	.wb = sm8750_wb,
>> +	.cwb_count = ARRAY_SIZE(sm8750_cwb),
>> +	.cwb = sm8650_cwb,
>> +	.intf_count = ARRAY_SIZE(sm8750_intf),
>> +	.intf = sm8750_intf,
>> +	.vbif_count = ARRAY_SIZE(sm8650_vbif),
>> +	.vbif = sm8650_vbif,
>> +	.perf = &sm8750_perf_data,
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 0b342c043875f3329a9f71c5e751b2244f9f5ef7..40966ab6283e666d1f113a62ada50298de68833b 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -399,6 +399,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 =
>>  static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =
>>  				_VIG_SBLK(SSPP_SCALER_VER(3, 3));
>>  
>> +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =
>> +				_VIG_SBLK(SSPP_SCALER_VER(3, 4));
>> +
>>  static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK();
>>  
>>  static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
>> @@ -407,8 +410,6 @@ static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
>>   * MIXER sub blocks config
>>   *************************************************************/
>>  
>> -/* MSM8998 */
>> -
> 
> This and the following changes: okay, but irrelevant, please split to a
> separate commit.
> 
>>  static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
>>  	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>>  	.maxblendstages = 7, /* excluding base layer */
>> @@ -418,8 +419,6 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
>>  	},
>>  };
>>  
>> -/* SDM845 */
>> -
>>  static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
>>  	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>>  	.maxblendstages = 11, /* excluding base layer */
>> @@ -429,8 +428,6 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
>>  	},
>>  };
>>  
>> -/* SC7180 */
>> -
>>  static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
>>  	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>>  	.maxblendstages = 7, /* excluding base layer */
>> @@ -439,7 +436,15 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
>>  	},
>>  };
>>  
>> -/* QCM2290 */
>> +static const struct dpu_lm_sub_blks sm8750_lm_sblk = {
>> +	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> +	.maxblendstages = 11, /* excluding base layer */
>> +	.blendstage_base = { /* offsets relative to mixer base */
>> +		/* 0x40 + n*0x30 */
>> +		0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0,
>> +		0x1f0, 0x220
>> +	},
>> +};
>>  
>>  static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
>>  	.maxwidth = DEFAULT_DPU_LINE_WIDTH,
>> @@ -462,6 +467,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
>>  		.len = 0x90, .version = 0x40000},
>>  };
>>  
>> +static const struct dpu_dspp_sub_blks sm8750_dspp_sblk = {
>> +	.pcc = {.name = "pcc", .base = 0x1700,
>> +		.len = 0x90, .version = 0x60000},
>> +};
>> +
>>  /*************************************************************
>>   * PINGPONG sub blocks config
>>   *************************************************************/
>> @@ -504,6 +514,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
>>  	.ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
>>  };
>>  
>> +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 = {
>> +	.enc = {.name = "enc", .base = 0x100, .len = 0x100},
>> +	.ctl = {.name = "ctl", .base = 0xF00, .len = 0x24},
>> +};
>> +
>> +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 = {
>> +	.enc = {.name = "enc", .base = 0x200, .len = 0x100},
>> +	.ctl = {.name = "ctl", .base = 0xF80, .len = 0x24},
>> +};
>> +
>>  /*************************************************************
>>   * CDM block config
>>   *************************************************************/
>> @@ -787,3 +807,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>>  #include "catalog/dpu_9_2_x1e80100.h"
>>  
>>  #include "catalog/dpu_10_0_sm8650.h"
>> +#include "catalog/dpu_12_0_sm8750.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 4cea19e1a20380c56ae014f2d33a6884a72e0ca0..1bd313f2c6f199d5eefcdaa5f7c18ea512d48684 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -863,6 +863,7 @@ extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
>>  extern const struct dpu_mdss_cfg dpu_sa8775p_cfg;
>>  extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
>>  extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm8750_cfg;
>>  extern const struct dpu_mdss_cfg dpu_x1e80100_cfg;
>>  
>>  #endif /* _DPU_HW_CATALOG_H */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> index 4893f10d6a5832521808c0f4d8b231c356dbdc41..06b01cd36ce2442ee6e1b85be227851a234cc96b 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> @@ -254,6 +254,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx,
>>  	case LM_5:
>>  		ctx->pending_flush_mask |= BIT(20);
>>  		break;
>> +	case LM_6:
>> +		ctx->pending_flush_mask |= BIT(21);
>> +		break;
>> +	case LM_7:
>> +		ctx->pending_flush_mask |= BIT(27);
>> +		break;
>>  	default:
>>  		break;
>>  	}
> 
> Please make functional changes first (new LMs, etc), keep catalog
> limited to just catalog changes.
> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> index ba7bb05efe9b8cac01a908e53121117e130f91ec..440a327c64eb83a944289c6ce9ef9a5bfacc25f3 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> @@ -123,6 +123,7 @@ enum dpu_lm {
>>  	LM_4,
>>  	LM_5,
>>  	LM_6,
>> +	LM_7,
>>  	LM_MAX
>>  };
>>  
>> @@ -167,6 +168,8 @@ enum dpu_dsc {
>>  	DSC_3,
>>  	DSC_4,
>>  	DSC_5,
>> +	DSC_6,
>> +	DSC_7,
>>  	DSC_MAX
>>  };
>>  
>> @@ -183,6 +186,8 @@ enum dpu_pingpong {
>>  	PINGPONG_3,
>>  	PINGPONG_4,
>>  	PINGPONG_5,
>> +	PINGPONG_6,
>> +	PINGPONG_7,
>>  	PINGPONG_CWB_0,
>>  	PINGPONG_CWB_1,
>>  	PINGPONG_CWB_2,
>> @@ -197,6 +202,7 @@ enum dpu_merge_3d {
>>  	MERGE_3D_2,
>>  	MERGE_3D_3,
>>  	MERGE_3D_4,
>> +	MERGE_3D_5,
>>  	MERGE_3D_MAX
>>  };
>>  
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 97e9cb8c2b099f4757169cadf7e941148d2bfb16..ac131a01dc2bd99a2a54986ae1e3f7c324c9da50 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1515,6 +1515,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>  	{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
>>  	{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
>>  	{ .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
>> +	{ .compatible = "qcom,sm8750-dpu", .data = &dpu_sm8750_cfg, },
>>  	{ .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
>>  	{}
>>  };
>>
>> -- 
>> 2.43.0
>>
> 


Best regards,
Krzysztof

[PATCH RFC 10/11] drm/msm/mdss: Add support for SM8750

[Krzysztof Kozlowski]

Add support for the Qualcomm SM8750 platform.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/gpu/drm/msm/msm_mdss.c | 33 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/msm/msm_mdss.h |  1 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index dcb49fd30402b80edd2cb5971f95a78eaad6081f..3f00eb6de3a9d2bee7637c6f516efff78b7d872b 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -222,6 +222,24 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
 	}
 }
 
+static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss)
+{
+	const struct msm_mdss_data *data = msm_mdss->mdss_data;
+	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
+		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
+
+	if (data->ubwc_bank_spread)
+		value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
+
+	if (data->macrotile_mode)
+		value |= MDSS_UBWC_STATIC_MACROTILE_MODE;
+
+	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
+
+	writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
+	writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
+}
+
 #define MDSS_HW_MAJ_MIN		\
 	(MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK)
 
@@ -339,6 +357,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
 	case UBWC_4_3:
 		msm_mdss_setup_ubwc_dec_40(msm_mdss);
 		break;
+	case UBWC_5_0:
+		msm_mdss_setup_ubwc_dec_50(msm_mdss);
+		break;
 	default:
 		dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
 			msm_mdss->mdss_data->ubwc_dec_version);
@@ -722,6 +743,17 @@ static const struct msm_mdss_data sm8550_data = {
 	.reg_bus_bw = 57000,
 };
 
+static const struct msm_mdss_data sm8750_data = {
+	.ubwc_enc_version = UBWC_5_0,
+	.ubwc_dec_version = UBWC_5_0,
+	.ubwc_swizzle = 6,
+	.ubwc_bank_spread = true,
+	/* TODO: highest_bank_bit = 2 for LP_DDR4 */
+	.highest_bank_bit = 3,
+	.macrotile_mode = true,
+	.reg_bus_bw = 57000,
+};
+
 static const struct msm_mdss_data x1e80100_data = {
 	.ubwc_enc_version = UBWC_4_0,
 	.ubwc_dec_version = UBWC_4_3,
@@ -756,6 +788,7 @@ static const struct of_device_id mdss_dt_match[] = {
 	{ .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
 	{ .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
 	{ .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
+	{ .compatible = "qcom,sm8750-mdss", .data = &sm8750_data},
 	{ .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
 	{}
 };
diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h
index 14dc53704314558841ee1fe08d93309fd2233812..dd0160c6ba1a297cea5b87cd8b03895b2aa08213 100644
--- a/drivers/gpu/drm/msm/msm_mdss.h
+++ b/drivers/gpu/drm/msm/msm_mdss.h
@@ -22,6 +22,7 @@ struct msm_mdss_data {
 #define UBWC_3_0 0x30000000
 #define UBWC_4_0 0x40000000
 #define UBWC_4_3 0x40030000
+#define UBWC_5_0 0x50000000
 
 const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev);
 

-- 
2.43.0

Re: [PATCH RFC 10/11] drm/msm/mdss: Add support for SM8750

[Dmitry Baryshkov]

On Thu, Jan 09, 2025 at 02:08:37PM +0100, Krzysztof Kozlowski wrote:
> Add support for the Qualcomm SM8750 platform.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  drivers/gpu/drm/msm/msm_mdss.c | 33 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/msm/msm_mdss.h |  1 +
>  2 files changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index dcb49fd30402b80edd2cb5971f95a78eaad6081f..3f00eb6de3a9d2bee7637c6f516efff78b7d872b 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -222,6 +222,24 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
>  	}
>  }
>  
> +static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss)
> +{
> +	const struct msm_mdss_data *data = msm_mdss->mdss_data;
> +	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
> +		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
> +
> +	if (data->ubwc_bank_spread)
> +		value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
> +
> +	if (data->macrotile_mode)
> +		value |= MDSS_UBWC_STATIC_MACROTILE_MODE;
> +
> +	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
> +
> +	writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
> +	writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);

Nit: this probably can be folded into the msm_mdss_setup_ubwc_dec_40(),
but I would not require it.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> +}
> +
>  #define MDSS_HW_MAJ_MIN		\
>  	(MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK)
>  

-- 
With best wishes
Dmitry

Re: [PATCH RFC 10/11] drm/msm/mdss: Add support for SM8750

[Krzysztof Kozlowski]

On 09/01/2025 23:39, Dmitry Baryshkov wrote:
> On Thu, Jan 09, 2025 at 02:08:37PM +0100, Krzysztof Kozlowski wrote:
>> Add support for the Qualcomm SM8750 platform.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>>  drivers/gpu/drm/msm/msm_mdss.c | 33 +++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/msm/msm_mdss.h |  1 +
>>  2 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>> index dcb49fd30402b80edd2cb5971f95a78eaad6081f..3f00eb6de3a9d2bee7637c6f516efff78b7d872b 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -222,6 +222,24 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
>>  	}
>>  }
>>  
>> +static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss)
>> +{
>> +	const struct msm_mdss_data *data = msm_mdss->mdss_data;
>> +	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
>> +		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
>> +
>> +	if (data->ubwc_bank_spread)
>> +		value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
>> +
>> +	if (data->macrotile_mode)
>> +		value |= MDSS_UBWC_STATIC_MACROTILE_MODE;
>> +
>> +	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
>> +
>> +	writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
>> +	writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
> 
> Nit: this probably can be folded into the msm_mdss_setup_ubwc_dec_40(),
> but I would not require it.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

That was my initial try, but the resulting code was getting big with all
the if-then.

Best regards,
Krzysztof

[PATCH RFC / WIP 11/11] drm/msm/dpu: WIP: CTL_LAYER_EXT is gone

[Krzysztof Kozlowski]

Not finished. Looking around, maybe someone already did some works
around new CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers?

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 12 ++++++------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c          |  3 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h          |  3 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c              | 10 ++++++++--
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
index b093f6e529f6d5f4a4b600d766cefb509619a3c1..df1ebb797959a67055acccd65137e4f1e342cd79 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
@@ -33,32 +33,32 @@ static const struct dpu_ctl_cfg sm8750_ctl[] = {
 	{
 		.name = "ctl_0", .id = CTL_0,
 		.base = 0x15000, .len = 0x1000,
-		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+		.features = CTL_SM8750_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	}, {
 		.name = "ctl_1", .id = CTL_1,
 		.base = 0x16000, .len = 0x1000,
-		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+		.features = CTL_SM8750_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	}, {
 		.name = "ctl_2", .id = CTL_2,
 		.base = 0x17000, .len = 0x1000,
-		.features = CTL_SM8550_MASK,
+		.features = CTL_SM8750_MASK,
 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	}, {
 		.name = "ctl_3", .id = CTL_3,
 		.base = 0x18000, .len = 0x1000,
-		.features = CTL_SM8550_MASK,
+		.features = CTL_SM8750_MASK,
 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 	}, {
 		.name = "ctl_4", .id = CTL_4,
 		.base = 0x19000, .len = 0x1000,
-		.features = CTL_SM8550_MASK,
+		.features = CTL_SM8750_MASK,
 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 	}, {
 		.name = "ctl_5", .id = CTL_5,
 		.base = 0x1a000, .len = 0x1000,
-		.features = CTL_SM8550_MASK,
+		.features = CTL_SM8750_MASK,
 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 	},
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 40966ab6283e666d1f113a62ada50298de68833b..8e938455459119708967e9c02a84042f3962ead1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -119,6 +119,9 @@
 #define CTL_SM8550_MASK \
 	(CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
 
+#define CTL_SM8750_MASK \
+	(CTL_SC7280_MASK | BIT(DPU_CTL_NO_LAYER_EXT))
+
 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
 
 #define INTF_SC7180_MASK \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 1bd313f2c6f199d5eefcdaa5f7c18ea512d48684..0231849b9c86662b44a0c133c87a64d9af047e7f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -137,6 +137,8 @@ enum {
  * @DPU_CTL_FETCH_ACTIVE:	Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:		CTL config to support multiple VMs
  * @DPU_CTL_HAS_LAYER_EXT4:	CTL has the CTL_LAYER_EXT4 register
+ * @DPU_CTL_NO_LAYER_EXT:	CTL has no CTL_LAYER_EXT registers at all, but
+ *                              has active bits for pipes and layer mixers
  * @DPU_CTL_DSPP_BLOCK_FLUSH:	CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
@@ -146,6 +148,7 @@ enum {
 	DPU_CTL_FETCH_ACTIVE,
 	DPU_CTL_VM_CFG,
 	DPU_CTL_HAS_LAYER_EXT4,
+	DPU_CTL_NO_LAYER_EXT,
 	DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
 	DPU_CTL_MAX
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 06b01cd36ce2442ee6e1b85be227851a234cc96b..502449cbbddcb21b7008f139ac065d187a16b68e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -40,6 +40,8 @@
 #define   CTL_INTF_FLUSH                0x110
 #define   CTL_CDM_FLUSH                0x114
 #define   CTL_PERIPH_FLUSH              0x128
+#define   CTL_PIPE_ACTIVE               0x12C
+#define   CTL_LAYER_ACTIVE              0x130
 #define   CTL_INTF_MASTER               0x134
 #define   CTL_DSPP_n_FLUSH(n)           ((0x13C) + ((n) * 4))
 
@@ -729,8 +731,12 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
 	ops->trigger_pending = dpu_hw_ctl_trigger_pending;
 	ops->reset = dpu_hw_ctl_reset_control;
 	ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
-	ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
-	ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
+	if (cap & BIT(DPU_CTL_NO_LAYER_EXT)) {
+		// TODO: NOT COMPLETE, This has to be implemented
+	} else {
+		ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
+		ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
+	}
 	ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
 	ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
 	if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))

-- 
2.43.0

Re: [PATCH RFC / WIP 11/11] drm/msm/dpu: WIP: CTL_LAYER_EXT is gone

[Dmitry Baryshkov]

On Thu, Jan 09, 2025 at 02:08:38PM +0100, Krzysztof Kozlowski wrote:
> Not finished. Looking around, maybe someone already did some works
> around new CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers?

This is not enough, the whole blend setup is to be moved to LM
block.

> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 12 ++++++------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c          |  3 +++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h          |  3 +++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c              | 10 ++++++++--
>  4 files changed, 20 insertions(+), 8 deletions(-)
> 

[...]

> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 06b01cd36ce2442ee6e1b85be227851a234cc96b..502449cbbddcb21b7008f139ac065d187a16b68e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -40,6 +40,8 @@
>  #define   CTL_INTF_FLUSH                0x110
>  #define   CTL_CDM_FLUSH                0x114
>  #define   CTL_PERIPH_FLUSH              0x128
> +#define   CTL_PIPE_ACTIVE               0x12C
> +#define   CTL_LAYER_ACTIVE              0x130
>  #define   CTL_INTF_MASTER               0x134
>  #define   CTL_DSPP_n_FLUSH(n)           ((0x13C) + ((n) * 4))
>  
> @@ -729,8 +731,12 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
>  	ops->trigger_pending = dpu_hw_ctl_trigger_pending;
>  	ops->reset = dpu_hw_ctl_reset_control;
>  	ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
> -	ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
> -	ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
> +	if (cap & BIT(DPU_CTL_NO_LAYER_EXT)) {

I'd prefer if this is was an explicit MDSS / DPU version check rather
than an extra feature bit, enable new functions for version >= 11.0

> +		// TODO: NOT COMPLETE, This has to be implemented
> +	} else {
> +		ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
> +		ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
> +	}
>  	ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
>  	ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
>  	if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
> 
> -- 
> 2.43.0
> 

-- 
With best wishes
Dmitry