[PATCH 0/4] arm64: dts: qcom: x1e80100: Enable bwmon and fastrpc support

[PATCH 0/4] arm64: dts: qcom: x1e80100: Enable bwmon and fastrpc support

[Sibi Sankar]

This patch series enables bwmon and fastrpc support on X1E80100 SoCs.

This series applies on:
next-20240603 + https://lore.kernel.org/lkml/20240603205859.2212225-1-quic_sibis@quicinc.com/

Sibi Sankar (4):
  dt-bindings: interconnect: qcom,msm8998-bwmon: Add X1E80100 BWMON
    instances
  soc: qcom: icc-bwmon: Allow for interrupts to be shared across
    instances
  arm64: dts: qcom: x1e80100: Add BWMONs
  arm64: dts: qcom: x1e80100: Add fastrpc nodes

 .../interconnect/qcom,msm8998-bwmon.yaml      |   2 +
 arch/arm64/boot/dts/qcom/x1e80100.dtsi        | 325 ++++++++++++++++++
 drivers/soc/qcom/icc-bwmon.c                  |   3 +-
 3 files changed, 329 insertions(+), 1 deletion(-)

-- 
2.34.1

[PATCH 1/4] dt-bindings: interconnect: qcom,msm8998-bwmon: Add X1E80100 BWMON instances

[Sibi Sankar]

Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4
instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR
path.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
 .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml    | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
index 05067e197abe..05f6bd348138 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -35,6 +35,7 @@ properties:
               - qcom,sm8250-cpu-bwmon
               - qcom,sm8550-cpu-bwmon
               - qcom,sm8650-cpu-bwmon
+              - qcom,x1e80100-cpu-bwmon
           - const: qcom,sdm845-bwmon    # BWMON v4, unified register space
       - items:
           - enum:
@@ -44,6 +45,7 @@ properties:
               - qcom,sm8250-llcc-bwmon
               - qcom,sm8550-llcc-bwmon
               - qcom,sm8650-llcc-bwmon
+              - qcom,x1e80100-llcc-bwmon
           - const: qcom,sc7280-llcc-bwmon
       - const: qcom,sc7280-llcc-bwmon   # BWMON v5
       - const: qcom,sdm845-llcc-bwmon   # BWMON v5
-- 
2.34.1

Re: [PATCH 1/4] dt-bindings: interconnect: qcom,msm8998-bwmon: Add X1E80100 BWMON instances

[Krzysztof Kozlowski]

On 04/06/2024 03:11, Sibi Sankar wrote:
> Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4
> instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR
> path.
> 
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances

[Sibi Sankar]

The multiple BWMONv4 instances available on the X1E80100 SoC use the
same interrupt number. Mark them are shared to allow for re-use across
instances.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
 drivers/soc/qcom/icc-bwmon.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c
index fb323b3364db..d69e0797eeda 100644
--- a/drivers/soc/qcom/icc-bwmon.c
+++ b/drivers/soc/qcom/icc-bwmon.c
@@ -783,7 +783,8 @@ static int bwmon_probe(struct platform_device *pdev)
 	bwmon_disable(bwmon);
 	ret = devm_request_threaded_irq(dev, bwmon->irq, bwmon_intr,
 					bwmon_intr_thread,
-					IRQF_ONESHOT, dev_name(dev), bwmon);
+					IRQF_ONESHOT | IRQF_SHARED,
+					dev_name(dev), bwmon);
 	if (ret)
 		return dev_err_probe(dev, ret, "failed to request IRQ\n");
 
-- 
2.34.1

Re: [PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances

[Krzysztof Kozlowski]

On 04/06/2024 03:11, Sibi Sankar wrote:
> The multiple BWMONv4 instances available on the X1E80100 SoC use the
> same interrupt number. Mark them are shared to allow for re-use across
> instances.

Would be nice if you also mention you checked that it is safe to have
both devm and shared interrupts (so you investigated possibility of race
on exit path).

Best regards,
Krzysztof

Re: [PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances

[Sibi Sankar]

On 6/4/24 12:16, Krzysztof Kozlowski wrote:
> On 04/06/2024 03:11, Sibi Sankar wrote:
>> The multiple BWMONv4 instances available on the X1E80100 SoC use the
>> same interrupt number. Mark them are shared to allow for re-use across
>> instances.

Hey Krzysztof,

Thanks for taking time to review the series :)

> 
> Would be nice if you also mention you checked that it is safe to have
> both devm and shared interrupts (so you investigated possibility of race
> on exit path).

I didn't see any problems with devm being used with SHARED when I posted
it out. After your review comments I went back again to vett the exit
path for races and ran into an pre-existing splat [1] but the bwmon
instances work as expected on module removal/re-insertion.

[1] - 
https://lore.kernel.org/lkml/20240613164506.982068-1-quic_sibis@quicinc.com/

-Sibi

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances

[Krzysztof Kozlowski]

On 13/06/2024 19:02, Sibi Sankar wrote:
> 
> 
> On 6/4/24 12:16, Krzysztof Kozlowski wrote:
>> On 04/06/2024 03:11, Sibi Sankar wrote:
>>> The multiple BWMONv4 instances available on the X1E80100 SoC use the
>>> same interrupt number. Mark them are shared to allow for re-use across
>>> instances.
> 
> Hey Krzysztof,
> 
> Thanks for taking time to review the series :)
> 
>>
>> Would be nice if you also mention you checked that it is safe to have
>> both devm and shared interrupts (so you investigated possibility of race
>> on exit path).
> 
> I didn't see any problems with devm being used with SHARED when I posted
> it out. After your review comments I went back again to vett the exit
> path for races and ran into an pre-existing splat [1] but the bwmon
> instances work as expected on module removal/re-insertion.

Using devm and shared interrupts is in general sign of possible race
issues and should be avoided. Just "not seeing problems" is not an
argument for me, to be honest.

Best regards,
Krzysztof

Re: [PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances

[Sibi Sankar]

On 6/14/24 13:54, Krzysztof Kozlowski wrote:
> On 13/06/2024 19:02, Sibi Sankar wrote:
>>
>>
>> On 6/4/24 12:16, Krzysztof Kozlowski wrote:
>>> On 04/06/2024 03:11, Sibi Sankar wrote:
>>>> The multiple BWMONv4 instances available on the X1E80100 SoC use the
>>>> same interrupt number. Mark them are shared to allow for re-use across
>>>> instances.
>>
>> Hey Krzysztof,
>>
>> Thanks for taking time to review the series :)
>>
>>>
>>> Would be nice if you also mention you checked that it is safe to have
>>> both devm and shared interrupts (so you investigated possibility of race
>>> on exit path).
>>
>> I didn't see any problems with devm being used with SHARED when I posted
>> it out. After your review comments I went back again to vett the exit
>> path for races and ran into an pre-existing splat [1] but the bwmon
>> instances work as expected on module removal/re-insertion.
> 
> Using devm and shared interrupts is in general sign of possible race
> issues and should be avoided. Just "not seeing problems" is not an
> argument for me, to be honest.

Didn't I go further and say I got it tested though? Also can you
elaborate on what race do you think the bwmon will hit rather than
being too generic about it?

-Sibi

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances

[Dmitry Baryshkov]

On Sat, Jun 15, 2024 at 01:49:34AM GMT, Sibi Sankar wrote:
> 
> 
> On 6/14/24 13:54, Krzysztof Kozlowski wrote:
> > On 13/06/2024 19:02, Sibi Sankar wrote:
> > > 
> > > 
> > > On 6/4/24 12:16, Krzysztof Kozlowski wrote:
> > > > On 04/06/2024 03:11, Sibi Sankar wrote:
> > > > > The multiple BWMONv4 instances available on the X1E80100 SoC use the
> > > > > same interrupt number. Mark them are shared to allow for re-use across
> > > > > instances.
> > > 
> > > Hey Krzysztof,
> > > 
> > > Thanks for taking time to review the series :)
> > > 
> > > > 
> > > > Would be nice if you also mention you checked that it is safe to have
> > > > both devm and shared interrupts (so you investigated possibility of race
> > > > on exit path).
> > > 
> > > I didn't see any problems with devm being used with SHARED when I posted
> > > it out. After your review comments I went back again to vett the exit
> > > path for races and ran into an pre-existing splat [1] but the bwmon
> > > instances work as expected on module removal/re-insertion.
> > 
> > Using devm and shared interrupts is in general sign of possible race
> > issues and should be avoided. Just "not seeing problems" is not an
> > argument for me, to be honest.
> 
> Didn't I go further and say I got it tested though? Also can you
> elaborate on what race do you think the bwmon will hit rather than
> being too generic about it?

devm_request_threaded_irq means that the IRQ is freed after the
bwmon_remove() function returns. Having IRQF_SHARED means that the IRQ
can still be triggered even though IRQ for this device has been disabled
in bwmon_disable().

In this particular case such IRQ probably won't cause issues, but at
least it needs to be validated and probably commented in bwmon_remove().
Just stating that "you tested and had no problems" usually isn't enough
for the expected race condition issues.

-- 
With best wishes
Dmitry

Re: [PATCH 2/4] soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances

[Sibi Sankar]

On 6/15/24 03:12, Dmitry Baryshkov wrote:
> On Sat, Jun 15, 2024 at 01:49:34AM GMT, Sibi Sankar wrote:
>>
>>
>> On 6/14/24 13:54, Krzysztof Kozlowski wrote:
>>> On 13/06/2024 19:02, Sibi Sankar wrote:
>>>>
>>>>
>>>> On 6/4/24 12:16, Krzysztof Kozlowski wrote:
>>>>> On 04/06/2024 03:11, Sibi Sankar wrote:
>>>>>> The multiple BWMONv4 instances available on the X1E80100 SoC use the
>>>>>> same interrupt number. Mark them are shared to allow for re-use across
>>>>>> instances.
>>>>
>>>> Hey Krzysztof,
>>>>
>>>> Thanks for taking time to review the series :)
>>>>
>>>>>
>>>>> Would be nice if you also mention you checked that it is safe to have
>>>>> both devm and shared interrupts (so you investigated possibility of race
>>>>> on exit path).
>>>>
>>>> I didn't see any problems with devm being used with SHARED when I posted
>>>> it out. After your review comments I went back again to vett the exit
>>>> path for races and ran into an pre-existing splat [1] but the bwmon
>>>> instances work as expected on module removal/re-insertion.
>>>
>>> Using devm and shared interrupts is in general sign of possible race
>>> issues and should be avoided. Just "not seeing problems" is not an
>>> argument for me, to be honest.
>>
>> Didn't I go further and say I got it tested though? Also can you
>> elaborate on what race do you think the bwmon will hit rather than
>> being too generic about it?
> 
> devm_request_threaded_irq means that the IRQ is freed after the
> bwmon_remove() function returns. Having IRQF_SHARED means that the IRQ
> can still be triggered even though IRQ for this device has been disabled
> in bwmon_disable().
> 
> In this particular case such IRQ probably won't cause issues, but at
> least it needs to be validated and probably commented in bwmon_remove().
> Just stating that "you tested and had no problems" usually isn't enough
> for the expected race condition issues.

Cool, thanks for the info. I'll get this fixed in the next re-spin.

-Sibi

> 

[PATCH 3/4] arm64: dts: qcom: x1e80100: Add BWMONs

[Sibi Sankar]

Add the CPU and LLCC BWMONs on X1E80100 SoCs.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++
 1 file changed, 169 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 1929c34ae70a..d86c4d3be126 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 {
 			};
 		};
 
+		pmu@24091000 {
+			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0 0x24091000 0 0x1000>;
+
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <800000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <2188000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <3072000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <6220800>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <6835200>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <8371200>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <10944000>;
+				};
+
+				opp-7 {
+					opp-peak-kBps = <12748800>;
+				};
+
+				opp-8 {
+					opp-peak-kBps = <14745600>;
+				};
+
+				opp-9 {
+					opp-peak-kBps = <16896000>;
+				};
+			};
+		};
+
+		pmu@240b3400 {
+			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0 0x240b3400 0 0x600>;
+
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+			operating-points-v2 = <&cpu0_bwmon_opp_table>;
+
+			cpu0_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-1 {
+					opp-peak-kBps = <4800000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <7464000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <9600000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <12896000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <14928000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <17064000>;
+				};
+			};
+		};
+
+		pmu@240b5400 {
+			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0 0x240b5400 0 0x600>;
+
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+			operating-points-v2 = <&cpu8_bwmon_opp_table>;
+
+			cpu8_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-1 {
+					opp-peak-kBps = <4800000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <7464000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <9600000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <12896000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <14928000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <17064000>;
+				};
+			};
+		};
+
+		pmu@240b6400 {
+			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0 0x240b6400 0 0x600>;
+
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+			operating-points-v2 = <&cpu4_bwmon_opp_table>;
+
+			cpu4_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-1 {
+					opp-peak-kBps = <4800000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <7464000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <9600000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <12896000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <14928000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <17064000>;
+				};
+			};
+		};
+
 		system-cache-controller@25000000 {
 			compatible = "qcom,x1e80100-llcc";
 			reg = <0 0x25000000 0 0x200000>,
-- 
2.34.1

Re: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add BWMONs

[Shivnandan Kumar]

On 6/4/2024 6:41 AM, Sibi Sankar wrote:
> Add the CPU and LLCC BWMONs on X1E80100 SoCs.
> 
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++
>   1 file changed, 169 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 1929c34ae70a..d86c4d3be126 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 {
>   			};
>   		};
>   
> +		pmu@24091000 {
> +			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> +			reg = <0 0x24091000 0 0x1000>;
> +
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
> +
> +			operating-points-v2 = <&llcc_bwmon_opp_table>;
> +
> +			llcc_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {

Nitpick,In one table, we start from ‘opp-0,’ while in the other table, 
it begins with ‘opp-1,it is better to make it consistent across table.

> +					opp-peak-kBps = <800000>;
> +				};
> +
> +				opp-1 {
> +					opp-peak-kBps = <2188000>;
> +				};
> +
> +				opp-2 {
> +					opp-peak-kBps = <3072000>;
> +				};
> +
> +				opp-3 {
> +					opp-peak-kBps = <6220800>;
> +				};
> +
> +				opp-4 {
> +					opp-peak-kBps = <6835200>;
> +				};
> +
> +				opp-5 {
> +					opp-peak-kBps = <8371200>;
> +				};
> +
> +				opp-6 {
> +					opp-peak-kBps = <10944000>;
> +				};
> +
> +				opp-7 {
> +					opp-peak-kBps = <12748800>;
> +				};
> +
> +				opp-8 {
> +					opp-peak-kBps = <14745600>;
> +				};
> +
> +				opp-9 {
> +					opp-peak-kBps = <16896000>;
> +				};
> +			};
> +		};
> +
> +		pmu@240b3400 {
> +			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
> +			reg = <0 0x240b3400 0 0x600>;
> +
> +			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
> +			operating-points-v2 = <&cpu0_bwmon_opp_table>;
> +
> +			cpu0_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-1 {
> +					opp-peak-kBps = <4800000>;
> +				};
> +
> +				opp-2 {
> +					opp-peak-kBps = <7464000>;
> +				};
> +
> +				opp-3 {
> +					opp-peak-kBps = <9600000>;
> +				};
> +
> +				opp-4 {
> +					opp-peak-kBps = <12896000>;
> +				};
> +
> +				opp-5 {
> +					opp-peak-kBps = <14928000>;
> +				};
> +
> +				opp-6 {
> +					opp-peak-kBps = <17064000>;
> +				};
> +			};
> +		};
> +
> +		pmu@240b5400 {
> +			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
> +			reg = <0 0x240b5400 0 0x600>;
> +
> +			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
> +			operating-points-v2 = <&cpu8_bwmon_opp_table>;
> +
> +			cpu8_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-1 {
> +					opp-peak-kBps = <4800000>;
> +				};
> +
> +				opp-2 {
> +					opp-peak-kBps = <7464000>;
> +				};
> +
> +				opp-3 {
> +					opp-peak-kBps = <9600000>;
> +				};
> +
> +				opp-4 {
> +					opp-peak-kBps = <12896000>;
> +				};
> +
> +				opp-5 {
> +					opp-peak-kBps = <14928000>;
> +				};
> +
> +				opp-6 {
> +					opp-peak-kBps = <17064000>;
> +				};
> +			};
> +		};
> +
> +		pmu@240b6400 {
> +			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
> +			reg = <0 0x240b6400 0 0x600>;
> +
> +			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
> +			operating-points-v2 = <&cpu4_bwmon_opp_table>;
> +
> +			cpu4_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-1 {
> +					opp-peak-kBps = <4800000>;
> +				};
> +
> +				opp-2 {
> +					opp-peak-kBps = <7464000>;
> +				};
> +
> +				opp-3 {
> +					opp-peak-kBps = <9600000>;
> +				};
> +
> +				opp-4 {
> +					opp-peak-kBps = <12896000>;
> +				};
> +
> +				opp-5 {
> +					opp-peak-kBps = <14928000>;
> +				};
> +
> +				opp-6 {
> +					opp-peak-kBps = <17064000>;
> +				};
> +			};
> +		};
> +
>   		system-cache-controller@25000000 {
>   			compatible = "qcom,x1e80100-llcc";
>   			reg = <0 0x25000000 0 0x200000>,


Thanks,
Shivnandan

Re: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add BWMONs

[Sibi Sankar]

On 6/6/24 14:39, Shivnandan Kumar wrote:
> 
> 
> On 6/4/2024 6:41 AM, Sibi Sankar wrote:
>> Add the CPU and LLCC BWMONs on X1E80100 SoCs.
>>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>

Hey Shiv,
Thanks for taking time to review the series :)

>> ---
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++
>>   1 file changed, 169 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
>> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 1929c34ae70a..d86c4d3be126 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 {
>>               };
>>           };
>> +        pmu@24091000 {
>> +            compatible = "qcom,x1e80100-llcc-bwmon", 
>> "qcom,sc7280-llcc-bwmon";
>> +            reg = <0 0x24091000 0 0x1000>;
>> +
>> +            interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +            interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt 
>> SLAVE_EBI1 3>;
>> +
>> +            operating-points-v2 = <&llcc_bwmon_opp_table>;
>> +
>> +            llcc_bwmon_opp_table: opp-table {
>> +                compatible = "operating-points-v2";
>> +
>> +                opp-0 {
> 
> Nitpick,In one table, we start from ‘opp-0,’ while in the other table, 
> it begins with ‘opp-1,it is better to make it consistent across table.
> 

Will fix it in the next re-spin.

-Sibi

>> +                    opp-peak-kBps = <800000>;
>>               reg = <0 0x25000000 0 0x200000>,
...
[snip]
...
> 
> 
> Thanks,
> Shivnandan

Re: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add BWMONs

[Konrad Dybcio]

On 4.06.2024 3:11 AM, Sibi Sankar wrote:
> Add the CPU and LLCC BWMONs on X1E80100 SoCs.
> 
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++
>  1 file changed, 169 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 1929c34ae70a..d86c4d3be126 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 {
>  			};
>  		};
>  
> +		pmu@24091000 {
> +			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> +			reg = <0 0x24091000 0 0x1000>;
> +
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;

QCOM_ICC_TAG_ACTIVE_ONLY

[...]

> +
> +			cpu0_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";

I *think* if you add opp-shared here, you can reference the same OPP table
from all 3 BWMONs without anything exploding.

Konrad

Re: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add BWMONs

[Sibi Sankar]

On 6/6/24 15:26, Konrad Dybcio wrote:
> On 4.06.2024 3:11 AM, Sibi Sankar wrote:
>> Add the CPU and LLCC BWMONs on X1E80100 SoCs.

Hey Konrad,

Thanks for taking time to review the series :)

>>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++
>>   1 file changed, 169 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 1929c34ae70a..d86c4d3be126 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 {
>>   			};
>>   		};
>>   
>> +		pmu@24091000 {
>> +			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
>> +			reg = <0 0x24091000 0 0x1000>;
>> +
>> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
> 
> QCOM_ICC_TAG_ACTIVE_ONLY

ack

> 
> [...]
> 
>> +
>> +			cpu0_bwmon_opp_table: opp-table {
>> +				compatible = "operating-points-v2";
> 
> I *think* if you add opp-shared here, you can reference the same OPP table
> from all 3 BWMONs without anything exploding.

I did try this out before IIRC this resulted in just one device vote
in the interconnect_summary. Didn't investigate further before because
it was breaking bindings anyway. Will have another look at it.

-Sibi

> 
> Konrad

[PATCH 4/4] arm64: dts: qcom: x1e80100: Add fastrpc nodes

[Sibi Sankar]

Add fastrpc nodes for ADSP and CDSP on X1E80100 SoC.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 156 +++++++++++++++++++++++++
 1 file changed, 156 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index d86c4d3be126..4edabe0ff592 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5567,6 +5567,55 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
 				label = "lpass";
 				qcom,remote-pid = <2>;
 
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1003 0x80>,
+							 <&apps_smmu 0x1063 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1004 0x80>,
+							 <&apps_smmu 0x1064 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1005 0x80>,
+							 <&apps_smmu 0x1065 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x1006 0x80>,
+							 <&apps_smmu 0x1066 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+						iommus = <&apps_smmu 0x1007 0x80>,
+							 <&apps_smmu 0x1067 0x0>;
+						dma-coherent;
+					};
+				};
+
 				gpr {
 					compatible = "qcom,gpr";
 					qcom,glink-channels = "adsp_apps";
@@ -5656,6 +5705,113 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
 
 				label = "cdsp";
 				qcom,remote-pid = <5>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "cdsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@1 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <1>;
+						iommus = <&apps_smmu 0x0c01 0x20>,
+							 <&apps_smmu 0x0c21 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@2 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <2>;
+						iommus = <&apps_smmu 0x0c02 0x20>,
+							 <&apps_smmu 0x0c22 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x0c03 0x20>,
+							 <&apps_smmu 0x0c23 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x0c04 0x20>,
+							 <&apps_smmu 0x0c24 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x0c05 0x20>,
+							 <&apps_smmu 0x0c25 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x0c06 0x20>,
+							 <&apps_smmu 0x0c26 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+						iommus = <&apps_smmu 0x0c07 0x20>,
+							 <&apps_smmu 0x0c27 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@8 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <8>;
+						iommus = <&apps_smmu 0x0c08 0x20>,
+							 <&apps_smmu 0x0c28 0x20>;
+						dma-coherent;
+					};
+
+					/* note: compute-cb@9 is secure */
+
+					compute-cb@10 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <10>;
+						iommus = <&apps_smmu 0x0c0c 0x20>,
+							 <&apps_smmu 0x0c2c 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@11 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <11>;
+						iommus = <&apps_smmu 0x0c0d 0x20>,
+							 <&apps_smmu 0x0c2d 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@12 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <12>;
+						iommus = <&apps_smmu 0x0c0e 0x20>,
+							 <&apps_smmu 0x0c2e 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@13 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <13>;
+						iommus = <&apps_smmu 0x0c0f 0x20>,
+							 <&apps_smmu 0x0c2f 0x20>;
+						dma-coherent;
+					};
+				};
 			};
 		};
 	};
-- 
2.34.1

Re: [PATCH 4/4] arm64: dts: qcom: x1e80100: Add fastrpc nodes

[Bjorn Andersson]

On Tue, Jun 04, 2024 at 06:41:57AM GMT, Sibi Sankar wrote:
> Add fastrpc nodes for ADSP and CDSP on X1E80100 SoC.
> 

This looks pretty unrelated to bwmon, could it not have been sent alone?

Regards,
Bjorn

> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 156 +++++++++++++++++++++++++
>  1 file changed, 156 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index d86c4d3be126..4edabe0ff592 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -5567,6 +5567,55 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
>  				label = "lpass";
>  				qcom,remote-pid = <2>;
>  
> +				fastrpc {
> +					compatible = "qcom,fastrpc";
> +					qcom,glink-channels = "fastrpcglink-apps-dsp";
> +					label = "adsp";
> +					qcom,non-secure-domain;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					compute-cb@3 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <3>;
> +						iommus = <&apps_smmu 0x1003 0x80>,
> +							 <&apps_smmu 0x1063 0x0>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@4 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <4>;
> +						iommus = <&apps_smmu 0x1004 0x80>,
> +							 <&apps_smmu 0x1064 0x0>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@5 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <5>;
> +						iommus = <&apps_smmu 0x1005 0x80>,
> +							 <&apps_smmu 0x1065 0x0>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@6 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <6>;
> +						iommus = <&apps_smmu 0x1006 0x80>,
> +							 <&apps_smmu 0x1066 0x0>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@7 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <7>;
> +						iommus = <&apps_smmu 0x1007 0x80>,
> +							 <&apps_smmu 0x1067 0x0>;
> +						dma-coherent;
> +					};
> +				};
> +
>  				gpr {
>  					compatible = "qcom,gpr";
>  					qcom,glink-channels = "adsp_apps";
> @@ -5656,6 +5705,113 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
>  
>  				label = "cdsp";
>  				qcom,remote-pid = <5>;
> +
> +				fastrpc {
> +					compatible = "qcom,fastrpc";
> +					qcom,glink-channels = "fastrpcglink-apps-dsp";
> +					label = "cdsp";
> +					qcom,non-secure-domain;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					compute-cb@1 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <1>;
> +						iommus = <&apps_smmu 0x0c01 0x20>,
> +							 <&apps_smmu 0x0c21 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@2 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <2>;
> +						iommus = <&apps_smmu 0x0c02 0x20>,
> +							 <&apps_smmu 0x0c22 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@3 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <3>;
> +						iommus = <&apps_smmu 0x0c03 0x20>,
> +							 <&apps_smmu 0x0c23 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@4 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <4>;
> +						iommus = <&apps_smmu 0x0c04 0x20>,
> +							 <&apps_smmu 0x0c24 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@5 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <5>;
> +						iommus = <&apps_smmu 0x0c05 0x20>,
> +							 <&apps_smmu 0x0c25 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@6 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <6>;
> +						iommus = <&apps_smmu 0x0c06 0x20>,
> +							 <&apps_smmu 0x0c26 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@7 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <7>;
> +						iommus = <&apps_smmu 0x0c07 0x20>,
> +							 <&apps_smmu 0x0c27 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@8 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <8>;
> +						iommus = <&apps_smmu 0x0c08 0x20>,
> +							 <&apps_smmu 0x0c28 0x20>;
> +						dma-coherent;
> +					};
> +
> +					/* note: compute-cb@9 is secure */
> +
> +					compute-cb@10 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <10>;
> +						iommus = <&apps_smmu 0x0c0c 0x20>,
> +							 <&apps_smmu 0x0c2c 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@11 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <11>;
> +						iommus = <&apps_smmu 0x0c0d 0x20>,
> +							 <&apps_smmu 0x0c2d 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@12 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <12>;
> +						iommus = <&apps_smmu 0x0c0e 0x20>,
> +							 <&apps_smmu 0x0c2e 0x20>;
> +						dma-coherent;
> +					};
> +
> +					compute-cb@13 {
> +						compatible = "qcom,fastrpc-compute-cb";
> +						reg = <13>;
> +						iommus = <&apps_smmu 0x0c0f 0x20>,
> +							 <&apps_smmu 0x0c2f 0x20>;
> +						dma-coherent;
> +					};
> +				};
>  			};
>  		};
>  	};
> -- 
> 2.34.1
> 

Re: [PATCH 4/4] arm64: dts: qcom: x1e80100: Add fastrpc nodes

[Sibi Sankar]

On 6/6/24 08:15, Bjorn Andersson wrote:
> On Tue, Jun 04, 2024 at 06:41:57AM GMT, Sibi Sankar wrote:
>> Add fastrpc nodes for ADSP and CDSP on X1E80100 SoC.
>>
> 
> This looks pretty unrelated to bwmon, could it not have been sent alone?

lol, I figured that the rest of the series was in decent shape to
land. Let me resend this one out standalone.

-Sibi

> 
> Regards,
> Bjorn
> 
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 156 +++++++++++++++++++++++++
>>   1 file changed, 156 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index d86c4d3be126..4edabe0ff592 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -5567,6 +5567,55 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
>>   				label = "lpass";
>>   				qcom,remote-pid = <2>;
>>   
>> +				fastrpc {
>> +					compatible = "qcom,fastrpc";
>> +					qcom,glink-channels = "fastrpcglink-apps-dsp";
>> +					label = "adsp";
>> +					qcom,non-secure-domain;
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +
>> +					compute-cb@3 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <3>;
>> +						iommus = <&apps_smmu 0x1003 0x80>,
>> +							 <&apps_smmu 0x1063 0x0>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@4 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <4>;
>> +						iommus = <&apps_smmu 0x1004 0x80>,
>> +							 <&apps_smmu 0x1064 0x0>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@5 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <5>;
>> +						iommus = <&apps_smmu 0x1005 0x80>,
>> +							 <&apps_smmu 0x1065 0x0>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@6 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <6>;
>> +						iommus = <&apps_smmu 0x1006 0x80>,
>> +							 <&apps_smmu 0x1066 0x0>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@7 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <7>;
>> +						iommus = <&apps_smmu 0x1007 0x80>,
>> +							 <&apps_smmu 0x1067 0x0>;
>> +						dma-coherent;
>> +					};
>> +				};
>> +
>>   				gpr {
>>   					compatible = "qcom,gpr";
>>   					qcom,glink-channels = "adsp_apps";
>> @@ -5656,6 +5705,113 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
>>   
>>   				label = "cdsp";
>>   				qcom,remote-pid = <5>;
>> +
>> +				fastrpc {
>> +					compatible = "qcom,fastrpc";
>> +					qcom,glink-channels = "fastrpcglink-apps-dsp";
>> +					label = "cdsp";
>> +					qcom,non-secure-domain;
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +
>> +					compute-cb@1 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <1>;
>> +						iommus = <&apps_smmu 0x0c01 0x20>,
>> +							 <&apps_smmu 0x0c21 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@2 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <2>;
>> +						iommus = <&apps_smmu 0x0c02 0x20>,
>> +							 <&apps_smmu 0x0c22 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@3 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <3>;
>> +						iommus = <&apps_smmu 0x0c03 0x20>,
>> +							 <&apps_smmu 0x0c23 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@4 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <4>;
>> +						iommus = <&apps_smmu 0x0c04 0x20>,
>> +							 <&apps_smmu 0x0c24 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@5 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <5>;
>> +						iommus = <&apps_smmu 0x0c05 0x20>,
>> +							 <&apps_smmu 0x0c25 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@6 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <6>;
>> +						iommus = <&apps_smmu 0x0c06 0x20>,
>> +							 <&apps_smmu 0x0c26 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@7 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <7>;
>> +						iommus = <&apps_smmu 0x0c07 0x20>,
>> +							 <&apps_smmu 0x0c27 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@8 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <8>;
>> +						iommus = <&apps_smmu 0x0c08 0x20>,
>> +							 <&apps_smmu 0x0c28 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					/* note: compute-cb@9 is secure */
>> +
>> +					compute-cb@10 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <10>;
>> +						iommus = <&apps_smmu 0x0c0c 0x20>,
>> +							 <&apps_smmu 0x0c2c 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@11 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <11>;
>> +						iommus = <&apps_smmu 0x0c0d 0x20>,
>> +							 <&apps_smmu 0x0c2d 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@12 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <12>;
>> +						iommus = <&apps_smmu 0x0c0e 0x20>,
>> +							 <&apps_smmu 0x0c2e 0x20>;
>> +						dma-coherent;
>> +					};
>> +
>> +					compute-cb@13 {
>> +						compatible = "qcom,fastrpc-compute-cb";
>> +						reg = <13>;
>> +						iommus = <&apps_smmu 0x0c0f 0x20>,
>> +							 <&apps_smmu 0x0c2f 0x20>;
>> +						dma-coherent;
>> +					};
>> +				};
>>   			};
>>   		};
>>   	};
>> -- 
>> 2.34.1
>>
> 

Re: [PATCH 0/4] arm64: dts: qcom: x1e80100: Enable bwmon and fastrpc support

[Konrad Dybcio]

On 4.06.2024 3:11 AM, Sibi Sankar wrote:
> This patch series enables bwmon and fastrpc support on X1E80100 SoCs.
> 
> This series applies on:
> next-20240603 + https://lore.kernel.org/lkml/20240603205859.2212225-1-quic_sibis@quicinc.com/
> 

Going back to [1], is memlat-over-scmi not enough to give us good numbers
without OS intervention? Does probing bwmon and making some decisions in
Linux actually help here?

Konrad

[1] https://lore.kernel.org/all/20240117173458.2312669-1-quic_sibis@quicinc.com/

Re: [PATCH 0/4] arm64: dts: qcom: x1e80100: Enable bwmon and fastrpc support

[Sibi Sankar]

On 6/6/24 16:00, Konrad Dybcio wrote:
> On 4.06.2024 3:11 AM, Sibi Sankar wrote:
>> This patch series enables bwmon and fastrpc support on X1E80100 SoCs.
>>
>> This series applies on:
>> next-20240603 + https://lore.kernel.org/lkml/20240603205859.2212225-1-quic_sibis@quicinc.com/
>>
> 
> Going back to [1], is memlat-over-scmi not enough to give us good numbers
> without OS intervention? Does probing bwmon and making some decisions in
> Linux actually help here?

Memlat and bwmon are meant to cover to different use cases. Though
they have a big overlap on when they get triggered bwmon is specifically
meant to address cases where band-width aggregation is required (meaning
if other peripherals already have a avg bw vote on active LLCC/DDR, the
vote from bwmon would be an additional request on top of that). However
to make use of this we should vote for avg-kbps in addition to peak from
icc-bwmon driver which we don't currently do (Shiv was planning on
sending a fix for it).

-Sibi

> 
> Konrad
> 
> [1] https://lore.kernel.org/all/20240117173458.2312669-1-quic_sibis@quicinc.com/

Re: [PATCH 0/4] arm64: dts: qcom: x1e80100: Enable bwmon and fastrpc support

[Konrad Dybcio]

On 6/13/24 19:27, Sibi Sankar wrote:
> 
> 
> On 6/6/24 16:00, Konrad Dybcio wrote:
>> On 4.06.2024 3:11 AM, Sibi Sankar wrote:
>>> This patch series enables bwmon and fastrpc support on X1E80100 SoCs.
>>>
>>> This series applies on:
>>> next-20240603 + https://lore.kernel.org/lkml/20240603205859.2212225-1-quic_sibis@quicinc.com/
>>>
>>
>> Going back to [1], is memlat-over-scmi not enough to give us good numbers
>> without OS intervention? Does probing bwmon and making some decisions in
>> Linux actually help here?
> 
> Memlat and bwmon are meant to cover to different use cases. Though
> they have a big overlap on when they get triggered bwmon is specifically
> meant to address cases where band-width aggregation is required (meaning
> if other peripherals already have a avg bw vote on active LLCC/DDR, the
> vote from bwmon would be an additional request on top of that). However
> to make use of this we should vote for avg-kbps in addition to peak from
> icc-bwmon driver which we don't currently do (Shiv was planning on
> sending a fix for it).

Great, thanks for confirming

Konrad