* [PATCH 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally
2023-05-22 0:42 [PATCH 0/6] drm/msm/dpu: rework interrupt handling Dmitry Baryshkov
@ 2023-05-22 0:42 ` Dmitry Baryshkov
2023-05-22 14:29 ` Neil Armstrong
2023-05-22 0:42 ` [PATCH 2/6] drm/msm/dpu: inline __intr_offset Dmitry Baryshkov
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-05-22 0:42 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
INTF_SC7280_MASK) results in this bit (and corrsponding operations)
being enabled for all interfaces, even the ones which do not have TE
block. Move this bit setting to INTF_DSI_TE(), so that it is only
enabled for those INTF blocks which have TE support.
Fixes: 152c1d430992 ("drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1dee5ba2b312..162141cb5c83 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -101,7 +101,6 @@
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
- BIT(DPU_INTF_TE) | \
BIT(DPU_INTF_STATUS_SUPPORTED) | \
BIT(DPU_DATA_HCTL_EN))
@@ -544,7 +543,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
{\
.name = _name, .id = _id, \
.base = _base, .len = _len, \
- .features = _features, \
+ .features = _features | BIT(DPU_INTF_TE), \
.type = _type, \
.controller_id = _ctrl_id, \
.prog_fetch_lines_worst_case = _progfetch, \
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally
2023-05-22 0:42 ` [PATCH 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally Dmitry Baryshkov
@ 2023-05-22 14:29 ` Neil Armstrong
0 siblings, 0 replies; 13+ messages in thread
From: Neil Armstrong @ 2023-05-22 14:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
> Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
> INTF_SC7280_MASK) results in this bit (and corrsponding operations)
> being enabled for all interfaces, even the ones which do not have TE
> block. Move this bit setting to INTF_DSI_TE(), so that it is only
> enabled for those INTF blocks which have TE support.
>
> Fixes: 152c1d430992 ("drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 1dee5ba2b312..162141cb5c83 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -101,7 +101,6 @@
>
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | \
> - BIT(DPU_INTF_TE) | \
> BIT(DPU_INTF_STATUS_SUPPORTED) | \
> BIT(DPU_DATA_HCTL_EN))
>
> @@ -544,7 +543,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> {\
> .name = _name, .id = _id, \
> .base = _base, .len = _len, \
> - .features = _features, \
> + .features = _features | BIT(DPU_INTF_TE), \
> .type = _type, \
> .controller_id = _ctrl_id, \
> .prog_fetch_lines_worst_case = _progfetch, \
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/6] drm/msm/dpu: inline __intr_offset
2023-05-22 0:42 [PATCH 0/6] drm/msm/dpu: rework interrupt handling Dmitry Baryshkov
2023-05-22 0:42 ` [PATCH 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally Dmitry Baryshkov
@ 2023-05-22 0:42 ` Dmitry Baryshkov
2023-05-22 14:30 ` Neil Armstrong
2023-05-22 0:42 ` [PATCH 3/6] drm/msm/dpu: split interrupt address arrays Dmitry Baryshkov
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-05-22 0:42 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
Inline __intr_offset(), there is no point in having a separate oneline
function for setting base block address.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 5e2d68ebb113..0776b0f6df4f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -435,12 +435,6 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
return intr_status;
}
-static void __intr_offset(const struct dpu_mdss_cfg *m,
- void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
-{
- hw->blk_addr = addr + m->mdp[0].base;
-}
-
struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
const struct dpu_mdss_cfg *m)
{
@@ -454,7 +448,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
if (!intr)
return ERR_PTR(-ENOMEM);
- __intr_offset(m, addr, &intr->hw);
+ intr->hw.blk_addr = addr + m->mdp[0].base;
intr->total_irqs = nirq;
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/6] drm/msm/dpu: inline __intr_offset
2023-05-22 0:42 ` [PATCH 2/6] drm/msm/dpu: inline __intr_offset Dmitry Baryshkov
@ 2023-05-22 14:30 ` Neil Armstrong
0 siblings, 0 replies; 13+ messages in thread
From: Neil Armstrong @ 2023-05-22 14:30 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
> Inline __intr_offset(), there is no point in having a separate oneline
> function for setting base block address.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +-------
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 5e2d68ebb113..0776b0f6df4f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -435,12 +435,6 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
> return intr_status;
> }
>
> -static void __intr_offset(const struct dpu_mdss_cfg *m,
> - void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
> -{
> - hw->blk_addr = addr + m->mdp[0].base;
> -}
> -
> struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> const struct dpu_mdss_cfg *m)
> {
> @@ -454,7 +448,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> if (!intr)
> return ERR_PTR(-ENOMEM);
>
> - __intr_offset(m, addr, &intr->hw);
> + intr->hw.blk_addr = addr + m->mdp[0].base;
>
> intr->total_irqs = nirq;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/6] drm/msm/dpu: split interrupt address arrays
2023-05-22 0:42 [PATCH 0/6] drm/msm/dpu: rework interrupt handling Dmitry Baryshkov
2023-05-22 0:42 ` [PATCH 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally Dmitry Baryshkov
2023-05-22 0:42 ` [PATCH 2/6] drm/msm/dpu: inline __intr_offset Dmitry Baryshkov
@ 2023-05-22 0:42 ` Dmitry Baryshkov
2023-05-22 14:36 ` Neil Armstrong
2023-05-22 0:42 ` [PATCH 4/6] drm/msm/dpu: autodetect supported interrupts Dmitry Baryshkov
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-05-22 0:42 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
3 files changed, 74 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 677048cc3b7d..72530ebb0ae6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
* @has_dim_layer dim layer feature status
* @has_idle_pc indicate if idle power collapse feature is supported
* @has_3d_merge indicate if 3D merge is supported
+ * @has_7xxx_intr indicate that INTF/IRQs use addressing for DPU 7.0 and greater
* @max_linewidth max linewidth for sspp
* @pixel_ram_size size of latency hiding and de-tiling buffer in bytes
* @max_hdeci_exp max horizontal decimation supported (max is 2^value)
@@ -364,6 +365,7 @@ struct dpu_caps {
bool has_dim_layer;
bool has_idle_pc;
bool has_3d_merge;
+ bool has_7xxx_intr;
/* SSPP limits */
u32 max_linewidth;
u32 pixel_ram_size;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 0776b0f6df4f..a03d826bb9ad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -51,11 +51,9 @@ struct dpu_intr_reg {
};
/*
- * struct dpu_intr_reg - List of DPU interrupt registers
- *
- * When making changes be sure to sync with dpu_hw_intr_reg
+ * dpu_intr_set_legacy - List of DPU interrupt registers for DPU <= 6.x
*/
-static const struct dpu_intr_reg dpu_intr_set[] = {
+static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
[MDP_SSPP_TOP0_INTR] = {
INTR_CLEAR,
INTR_EN,
@@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
MDP_AD4_INTR_EN_OFF(1),
MDP_AD4_INTR_STATUS_OFF(1),
},
- [MDP_INTF0_7xxx_INTR] = {
+};
+
+/*
+ * dpu_intr_set_7xxx - List of DPU interrupt registers for DPU >= 7.0
+ */
+static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
+ [MDP_SSPP_TOP0_INTR] = {
+ INTR_CLEAR,
+ INTR_EN,
+ INTR_STATUS
+ },
+ [MDP_SSPP_TOP0_INTR2] = {
+ INTR2_CLEAR,
+ INTR2_EN,
+ INTR2_STATUS
+ },
+ [MDP_SSPP_TOP0_HIST_INTR] = {
+ HIST_INTR_CLEAR,
+ HIST_INTR_EN,
+ HIST_INTR_STATUS
+ },
+ [MDP_INTF0_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(0),
MDP_INTF_REV_7xxx_INTR_EN(0),
MDP_INTF_REV_7xxx_INTR_STATUS(0)
},
- [MDP_INTF1_7xxx_INTR] = {
+ [MDP_INTF1_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(1),
MDP_INTF_REV_7xxx_INTR_EN(1),
MDP_INTF_REV_7xxx_INTR_STATUS(1)
},
- [MDP_INTF1_7xxx_TEAR_INTR] = {
+ [MDP_INTF1_TEAR_INTR] = {
MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
},
- [MDP_INTF2_7xxx_INTR] = {
+ [MDP_INTF2_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(2),
MDP_INTF_REV_7xxx_INTR_EN(2),
MDP_INTF_REV_7xxx_INTR_STATUS(2)
},
- [MDP_INTF2_7xxx_TEAR_INTR] = {
+ [MDP_INTF2_TEAR_INTR] = {
MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
},
- [MDP_INTF3_7xxx_INTR] = {
+ [MDP_INTF3_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(3),
MDP_INTF_REV_7xxx_INTR_EN(3),
MDP_INTF_REV_7xxx_INTR_STATUS(3)
},
- [MDP_INTF4_7xxx_INTR] = {
+ [MDP_INTF4_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(4),
MDP_INTF_REV_7xxx_INTR_EN(4),
MDP_INTF_REV_7xxx_INTR_STATUS(4)
},
- [MDP_INTF5_7xxx_INTR] = {
+ [MDP_INTF5_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(5),
MDP_INTF_REV_7xxx_INTR_EN(5),
MDP_INTF_REV_7xxx_INTR_STATUS(5)
},
- [MDP_INTF6_7xxx_INTR] = {
+ [MDP_INTF6_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(6),
MDP_INTF_REV_7xxx_INTR_EN(6),
MDP_INTF_REV_7xxx_INTR_STATUS(6)
},
- [MDP_INTF7_7xxx_INTR] = {
+ [MDP_INTF7_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(7),
MDP_INTF_REV_7xxx_INTR_EN(7),
MDP_INTF_REV_7xxx_INTR_STATUS(7)
},
- [MDP_INTF8_7xxx_INTR] = {
+ [MDP_INTF8_INTR] = {
MDP_INTF_REV_7xxx_INTR_CLEAR(8),
MDP_INTF_REV_7xxx_INTR_EN(8),
MDP_INTF_REV_7xxx_INTR_STATUS(8)
@@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
return IRQ_NONE;
spin_lock_irqsave(&intr->irq_lock, irq_flags);
- for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
+ for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
if (!test_bit(reg_idx, &intr->irq_mask))
continue;
/* Read interrupt status */
- irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
+ irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
/* Read enable mask */
- enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
+ enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
/* and clear the interrupt */
if (irq_status)
- DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
+ DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
irq_status);
/* Finally update IRQ status based on enable mask */
@@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
assert_spin_locked(&intr->irq_lock);
reg_idx = DPU_IRQ_REG(irq_idx);
- reg = &dpu_intr_set[reg_idx];
+ reg = &intr->intr_set[reg_idx];
+
+ /* Is this interrupt register supported on the platform */
+ if (WARN_ON(!reg->en_off))
+ return -EINVAL;
cache_irq_mask = intr->cache_irq_mask[reg_idx];
if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
@@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
assert_spin_locked(&intr->irq_lock);
reg_idx = DPU_IRQ_REG(irq_idx);
- reg = &dpu_intr_set[reg_idx];
+ reg = &intr->intr_set[reg_idx];
cache_irq_mask = intr->cache_irq_mask[reg_idx];
if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
@@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
if (!intr)
return;
- for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
+ for (i = 0; i < MDP_INTR_MAX; i++) {
if (test_bit(i, &intr->irq_mask))
DPU_REG_WRITE(&intr->hw,
- dpu_intr_set[i].clr_off, 0xffffffff);
+ intr->intr_set[i].clr_off, 0xffffffff);
}
/* ensure register writes go through */
@@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
if (!intr)
return;
- for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
+ for (i = 0; i < MDP_INTR_MAX; i++) {
if (test_bit(i, &intr->irq_mask))
DPU_REG_WRITE(&intr->hw,
- dpu_intr_set[i].en_off, 0x00000000);
+ intr->intr_set[i].en_off, 0x00000000);
}
/* ensure register writes go through */
@@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
reg_idx = DPU_IRQ_REG(irq_idx);
intr_status = DPU_REG_READ(&intr->hw,
- dpu_intr_set[reg_idx].status_off) &
+ intr->intr_set[reg_idx].status_off) &
DPU_IRQ_MASK(irq_idx);
if (intr_status)
- DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
+ DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
intr_status);
/* ensure register writes go through */
@@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
if (!intr)
return ERR_PTR(-ENOMEM);
+ if (m->caps->has_7xxx_intr)
+ intr->intr_set = dpu_intr_set_7xxx;
+ else
+ intr->intr_set = dpu_intr_set_legacy;
+
intr->hw.blk_addr = addr + m->mdp[0].base;
intr->total_irqs = nirq;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 1f2dabc54c22..f329d6d7f646 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
MDP_INTF3_INTR,
MDP_INTF4_INTR,
MDP_INTF5_INTR,
+ MDP_INTF6_INTR,
+ MDP_INTF7_INTR,
+ MDP_INTF8_INTR,
MDP_INTF1_TEAR_INTR,
MDP_INTF2_TEAR_INTR,
MDP_AD4_0_INTR,
MDP_AD4_1_INTR,
- MDP_INTF0_7xxx_INTR,
- MDP_INTF1_7xxx_INTR,
- MDP_INTF1_7xxx_TEAR_INTR,
- MDP_INTF2_7xxx_INTR,
- MDP_INTF2_7xxx_TEAR_INTR,
- MDP_INTF3_7xxx_INTR,
- MDP_INTF4_7xxx_INTR,
- MDP_INTF5_7xxx_INTR,
- MDP_INTF6_7xxx_INTR,
- MDP_INTF7_7xxx_INTR,
- MDP_INTF8_7xxx_INTR,
MDP_INTR_MAX,
};
+/* compatibility */
+#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
+#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
+#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
+#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
+#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
+#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
+#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
+#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
+#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
+#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
+#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
+
#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
/**
@@ -60,6 +65,7 @@ struct dpu_hw_intr {
u32 total_irqs;
spinlock_t irq_lock;
unsigned long irq_mask;
+ const struct dpu_intr_reg *intr_set;
struct {
void (*cb)(void *arg, int irq_idx);
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/6] drm/msm/dpu: split interrupt address arrays
2023-05-22 0:42 ` [PATCH 3/6] drm/msm/dpu: split interrupt address arrays Dmitry Baryshkov
@ 2023-05-22 14:36 ` Neil Armstrong
2023-05-22 14:58 ` Dmitry Baryshkov
0 siblings, 1 reply; 13+ messages in thread
From: Neil Armstrong @ 2023-05-22 14:36 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
Hi,
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
> There is no point in having a single enum (and a single array) for both
> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> enum and two IRQ address arrays.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
> 3 files changed, 74 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 677048cc3b7d..72530ebb0ae6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
> * @has_dim_layer dim layer feature status
> * @has_idle_pc indicate if idle power collapse feature is supported
> * @has_3d_merge indicate if 3D merge is supported
> + * @has_7xxx_intr indicate that INTF/IRQs use addressing for DPU 7.0 and greater
> * @max_linewidth max linewidth for sspp
> * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes
> * @max_hdeci_exp max horizontal decimation supported (max is 2^value)
> @@ -364,6 +365,7 @@ struct dpu_caps {
> bool has_dim_layer;
> bool has_idle_pc;
> bool has_3d_merge;
> + bool has_7xxx_intr;
looks good, but I can't find where has_7xxx_intr is set in the patchset
Neil
> /* SSPP limits */
> u32 max_linewidth;
> u32 pixel_ram_size;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 0776b0f6df4f..a03d826bb9ad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -51,11 +51,9 @@ struct dpu_intr_reg {
> };
>
> /*
> - * struct dpu_intr_reg - List of DPU interrupt registers
> - *
> - * When making changes be sure to sync with dpu_hw_intr_reg
> + * dpu_intr_set_legacy - List of DPU interrupt registers for DPU <= 6.x
> */
> -static const struct dpu_intr_reg dpu_intr_set[] = {
> +static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
> [MDP_SSPP_TOP0_INTR] = {
> INTR_CLEAR,
> INTR_EN,
> @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
> MDP_AD4_INTR_EN_OFF(1),
> MDP_AD4_INTR_STATUS_OFF(1),
> },
> - [MDP_INTF0_7xxx_INTR] = {
> +};
> +
> +/*
> + * dpu_intr_set_7xxx - List of DPU interrupt registers for DPU >= 7.0
> + */
> +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
> + [MDP_SSPP_TOP0_INTR] = {
> + INTR_CLEAR,
> + INTR_EN,
> + INTR_STATUS
> + },
> + [MDP_SSPP_TOP0_INTR2] = {
> + INTR2_CLEAR,
> + INTR2_EN,
> + INTR2_STATUS
> + },
> + [MDP_SSPP_TOP0_HIST_INTR] = {
> + HIST_INTR_CLEAR,
> + HIST_INTR_EN,
> + HIST_INTR_STATUS
> + },
> + [MDP_INTF0_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(0),
> MDP_INTF_REV_7xxx_INTR_EN(0),
> MDP_INTF_REV_7xxx_INTR_STATUS(0)
> },
> - [MDP_INTF1_7xxx_INTR] = {
> + [MDP_INTF1_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(1),
> MDP_INTF_REV_7xxx_INTR_EN(1),
> MDP_INTF_REV_7xxx_INTR_STATUS(1)
> },
> - [MDP_INTF1_7xxx_TEAR_INTR] = {
> + [MDP_INTF1_TEAR_INTR] = {
> MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
> MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
> MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
> },
> - [MDP_INTF2_7xxx_INTR] = {
> + [MDP_INTF2_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(2),
> MDP_INTF_REV_7xxx_INTR_EN(2),
> MDP_INTF_REV_7xxx_INTR_STATUS(2)
> },
> - [MDP_INTF2_7xxx_TEAR_INTR] = {
> + [MDP_INTF2_TEAR_INTR] = {
> MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
> MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
> MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
> },
> - [MDP_INTF3_7xxx_INTR] = {
> + [MDP_INTF3_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(3),
> MDP_INTF_REV_7xxx_INTR_EN(3),
> MDP_INTF_REV_7xxx_INTR_STATUS(3)
> },
> - [MDP_INTF4_7xxx_INTR] = {
> + [MDP_INTF4_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(4),
> MDP_INTF_REV_7xxx_INTR_EN(4),
> MDP_INTF_REV_7xxx_INTR_STATUS(4)
> },
> - [MDP_INTF5_7xxx_INTR] = {
> + [MDP_INTF5_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(5),
> MDP_INTF_REV_7xxx_INTR_EN(5),
> MDP_INTF_REV_7xxx_INTR_STATUS(5)
> },
> - [MDP_INTF6_7xxx_INTR] = {
> + [MDP_INTF6_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(6),
> MDP_INTF_REV_7xxx_INTR_EN(6),
> MDP_INTF_REV_7xxx_INTR_STATUS(6)
> },
> - [MDP_INTF7_7xxx_INTR] = {
> + [MDP_INTF7_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(7),
> MDP_INTF_REV_7xxx_INTR_EN(7),
> MDP_INTF_REV_7xxx_INTR_STATUS(7)
> },
> - [MDP_INTF8_7xxx_INTR] = {
> + [MDP_INTF8_INTR] = {
> MDP_INTF_REV_7xxx_INTR_CLEAR(8),
> MDP_INTF_REV_7xxx_INTR_EN(8),
> MDP_INTF_REV_7xxx_INTR_STATUS(8)
> @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
> return IRQ_NONE;
>
> spin_lock_irqsave(&intr->irq_lock, irq_flags);
> - for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> + for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
> if (!test_bit(reg_idx, &intr->irq_mask))
> continue;
>
> /* Read interrupt status */
> - irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
> + irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
>
> /* Read enable mask */
> - enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
> + enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
>
> /* and clear the interrupt */
> if (irq_status)
> - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> + DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
> irq_status);
>
> /* Finally update IRQ status based on enable mask */
> @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
> assert_spin_locked(&intr->irq_lock);
>
> reg_idx = DPU_IRQ_REG(irq_idx);
> - reg = &dpu_intr_set[reg_idx];
> + reg = &intr->intr_set[reg_idx];
> +
> + /* Is this interrupt register supported on the platform */
> + if (WARN_ON(!reg->en_off))
> + return -EINVAL;
>
> cache_irq_mask = intr->cache_irq_mask[reg_idx];
> if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
> @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
> assert_spin_locked(&intr->irq_lock);
>
> reg_idx = DPU_IRQ_REG(irq_idx);
> - reg = &dpu_intr_set[reg_idx];
> + reg = &intr->intr_set[reg_idx];
>
> cache_irq_mask = intr->cache_irq_mask[reg_idx];
> if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
> @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
> if (!intr)
> return;
>
> - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> + for (i = 0; i < MDP_INTR_MAX; i++) {
> if (test_bit(i, &intr->irq_mask))
> DPU_REG_WRITE(&intr->hw,
> - dpu_intr_set[i].clr_off, 0xffffffff);
> + intr->intr_set[i].clr_off, 0xffffffff);
> }
>
> /* ensure register writes go through */
> @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
> if (!intr)
> return;
>
> - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> + for (i = 0; i < MDP_INTR_MAX; i++) {
> if (test_bit(i, &intr->irq_mask))
> DPU_REG_WRITE(&intr->hw,
> - dpu_intr_set[i].en_off, 0x00000000);
> + intr->intr_set[i].en_off, 0x00000000);
> }
>
> /* ensure register writes go through */
> @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
>
> reg_idx = DPU_IRQ_REG(irq_idx);
> intr_status = DPU_REG_READ(&intr->hw,
> - dpu_intr_set[reg_idx].status_off) &
> + intr->intr_set[reg_idx].status_off) &
> DPU_IRQ_MASK(irq_idx);
> if (intr_status)
> - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> + DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
> intr_status);
>
> /* ensure register writes go through */
> @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> if (!intr)
> return ERR_PTR(-ENOMEM);
>
> + if (m->caps->has_7xxx_intr)
> + intr->intr_set = dpu_intr_set_7xxx;
> + else
> + intr->intr_set = dpu_intr_set_legacy;
> +
> intr->hw.blk_addr = addr + m->mdp[0].base;
>
> intr->total_irqs = nirq;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 1f2dabc54c22..f329d6d7f646 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
> MDP_INTF3_INTR,
> MDP_INTF4_INTR,
> MDP_INTF5_INTR,
> + MDP_INTF6_INTR,
> + MDP_INTF7_INTR,
> + MDP_INTF8_INTR,
> MDP_INTF1_TEAR_INTR,
> MDP_INTF2_TEAR_INTR,
> MDP_AD4_0_INTR,
> MDP_AD4_1_INTR,
> - MDP_INTF0_7xxx_INTR,
> - MDP_INTF1_7xxx_INTR,
> - MDP_INTF1_7xxx_TEAR_INTR,
> - MDP_INTF2_7xxx_INTR,
> - MDP_INTF2_7xxx_TEAR_INTR,
> - MDP_INTF3_7xxx_INTR,
> - MDP_INTF4_7xxx_INTR,
> - MDP_INTF5_7xxx_INTR,
> - MDP_INTF6_7xxx_INTR,
> - MDP_INTF7_7xxx_INTR,
> - MDP_INTF8_7xxx_INTR,
> MDP_INTR_MAX,
> };
>
> +/* compatibility */
> +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
> +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
> +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
> +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
> +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
> +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
> +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
> +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
> +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
> +
> #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
>
> /**
> @@ -60,6 +65,7 @@ struct dpu_hw_intr {
> u32 total_irqs;
> spinlock_t irq_lock;
> unsigned long irq_mask;
> + const struct dpu_intr_reg *intr_set;
>
> struct {
> void (*cb)(void *arg, int irq_idx);
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/6] drm/msm/dpu: split interrupt address arrays
2023-05-22 14:36 ` Neil Armstrong
@ 2023-05-22 14:58 ` Dmitry Baryshkov
0 siblings, 0 replies; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-05-22 14:58 UTC (permalink / raw)
To: neil.armstrong, Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 22/05/2023 17:36, Neil Armstrong wrote:
> Hi,
>
> On 22/05/2023 02:42, Dmitry Baryshkov wrote:
>> There is no point in having a single enum (and a single array) for both
>> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
>> enum and two IRQ address arrays.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
>> 3 files changed, 74 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 677048cc3b7d..72530ebb0ae6 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
>> * @has_dim_layer dim layer feature status
>> * @has_idle_pc indicate if idle power collapse feature is
>> supported
>> * @has_3d_merge indicate if 3D merge is supported
>> + * @has_7xxx_intr indicate that INTF/IRQs use addressing for DPU
>> 7.0 and greater
>> * @max_linewidth max linewidth for sspp
>> * @pixel_ram_size size of latency hiding and de-tiling buffer
>> in bytes
>> * @max_hdeci_exp max horizontal decimation supported (max is
>> 2^value)
>> @@ -364,6 +365,7 @@ struct dpu_caps {
>> bool has_dim_layer;
>> bool has_idle_pc;
>> bool has_3d_merge;
>> + bool has_7xxx_intr;
>
> looks good, but I can't find where has_7xxx_intr is set in the patchset
>
> Neil
Indeed. It seems I missed a patch.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/6] drm/msm/dpu: autodetect supported interrupts
2023-05-22 0:42 [PATCH 0/6] drm/msm/dpu: rework interrupt handling Dmitry Baryshkov
` (2 preceding siblings ...)
2023-05-22 0:42 ` [PATCH 3/6] drm/msm/dpu: split interrupt address arrays Dmitry Baryshkov
@ 2023-05-22 0:42 ` Dmitry Baryshkov
2023-05-22 0:42 ` [PATCH 5/6] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog Dmitry Baryshkov
2023-05-22 0:42 ` [PATCH 6/6] drm/msm/dpu: drop compatibility INTR defines Dmitry Baryshkov
5 siblings, 0 replies; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-05-22 0:42 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this with looping over the enabled INTF blocks
to setup the irq mask.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 20 ++++++++++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 6 ++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index a03d826bb9ad..01f2660a2354 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -463,6 +463,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
{
struct dpu_hw_intr *intr;
int nirq = MDP_INTR_MAX * 32;
+ unsigned int i;
if (!addr || !m)
return ERR_PTR(-EINVAL);
@@ -480,7 +481,24 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
intr->total_irqs = nirq;
- intr->irq_mask = m->mdss_irqs;
+ intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) |
+ BIT(MDP_SSPP_TOP0_INTR2) |
+ BIT(MDP_SSPP_TOP0_HIST_INTR);
+ for (i = 0; i < m->intf_count; i++) {
+ const struct dpu_intf_cfg *intf = &m->intf[i];
+
+ if (intf->type == INTF_NONE)
+ continue;
+
+ intr->irq_mask |= BIT(MDP_INTFn_INTR(intf->id));
+
+ if (test_bit(DPU_INTF_TE, &intf->features)) {
+ unsigned idx = MDP_INTFn_TEAR_INTR(intf->id);
+
+ if (!WARN_ON(idx == -1))
+ intr->irq_mask |= BIT(idx);
+ }
+ }
spin_lock_init(&intr->irq_lock);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index f329d6d7f646..f0b92c9e3b09 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -17,6 +17,7 @@ enum dpu_hw_intr_reg {
MDP_SSPP_TOP0_INTR,
MDP_SSPP_TOP0_INTR2,
MDP_SSPP_TOP0_HIST_INTR,
+ /* All MDP_INTFn_INTR should come sequentially */
MDP_INTF0_INTR,
MDP_INTF1_INTR,
MDP_INTF2_INTR,
@@ -33,6 +34,11 @@ enum dpu_hw_intr_reg {
MDP_INTR_MAX,
};
+#define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0))
+#define MDP_INTFn_TEAR_INTR(intf) (intf == INTF_1 ? MDP_INTF1_TEAR_INTR : \
+ intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
+ -1)
+
/* compatibility */
#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 5/6] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog
2023-05-22 0:42 [PATCH 0/6] drm/msm/dpu: rework interrupt handling Dmitry Baryshkov
` (3 preceding siblings ...)
2023-05-22 0:42 ` [PATCH 4/6] drm/msm/dpu: autodetect supported interrupts Dmitry Baryshkov
@ 2023-05-22 0:42 ` Dmitry Baryshkov
2023-05-22 14:37 ` Neil Armstrong
2023-05-22 0:42 ` [PATCH 6/6] drm/msm/dpu: drop compatibility INTR defines Dmitry Baryshkov
5 siblings, 1 reply; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-05-22 0:42 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
Now as the list of the interrupts is constructed from the catalog
data, drop the mdss_irqs field from catalog.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 --------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 9 ---------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 11 -----------
.../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 13 -------------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 10 ----------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 ------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 5 -----
.../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 5 -----
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 9 ---------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 -------
.../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 14 --------------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 9 ---------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 9 ---------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
14 files changed, 118 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 3c732a0360c7..ff7c3d522046 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -204,14 +204,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
.vbif_count = ARRAY_SIZE(msm8998_vbif),
.vbif = msm8998_vbif,
.perf = &msm8998_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_INTR) | \
- BIT(MDP_INTF1_INTR) | \
- BIT(MDP_INTF2_INTR) | \
- BIT(MDP_INTF3_INTR) | \
- BIT(MDP_INTF4_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 36ea1af10894..c4ccd742690a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -202,15 +202,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sdm845_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_INTR) | \
- BIT(MDP_INTF1_INTR) | \
- BIT(MDP_INTF2_INTR) | \
- BIT(MDP_INTF3_INTR) | \
- BIT(MDP_AD4_0_INTR) | \
- BIT(MDP_AD4_1_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index b5f751354267..fb7069d470ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -231,17 +231,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sm8150_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_INTR) | \
- BIT(MDP_INTF1_INTR) | \
- BIT(MDP_INTF1_TEAR_INTR) | \
- BIT(MDP_INTF2_INTR) | \
- BIT(MDP_INTF2_TEAR_INTR) | \
- BIT(MDP_INTF3_INTR) | \
- BIT(MDP_AD4_0_INTR) | \
- BIT(MDP_AD4_1_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 8ed2b263c5ea..bd7422e597aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -237,19 +237,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sc8180x_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_INTR) | \
- BIT(MDP_INTF1_INTR) | \
- BIT(MDP_INTF1_TEAR_INTR) | \
- BIT(MDP_INTF2_INTR) | \
- BIT(MDP_INTF2_TEAR_INTR) | \
- BIT(MDP_INTF3_INTR) | \
- BIT(MDP_INTF4_INTR) | \
- BIT(MDP_INTF5_INTR) | \
- BIT(MDP_AD4_0_INTR) | \
- BIT(MDP_AD4_1_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index daebd2170041..75a5c1b5a74a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -239,16 +239,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
.wb_count = ARRAY_SIZE(sm8250_wb),
.wb = sm8250_wb,
.perf = &sm8250_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_INTR) | \
- BIT(MDP_INTF1_INTR) | \
- BIT(MDP_INTF1_TEAR_INTR) | \
- BIT(MDP_INTF2_INTR) | \
- BIT(MDP_INTF2_TEAR_INTR) | \
- BIT(MDP_INTF3_INTR) | \
- BIT(MDP_INTF4_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 0b05da2592c0..84be02ce9c9c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -149,12 +149,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sc7180_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_INTR) | \
- BIT(MDP_INTF1_INTR) | \
- BIT(MDP_INTF1_TEAR_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index ba9de008519b..71d6e036a7a7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -122,11 +122,6 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sm6115_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF1_INTR) | \
- BIT(MDP_INTF1_TEAR_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 92ac348eea6b..d80b383d874d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -112,11 +112,6 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &qcm2290_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF1_INTR) | \
- BIT(MDP_INTF1_TEAR_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 3c1b2c13398d..f9e5f252ae54 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -222,15 +222,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sm8350_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF2_7xxx_INTR) | \
- BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF3_7xxx_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 5d894cbb0a62..dede8cb2d784 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -162,13 +162,6 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sc7280_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF5_7xxx_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index c3f1ae000a21..79ab2d015a44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -224,20 +224,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sc8280xp_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF2_7xxx_INTR) | \
- BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF3_7xxx_INTR) | \
- BIT(MDP_INTF4_7xxx_INTR) | \
- BIT(MDP_INTF5_7xxx_INTR) | \
- BIT(MDP_INTF6_7xxx_INTR) | \
- BIT(MDP_INTF7_7xxx_INTR) | \
- BIT(MDP_INTF8_7xxx_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 86c2e68ebd2c..b0bc88136e86 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -230,15 +230,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sm8450_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF2_7xxx_INTR) | \
- BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF3_7xxx_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 85dc34458b88..afed62e44f90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -234,15 +234,6 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sm8550_perf_data,
- .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
- BIT(MDP_SSPP_TOP0_INTR2) | \
- BIT(MDP_SSPP_TOP0_HIST_INTR) | \
- BIT(MDP_INTF0_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_INTR) | \
- BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF2_7xxx_INTR) | \
- BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
- BIT(MDP_INTF3_7xxx_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 72530ebb0ae6..6d8c2fa8558a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -777,7 +777,6 @@ struct dpu_perf_cfg {
* @dma_formats Supported formats for dma pipe
* @cursor_formats Supported formats for cursor pipe
* @vig_formats Supported formats for vig pipe
- * @mdss_irqs: Bitmap with the irqs supported by the target
*/
struct dpu_mdss_cfg {
const struct dpu_caps *caps;
@@ -825,8 +824,6 @@ struct dpu_mdss_cfg {
const struct dpu_format_extended *dma_formats;
const struct dpu_format_extended *cursor_formats;
const struct dpu_format_extended *vig_formats;
-
- unsigned long mdss_irqs;
};
extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 5/6] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog
2023-05-22 0:42 ` [PATCH 5/6] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog Dmitry Baryshkov
@ 2023-05-22 14:37 ` Neil Armstrong
0 siblings, 0 replies; 13+ messages in thread
From: Neil Armstrong @ 2023-05-22 14:37 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
> Now as the list of the interrupts is constructed from the catalog
> data, drop the mdss_irqs field from catalog.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 --------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 9 ---------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 11 -----------
> .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 13 -------------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 10 ----------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 ------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 5 -----
> .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 5 -----
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 9 ---------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 -------
> .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 14 --------------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 9 ---------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 9 ---------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
> 14 files changed, 118 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 3c732a0360c7..ff7c3d522046 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -204,14 +204,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
> .vbif_count = ARRAY_SIZE(msm8998_vbif),
> .vbif = msm8998_vbif,
> .perf = &msm8998_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF2_INTR) | \
> - BIT(MDP_INTF3_INTR) | \
> - BIT(MDP_INTF4_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 36ea1af10894..c4ccd742690a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -202,15 +202,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sdm845_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF2_INTR) | \
> - BIT(MDP_INTF3_INTR) | \
> - BIT(MDP_AD4_0_INTR) | \
> - BIT(MDP_AD4_1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index b5f751354267..fb7069d470ff 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -231,17 +231,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sm8150_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF1_TEAR_INTR) | \
> - BIT(MDP_INTF2_INTR) | \
> - BIT(MDP_INTF2_TEAR_INTR) | \
> - BIT(MDP_INTF3_INTR) | \
> - BIT(MDP_AD4_0_INTR) | \
> - BIT(MDP_AD4_1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 8ed2b263c5ea..bd7422e597aa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -237,19 +237,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sc8180x_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF1_TEAR_INTR) | \
> - BIT(MDP_INTF2_INTR) | \
> - BIT(MDP_INTF2_TEAR_INTR) | \
> - BIT(MDP_INTF3_INTR) | \
> - BIT(MDP_INTF4_INTR) | \
> - BIT(MDP_INTF5_INTR) | \
> - BIT(MDP_AD4_0_INTR) | \
> - BIT(MDP_AD4_1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index daebd2170041..75a5c1b5a74a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -239,16 +239,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
> .wb_count = ARRAY_SIZE(sm8250_wb),
> .wb = sm8250_wb,
> .perf = &sm8250_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF1_TEAR_INTR) | \
> - BIT(MDP_INTF2_INTR) | \
> - BIT(MDP_INTF2_TEAR_INTR) | \
> - BIT(MDP_INTF3_INTR) | \
> - BIT(MDP_INTF4_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 0b05da2592c0..84be02ce9c9c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -149,12 +149,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sc7180_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF1_TEAR_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index ba9de008519b..71d6e036a7a7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -122,11 +122,6 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sm6115_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF1_TEAR_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 92ac348eea6b..d80b383d874d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -112,11 +112,6 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &qcm2290_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF1_TEAR_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 3c1b2c13398d..f9e5f252ae54 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -222,15 +222,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sm8350_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF2_7xxx_INTR) | \
> - BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF3_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 5d894cbb0a62..dede8cb2d784 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -162,13 +162,6 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sc7280_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF5_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index c3f1ae000a21..79ab2d015a44 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -224,20 +224,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sc8280xp_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF2_7xxx_INTR) | \
> - BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF3_7xxx_INTR) | \
> - BIT(MDP_INTF4_7xxx_INTR) | \
> - BIT(MDP_INTF5_7xxx_INTR) | \
> - BIT(MDP_INTF6_7xxx_INTR) | \
> - BIT(MDP_INTF7_7xxx_INTR) | \
> - BIT(MDP_INTF8_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 86c2e68ebd2c..b0bc88136e86 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -230,15 +230,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sm8450_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF2_7xxx_INTR) | \
> - BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF3_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 85dc34458b88..afed62e44f90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -234,15 +234,6 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sm8550_perf_data,
> - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF2_7xxx_INTR) | \
> - BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> - BIT(MDP_INTF3_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 72530ebb0ae6..6d8c2fa8558a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -777,7 +777,6 @@ struct dpu_perf_cfg {
> * @dma_formats Supported formats for dma pipe
> * @cursor_formats Supported formats for cursor pipe
> * @vig_formats Supported formats for vig pipe
> - * @mdss_irqs: Bitmap with the irqs supported by the target
> */
> struct dpu_mdss_cfg {
> const struct dpu_caps *caps;
> @@ -825,8 +824,6 @@ struct dpu_mdss_cfg {
> const struct dpu_format_extended *dma_formats;
> const struct dpu_format_extended *cursor_formats;
> const struct dpu_format_extended *vig_formats;
> -
> - unsigned long mdss_irqs;
> };
>
> extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/6] drm/msm/dpu: drop compatibility INTR defines
2023-05-22 0:42 [PATCH 0/6] drm/msm/dpu: rework interrupt handling Dmitry Baryshkov
` (4 preceding siblings ...)
2023-05-22 0:42 ` [PATCH 5/6] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog Dmitry Baryshkov
@ 2023-05-22 0:42 ` Dmitry Baryshkov
2023-05-22 14:37 ` Neil Armstrong
5 siblings, 1 reply; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-05-22 0:42 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
While reworking interrupts masks, it was easier to keep old
MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
to drop them and use unified symbol names.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
.../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 13 -------------
6 files changed, 9 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index f9e5f252ae54..c64b6a7a30af 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -160,11 +160,11 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index dede8cb2d784..98623388badc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -106,7 +106,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 79ab2d015a44..fde9204c2c8e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -150,11 +150,11 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index b0bc88136e86..3821cc465c47 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -168,11 +168,11 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index afed62e44f90..f35671d1f2b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -172,11 +172,11 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
+ DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index f0b92c9e3b09..4a46c0900e04 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -39,19 +39,6 @@ enum dpu_hw_intr_reg {
intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
-1)
-/* compatibility */
-#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
-#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
-#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
-#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
-#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
-#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
-#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
-#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
-#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
-#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
-#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
-
#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
/**
--
2.39.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 6/6] drm/msm/dpu: drop compatibility INTR defines
2023-05-22 0:42 ` [PATCH 6/6] drm/msm/dpu: drop compatibility INTR defines Dmitry Baryshkov
@ 2023-05-22 14:37 ` Neil Armstrong
0 siblings, 0 replies; 13+ messages in thread
From: Neil Armstrong @ 2023-05-22 14:37 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Abhinav Kumar
Cc: Marijn Suijten, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno
On 22/05/2023 02:42, Dmitry Baryshkov wrote:
> While reworking interrupts masks, it was easier to keep old
> MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
> to drop them and use unified symbol names.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++--
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
> .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++--
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++--
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 13 -------------
> 6 files changed, 9 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index f9e5f252ae54..c64b6a7a30af 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -160,11 +160,11 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
> INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
> INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index dede8cb2d784..98623388badc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -106,7 +106,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 79ab2d015a44..fde9204c2c8e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -150,11 +150,11 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
> INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index b0bc88136e86..3821cc465c47 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -168,11 +168,11 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
> INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
> INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index afed62e44f90..f35671d1f2b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -172,11 +172,11 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
> INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> + DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
> INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index f0b92c9e3b09..4a46c0900e04 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -39,19 +39,6 @@ enum dpu_hw_intr_reg {
> intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
> -1)
>
> -/* compatibility */
> -#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> -#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> -#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
> -#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
> -#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
> -#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
> -#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
> -#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
> -#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
> -#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
> -#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
> -
> #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
>
> /**
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 13+ messages in thread