* [PATCH v7 0/5] media: qcom: camss: Add sc7280 support
@ 2024-12-04 9:59 Vikram Sharma
2024-12-04 9:59 ` [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss Vikram Sharma
` (4 more replies)
0 siblings, 5 replies; 17+ messages in thread
From: Vikram Sharma @ 2024-12-04 9:59 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
SC7280 is a Qualcomm SoC. This series adds support to bring up the CSIPHY,
CSID, VFE/RDI interfaces in SC7280.
SC7280 provides
- 3 x VFE, 3 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE
- 3 x CSID
- 2 x CSID Lite
- 5 x CSI PHY
The changes are verified on SC7280 qcs6490-rb3gen2 board, with attached vision mezzanine
TPG (mode 1-9) and IMX577 sensor.
The base dts for qcs6490-rb3gen2 is:
https://lore.kernel.org/all/20231103184655.23555-1-quic_kbajaj@quicinc.com/
This change is dependent on below series. As it is raised on top of
this. Please take both to validate.
https://lore.kernel.org/lkml/20241126100126.2743795-1-quic_vikramsa@quicinc.com/
Used following tools for the sanity check of these changes.
- make CHECK_DTBS=y W=1 DT_SCHEMA_FILES=media/qcom,sc7280-camss.yaml
qcom/qcs6490-rb3gen2-vision-mezzanine.dtb
- make DT_CHECKER_FLAGS=-m W=1
DT_SCHEMA_FILES=media/qcom,sc7280-camss.yaml dt_binding_check
- Smatch: make CHECK="smatch --full-path"
M=drivers/media/platform/qcom/camss/
- Sparse: make C=2 M=drivers/media/platform/qcom/camss/
- coccicheck : make coccicheck M=drivers/media/platform/qcom/camss/
- make -j32 W=1
- ./scripts/checkpatch.pl
Changes in V7:
- Changed unit address for camss in documention and dts.
- Added avdd-supply and dvdd-supply for sensor.
- Changed reg/clocks/interrupts name for vfe_lite and csid_lite.
- Link to v6: https://lore.kernel.org/linux-arm-msm/20241127100421.3447601-1-quic_vikramsa@quicinc.com/
Changes in V6:
- Changed order of properties in Documentation [PATCH 1/5].
- Updated description for ports in Documentaion [PATCH 1/5].
- Moved regulators from csid to csiphy [PATCH 3/5].
- Link to v5: https://lore.kernel.org/linux-arm-msm/20241112173032.2740119-1-quic_vikramsa@quicinc.com/
Changes in V5:
- Updated Commit text for [PATCH v5 1/6].
- Moved reg after compatible string.
- Renamed csi'x' clocks to vfe'x'_csid
- Removed [PATCH v4 4/6] and raised a seprate series for this one.
- Moved gpio states to mezzanine dtso.
- Added more clock levels to address TPG related issues.
- Renamed power-domains-names -> power-domain-names.
- Link to v4: https://lore.kernel.org/linux-arm-msm/20241030105347.2117034-1-quic_vikramsa@quicinc.com/
Changes in V4:
- V3 had 8 patches and V4 is reduced to 6.
- Removed [Patch v3 2/8] as binding change is not required for dtso.
- Removed [Patch v3 3/8] as the fix is already taken care in latest
kernel tip.
- Updated alignment for dtsi and dt-bindings.
- Adding qcs6490-rb3gen2-vision-mezzanine as overlay.
- Link to v3: https://lore.kernel.org/linux-arm-msm/20241011140932.1744124-1-quic_vikramsa@quicinc.com/
Changes in V3:
- Added missed subject line for cover letter of V2.
- Updated Alignment, indentation and properties order.
- edit commit text for [PATCH 02/10] and [PATCH 03/10].
- Refactor camss_link_entities.
- Removed camcc enablement changes as it already done.
- Link to v2: https://lore.kernel.org/linux-arm-msm/20240904-camss_on_sc7280_rb3gen2_vision_v2_patches-v1-0-b18ddcd7d9df@quicinc.com/
Changes in V2:
- Improved indentation/formatting.
- Removed _src clocks and misleading code comments.
- Added name fields for power domains and csid register offset in DTSI.
- Dropped minItems field from YAML file.
- Listed changes in alphabetical order.
- Updated description and commit text to reflect changes
- Changed the compatible string from imx412 to imx577.
- Added board-specific enablement changes in the newly created vision
board DTSI file.
- Fixed bug encountered during testing.
- Moved logically independent changes to a new/seprate patch.
- Removed cci0 as no sensor is on this port and MCLK2, which was a
copy-paste error from the RB5 board reference.
- Added power rails, referencing the RB5 board.
- Discarded Patch 5/6 completely (not required).
- Removed unused enums.
- Link to v1: https://lore.kernel.org/linux-arm-msm/20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com/
Suresh Vankadara (1):
media: qcom: camss: Add support for camss driver on sc7280
Vikram Sharma (4):
media: dt-bindings: Add qcom,sc7280-camss
media: qcom: camss: Sort camss version enums and compatible strings
arm64: dts: qcom: sc7280: Add support for camss
arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision
mezzanine
.../bindings/media/qcom,sc7280-camss.yaml | 418 ++++++++++++++++++
arch/arm64/boot/dts/qcom/Makefile | 4 +
.../qcs6490-rb3gen2-vision-mezzanine.dtso | 110 +++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 172 +++++++
.../qcom/camss/camss-csiphy-3ph-1-0.c | 13 +-
.../media/platform/qcom/camss/camss-csiphy.c | 5 +
.../media/platform/qcom/camss/camss-csiphy.h | 1 +
drivers/media/platform/qcom/camss/camss-vfe.c | 8 +-
drivers/media/platform/qcom/camss/camss.c | 321 +++++++++++++-
drivers/media/platform/qcom/camss/camss.h | 5 +-
10 files changed, 1047 insertions(+), 10 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss
2024-12-04 9:59 [PATCH v7 0/5] media: qcom: camss: Add sc7280 support Vikram Sharma
@ 2024-12-04 9:59 ` Vikram Sharma
2024-12-05 8:26 ` Krzysztof Kozlowski
2024-12-05 9:53 ` Bryan O'Donoghue
2024-12-04 10:00 ` [PATCH v7 2/5] media: qcom: camss: Sort camss version enums and compatible strings Vikram Sharma
` (3 subsequent siblings)
4 siblings, 2 replies; 17+ messages in thread
From: Vikram Sharma @ 2024-12-04 9:59 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
Add bindings for qcom,sc7280-camss to support the camera subsystem
on the SC7280 platform.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
.../bindings/media/qcom,sc7280-camss.yaml | 418 ++++++++++++++++++
1 file changed, 418 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
new file mode 100644
index 000000000000..b613dfbc47fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
@@ -0,0 +1,418 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7280 CAMSS ISP
+
+maintainers:
+ - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com>
+ - Hariram Purushothaman <hariramp@quicinc.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sc7280-camss
+
+ reg:
+ maxItems: 15
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ clocks:
+ maxItems: 33
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: cpas_ahb
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: gcc_camera_ahb
+ - const: gcc_cam_hf_axi
+ - const: icp_ahb
+ - const: vfe0
+ - const: vfe0_axi
+ - const: vfe0_cphy_rx
+ - const: vfe0_csid
+ - const: vfe1
+ - const: vfe1_axi
+ - const: vfe1_cphy_rx
+ - const: vfe1_csid
+ - const: vfe2
+ - const: vfe2_axi
+ - const: vfe2_cphy_rx
+ - const: vfe2_csid
+ - const: vfe_lite0
+ - const: vfe_lite0_cphy_rx
+ - const: vfe_lite0_csid
+ - const: vfe_lite1
+ - const: vfe_lite1_cphy_rx
+ - const: vfe_lite1_csid
+
+ interrupts:
+ maxItems: 15
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_0
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSIPHY 0.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSIPHY 1.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSIPHY 2.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSIPHY 3.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ port@4:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSIPHY 4.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,camcc-sc7280.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+ #include <dt-bindings/interconnect/qcom,sc7280.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss@acb3000 {
+ compatible = "qcom,sc7280-camss";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc1000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0accf000 0x0 0x1000>,
+ <0x0 0x0ace0000 0x0 0x2000>,
+ <0x0 0x0ace2000 0x0 0x2000>,
+ <0x0 0x0ace4000 0x0 0x2000>,
+ <0x0 0x0ace6000 0x0 0x2000>,
+ <0x0 0x0ace8000 0x0 0x2000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acbd000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0accb000 0x0 0x4000>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_AXI_CLK>,
+ <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_2_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_camera_ahb",
+ "gcc_cam_hf_axi",
+ "icp_ahb",
+ "vfe0",
+ "vfe0_axi",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1",
+ "vfe1_axi",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe2",
+ "vfe2_axi",
+ "vfe2_cphy_rx",
+ "vfe2_csid",
+ "vfe_lite0",
+ "vfe_lite0_cphy_rx",
+ "vfe_lite0_csid",
+ "vfe_lite1",
+ "vfe_lite1_cphy_rx",
+ "vfe_lite1_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "ahb", "hf_0";
+
+ iommus = <&apps_smmu 0x800 0x4e0>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_IFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0", "ife1", "ife2", "top";
+
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v7 2/5] media: qcom: camss: Sort camss version enums and compatible strings
2024-12-04 9:59 [PATCH v7 0/5] media: qcom: camss: Add sc7280 support Vikram Sharma
2024-12-04 9:59 ` [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss Vikram Sharma
@ 2024-12-04 10:00 ` Vikram Sharma
2024-12-04 10:00 ` [PATCH v7 3/5] media: qcom: camss: Add support for camss driver on sc7280 Vikram Sharma
` (2 subsequent siblings)
4 siblings, 0 replies; 17+ messages in thread
From: Vikram Sharma @ 2024-12-04 10:00 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
Sort CAMSS version enums and compatible strings alphanumerically.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 10 +++++-----
drivers/media/platform/qcom/camss/camss-vfe.c | 6 +++---
drivers/media/platform/qcom/camss/camss.c | 2 +-
drivers/media/platform/qcom/camss/camss.h | 4 ++--
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index df7e93a5a4f6..7d2490c9de01 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -505,10 +505,6 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
u32 val;
switch (csiphy->camss->res->version) {
- case CAMSS_845:
- r = &lane_regs_sdm845[0][0];
- array_size = ARRAY_SIZE(lane_regs_sdm845[0]);
- break;
case CAMSS_8250:
r = &lane_regs_sm8250[0][0];
array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
@@ -517,6 +513,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
r = &lane_regs_sc8280xp[0][0];
array_size = ARRAY_SIZE(lane_regs_sc8280xp[0]);
break;
+ case CAMSS_845:
+ r = &lane_regs_sdm845[0][0];
+ array_size = ARRAY_SIZE(lane_regs_sdm845[0]);
+ break;
default:
WARN(1, "unknown cspi version\n");
return;
@@ -557,9 +557,9 @@ static bool csiphy_is_gen2(u32 version)
bool ret = false;
switch (version) {
- case CAMSS_845:
case CAMSS_8250:
case CAMSS_8280XP:
+ case CAMSS_845:
ret = true;
break;
}
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 80a62ba11295..fb3234c65403 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -334,11 +334,11 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
return sink_code;
}
break;
- case CAMSS_8x96:
case CAMSS_660:
- case CAMSS_845:
+ case CAMSS_8x96:
case CAMSS_8250:
case CAMSS_8280XP:
+ case CAMSS_845:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
{
@@ -1693,9 +1693,9 @@ static int vfe_bpl_align(struct vfe_device *vfe)
int ret = 8;
switch (vfe->camss->res->version) {
- case CAMSS_845:
case CAMSS_8250:
case CAMSS_8280XP:
+ case CAMSS_845:
ret = 16;
break;
default:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 9fb31f4c18ad..f5704c23766a 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2626,10 +2626,10 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
+ { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
- { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ }
};
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 9da7f48f5dd7..ffce0a0edbc5 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -77,13 +77,13 @@ enum pm_domain {
};
enum camss_version {
+ CAMSS_660,
CAMSS_8x16,
CAMSS_8x53,
CAMSS_8x96,
- CAMSS_660,
- CAMSS_845,
CAMSS_8250,
CAMSS_8280XP,
+ CAMSS_845,
};
enum icc_count {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v7 3/5] media: qcom: camss: Add support for camss driver on sc7280
2024-12-04 9:59 [PATCH v7 0/5] media: qcom: camss: Add sc7280 support Vikram Sharma
2024-12-04 9:59 ` [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss Vikram Sharma
2024-12-04 10:00 ` [PATCH v7 2/5] media: qcom: camss: Sort camss version enums and compatible strings Vikram Sharma
@ 2024-12-04 10:00 ` Vikram Sharma
2024-12-06 7:51 ` Luca Weiss
2024-12-04 10:00 ` [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
2024-12-04 10:00 ` [PATCH v7 5/5] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma
4 siblings, 1 reply; 17+ messages in thread
From: Vikram Sharma @ 2024-12-04 10:00 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
From: Suresh Vankadara <quic_svankada@quicinc.com>
Add support for the camss driver on the sc7280 soc.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../qcom/camss/camss-csiphy-3ph-1-0.c | 5 +
.../media/platform/qcom/camss/camss-csiphy.c | 5 +
.../media/platform/qcom/camss/camss-csiphy.h | 1 +
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 319 ++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
6 files changed, 333 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 7d2490c9de01..f341f7b7fd8a 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
u32 val;
switch (csiphy->camss->res->version) {
+ case CAMSS_7280:
+ r = &lane_regs_sm8250[0][0];
+ array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
+ break;
case CAMSS_8250:
r = &lane_regs_sm8250[0][0];
array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
@@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version)
bool ret = false;
switch (version) {
+ case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
case CAMSS_845:
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
index 5af2b382a843..3791c2d8a6cf 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
@@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = {
.formats = formats_8x96
};
+const struct csiphy_formats csiphy_formats_sc7280 = {
+ .nformats = ARRAY_SIZE(formats_sdm845),
+ .formats = formats_sdm845
+};
+
const struct csiphy_formats csiphy_formats_sdm845 = {
.nformats = ARRAY_SIZE(formats_sdm845),
.formats = formats_sdm845
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
index eebc1ff1cfab..b6209bddfb61 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.h
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
@@ -111,6 +111,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
extern const struct csiphy_formats csiphy_formats_8x16;
extern const struct csiphy_formats csiphy_formats_8x96;
+extern const struct csiphy_formats csiphy_formats_sc7280;
extern const struct csiphy_formats csiphy_formats_sdm845;
extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index fb3234c65403..95f6a1ac7eaf 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -335,6 +335,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
}
break;
case CAMSS_660:
+ case CAMSS_7280:
case CAMSS_8x96:
case CAMSS_8250:
case CAMSS_8280XP:
@@ -1693,6 +1694,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
int ret = 8;
switch (vfe->camss->res->version) {
+ case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
case CAMSS_845:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index f5704c23766a..4fa16ff6e614 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -1266,6 +1266,310 @@ static const struct resources_icc icc_res_sm8250[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_7280[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy3", "csiphy3_timer" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+ /* CSIPHY4 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy4", "csiphy4_timer" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy4" },
+ .interrupt = { "csiphy4" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sc7280
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_7280[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+
+ .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 0 },
+ { 380000000, 510000000, 637000000, 760000000 }
+ },
+
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+
+ .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 0 },
+ { 380000000, 510000000, 637000000, 760000000 }
+ },
+
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+
+ .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 0 },
+ { 380000000, 510000000, 637000000, 760000000 }
+ },
+
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID3 */
+ {
+ .regulators = {},
+
+ .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 0 },
+ { 320000000, 400000000, 480000000, 600000000 }
+ },
+
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID4 */
+ {
+ .regulators = {},
+
+ .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
+ .clock_rate = { { 300000000, 400000000 },
+ { 0 },
+ { 320000000, 400000000, 480000000, 600000000 }
+ },
+
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_7280[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+
+ .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe0",
+ "vfe0_axi", "gcc_cam_hf_axi" },
+ .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
+ { 80000000 },
+ { 0 },
+ { 380000000, 510000000, 637000000, 760000000 },
+ { 0 },
+ { 0 } },
+
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+
+ .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe1",
+ "vfe1_axi", "gcc_cam_hf_axi" },
+ .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
+ { 80000000 },
+ { 0 },
+ { 380000000, 510000000, 637000000, 760000000 },
+ { 0 },
+ { 0 } },
+
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 */
+ {
+ .regulators = {},
+
+ .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe2",
+ "vfe2_axi", "gcc_cam_hf_axi" },
+ .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
+ { 80000000 },
+ { 0 },
+ { 380000000, 510000000, 637000000, 760000000 },
+ { 0 },
+ { 0 } },
+
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .hw_ops = &vfe_ops_170,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 (lite) */
+ {
+ .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
+ "vfe_lite0", "gcc_cam_hf_axi" },
+ .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
+ { 80000000 },
+ { 0 },
+ { 320000000, 400000000, 480000000, 600000000 },
+ { 0 } },
+
+ .regulators = {},
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE4 (lite) */
+ {
+ .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
+ "vfe_lite1", "gcc_cam_hf_axi" },
+ .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
+ { 80000000 },
+ { 0 },
+ { 320000000, 400000000, 480000000, 600000000 },
+ { 0 } },
+
+ .regulators = {},
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
+static const struct resources_icc icc_res_sc7280[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_0",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_sc8280xp[] = {
/* CSIPHY0 */
{
@@ -2622,10 +2926,25 @@ static const struct camss_resources sc8280xp_resources = {
.link_entities = camss_link_entities
};
+static const struct camss_resources sc7280_resources = {
+ .version = CAMSS_7280,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_7280,
+ .csid_res = csid_res_7280,
+ .vfe_res = vfe_res_7280,
+ .icc_res = icc_res_sc7280,
+ .icc_path_num = ARRAY_SIZE(icc_res_sc7280),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_7280),
+ .csid_num = ARRAY_SIZE(csid_res_7280),
+ .vfe_num = ARRAY_SIZE(vfe_res_7280),
+ .link_entities = camss_link_entities
+};
+
static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
+ { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index ffce0a0edbc5..9a046eea334f 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -78,6 +78,7 @@ enum pm_domain {
enum camss_version {
CAMSS_660,
+ CAMSS_7280,
CAMSS_8x16,
CAMSS_8x53,
CAMSS_8x96,
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss
2024-12-04 9:59 [PATCH v7 0/5] media: qcom: camss: Add sc7280 support Vikram Sharma
` (2 preceding siblings ...)
2024-12-04 10:00 ` [PATCH v7 3/5] media: qcom: camss: Add support for camss driver on sc7280 Vikram Sharma
@ 2024-12-04 10:00 ` Vikram Sharma
2024-12-05 9:35 ` Bryan O'Donoghue
` (2 more replies)
2024-12-04 10:00 ` [PATCH v7 5/5] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma
4 siblings, 3 replies; 17+ messages in thread
From: Vikram Sharma @ 2024-12-04 10:00 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
Add changes to support the camera subsystem on the SC7280.
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 172 +++++++++++++++++++++++++++
1 file changed, 172 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 55db1c83ef55..e363996602d6 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -4426,6 +4426,178 @@ cci1_i2c1: i2c-bus@1 {
};
};
+ camss: camss@acb3000 {
+ compatible = "qcom,sc7280-camss";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc1000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0accf000 0x0 0x1000>,
+ <0x0 0x0ace0000 0x0 0x2000>,
+ <0x0 0x0ace2000 0x0 0x2000>,
+ <0x0 0x0ace4000 0x0 0x2000>,
+ <0x0 0x0ace6000 0x0 0x2000>,
+ <0x0 0x0ace8000 0x0 0x2000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acbd000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0accb000 0x0 0x4000>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_AXI_CLK>,
+ <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_2_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_camera_ahb",
+ "gcc_cam_hf_axi",
+ "icp_ahb",
+ "vfe0",
+ "vfe0_axi",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1",
+ "vfe1_axi",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe2",
+ "vfe2_axi",
+ "vfe2_cphy_rx",
+ "vfe2_csid",
+ "vfe_lite0",
+ "vfe_lite0_cphy_rx",
+ "vfe_lite0_csid",
+ "vfe_lite1",
+ "vfe_lite1_cphy_rx",
+ "vfe_lite1_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "ahb", "hf_0";
+
+ iommus = <&apps_smmu 0x800 0x4e0>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_IFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0", "ife1", "ife2", "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sc7280-camcc";
reg = <0 0x0ad00000 0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v7 5/5] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine
2024-12-04 9:59 [PATCH v7 0/5] media: qcom: camss: Add sc7280 support Vikram Sharma
` (3 preceding siblings ...)
2024-12-04 10:00 ` [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
@ 2024-12-04 10:00 ` Vikram Sharma
2024-12-05 16:30 ` Konrad Dybcio
4 siblings, 1 reply; 17+ messages in thread
From: Vikram Sharma @ 2024-12-04 10:00 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
The Vision Mezzanine for the RB3 ships with an imx577 camera sensor.
Enable the IMX577 on the vision mezzanine.
An example media-ctl pipeline for the imx577 is:
media-ctl --reset
media-ctl -v -V '"imx577 '19-001a'":0[fmt:SRGGB10/4056x3040 field:none]'
media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]'
media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]'
media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0
Signed-off-by: Hariram Purushothaman <quic_hariramp@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/Makefile | 4 +
.../qcs6490-rb3gen2-vision-mezzanine.dtso | 110 ++++++++++++++++++
2 files changed, 114 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 9bb8b191aeb5..4ee57b3871dd 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -114,6 +114,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
+
+qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso
new file mode 100644
index 000000000000..d6085637d0c3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/*
+ * Camera Sensor overlay on top of rb3gen2 core kit.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,camcc-sc7280.h>
+
+/dts-v1/;
+/plugin/;
+
+&camcc {
+ status = "okay";
+};
+
+&camss {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* The port index denotes CSIPHY id i.e. csiphy3 */
+ port@3 {
+ reg = <3>;
+ csiphy3_ep: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&imx577_ep>;
+ };
+ };
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@1a {
+ compatible = "sony,imx577";
+ reg = <0x1a>;
+
+ reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "suspend";
+ pinctrl-0 = <&cam2_default>;
+ pinctrl-1 = <&cam2_suspend>;
+
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ dovdd-supply = <&vreg_l18b_1p8>;
+ avdd-supply = <&vph_pwr>;
+ dvdd-supply = <&vph_pwr>;
+
+ port {
+ imx577_ep: endpoint {
+ clock-lanes = <7>;
+ link-frequencies = /bits/ 64 <600000000>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&csiphy3_ep>;
+ };
+ };
+ };
+};
+
+&tlmm {
+ cam2_default: cam2-default-state {
+ rst-pins {
+ pins = "gpio78";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mclk-pins {
+ pins = "gpio67";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cam2_suspend: cam2-suspend-state {
+ rst-pins {
+ pins = "gpio78";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+
+ mclk-pins {
+ pins = "gpio67";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss
2024-12-04 9:59 ` [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss Vikram Sharma
@ 2024-12-05 8:26 ` Krzysztof Kozlowski
[not found] ` <eaffa633-c3a4-4924-8ba7-694b18bf92ee@quicinc.com>
2024-12-05 9:53 ` Bryan O'Donoghue
1 sibling, 1 reply; 17+ messages in thread
From: Krzysztof Kozlowski @ 2024-12-05 8:26 UTC (permalink / raw)
To: Vikram Sharma
Cc: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will,
linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On Wed, Dec 04, 2024 at 03:29:59PM +0530, Vikram Sharma wrote:
> Add bindings for qcom,sc7280-camss to support the camera subsystem
> on the SC7280 platform.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> .../bindings/media/qcom,sc7280-camss.yaml | 418 ++++++++++++++++++
> 1 file changed, 418 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
>
...
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,camcc-sc7280.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> + #include <dt-bindings/interconnect/qcom,sc7280.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss@acb3000 {
If there is going to be resend, then node name: isp
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss
2024-12-04 10:00 ` [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
@ 2024-12-05 9:35 ` Bryan O'Donoghue
2024-12-05 16:28 ` Konrad Dybcio
2024-12-06 7:51 ` Luca Weiss
2 siblings, 0 replies; 17+ messages in thread
From: Bryan O'Donoghue @ 2024-12-05 9:35 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
akapatra, hariramp, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On 04/12/2024 10:00, Vikram Sharma wrote:
> Add changes to support the camera subsystem on the SC7280.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 172 +++++++++++++++++++++++++++
> 1 file changed, 172 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 55db1c83ef55..e363996602d6 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss
2024-12-04 9:59 ` [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss Vikram Sharma
2024-12-05 8:26 ` Krzysztof Kozlowski
@ 2024-12-05 9:53 ` Bryan O'Donoghue
1 sibling, 0 replies; 17+ messages in thread
From: Bryan O'Donoghue @ 2024-12-05 9:53 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
akapatra, hariramp, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On 04/12/2024 09:59, Vikram Sharma wrote:
> Add bindings for qcom,sc7280-camss to support the camera subsystem
> on the SC7280 platform.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss
[not found] ` <eaffa633-c3a4-4924-8ba7-694b18bf92ee@quicinc.com>
@ 2024-12-05 11:56 ` Bryan O'Donoghue
2024-12-05 12:58 ` Vikram Sharma
0 siblings, 1 reply; 17+ messages in thread
From: Bryan O'Donoghue @ 2024-12-05 11:56 UTC (permalink / raw)
To: Vikram Sharma, Krzysztof Kozlowski
Cc: rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt, akapatra,
hariramp, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will, linux-arm-kernel,
linux-media, linux-arm-msm, devicetree, linux-kernel, kernel
On 05/12/2024 10:59, Vikram Sharma wrote:
> Hi Krzysztof,
>
> Thanks for your "Reviewed-by"
>
> + camss@acb3000 {
>
> If there is going to be resend, then node name: isp
>
> Sure, we will change node-name from camss to isp or camera (As its a
> part of generic names recommendation as per the shared link.)
> If there is a resend. or we will address this as a followup.
>
> So
>
> - camss@acb3000 {
> + camera@acb3000 {
>
> Best Regards,
> Vikram
Please no top-posting.
https://subspace.kernel.org/etiquette.html
Shouldn't that be isp@0xaddress ?
If you are making this change, please remember to do it in both the
example and the dts.
---
bod
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss
2024-12-05 11:56 ` Bryan O'Donoghue
@ 2024-12-05 12:58 ` Vikram Sharma
0 siblings, 0 replies; 17+ messages in thread
From: Vikram Sharma @ 2024-12-05 12:58 UTC (permalink / raw)
To: Bryan O'Donoghue, Krzysztof Kozlowski
Cc: rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt, akapatra,
hariramp, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will, linux-arm-kernel,
linux-media, linux-arm-msm, devicetree, linux-kernel, kernel
On 12/5/2024 5:26 PM, Bryan O'Donoghue wrote:
> On 05/12/2024 10:59, Vikram Sharma wrote:
>> Hi Krzysztof,
>>
>> Thanks for your "Reviewed-by"
>>
>> + camss@acb3000 {
>>
>> If there is going to be resend, then node name: isp
>>
>> Sure, we will change node-name from camss to isp or camera (As its a
>> part of generic names recommendation as per the shared link.)
>> If there is a resend. or we will address this as a followup.
>>
>> So
>>
>> - camss@acb3000 {
>> + camera@acb3000 {
>>
>> Best Regards,
>> Vikram
>
> Please no top-posting.
> https://subspace.kernel.org/etiquette.html
>
> Shouldn't that be isp@0xaddress ?
ACK.
- camss@acb3000 {
+ isp@acb3000 {
In both YAML and DTS. If we post V8.
>
> If you are making this change, please remember to do it in both the
> example and the dts.
Understood. Will avoid this.
>
> ---
> bod
Best Regards,
Vikram
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss
2024-12-04 10:00 ` [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
2024-12-05 9:35 ` Bryan O'Donoghue
@ 2024-12-05 16:28 ` Konrad Dybcio
2024-12-06 19:27 ` Vikram Sharma
2024-12-06 7:51 ` Luca Weiss
2 siblings, 1 reply; 17+ messages in thread
From: Konrad Dybcio @ 2024-12-05 16:28 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh,
krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On 4.12.2024 11:00 AM, Vikram Sharma wrote:
> Add changes to support the camera subsystem on the SC7280.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
[...]
(isp@ as mentioned)
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
QCOM_ICC_TAG_ACTIVE_ONLY
> + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
QCOM_ICC_TAG_ALWAYS
> + interconnect-names = "ahb", "hf_0";
> +
> + iommus = <&apps_smmu 0x800 0x4e0>;
> +
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_IFE_1_GDSC>,
> + <&camcc CAM_CC_IFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "ife0", "ife1", "ife2", "top";
vertical list, please
Konrad
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 5/5] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine
2024-12-04 10:00 ` [PATCH v7 5/5] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma
@ 2024-12-05 16:30 ` Konrad Dybcio
0 siblings, 0 replies; 17+ messages in thread
From: Konrad Dybcio @ 2024-12-05 16:30 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh,
krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On 4.12.2024 11:00 AM, Vikram Sharma wrote:
> The Vision Mezzanine for the RB3 ships with an imx577 camera sensor.
> Enable the IMX577 on the vision mezzanine.
>
> An example media-ctl pipeline for the imx577 is:
>
> media-ctl --reset
> media-ctl -v -V '"imx577 '19-001a'":0[fmt:SRGGB10/4056x3040 field:none]'
> media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]'
> media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]'
> media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]'
> media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]'
> media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
>
> yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0
>
> Signed-off-by: Hariram Purushothaman <quic_hariramp@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
[...]
> +&camcc {
> + status = "okay";
> +};
It's already enabled
> +
> +&camss {
> + vdda-phy-supply = <&vreg_l10c_0p88>;
> + vdda-pll-supply = <&vreg_l6b_1p2>;
> + status = "okay";
A newline before status is expected
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* The port index denotes CSIPHY id i.e. csiphy3 */
> + port@3 {
> + reg = <3>;
> + csiphy3_ep: endpoint {
Also between last property and subnode
[...]
> +
> +&tlmm {
> + cam2_default: cam2-default-state {
> + rst-pins {
> + pins = "gpio78";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + mclk-pins {
> + pins = "gpio67";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
Please sort these by gpio idx
Konrad
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 3/5] media: qcom: camss: Add support for camss driver on sc7280
2024-12-04 10:00 ` [PATCH v7 3/5] media: qcom: camss: Add support for camss driver on sc7280 Vikram Sharma
@ 2024-12-06 7:51 ` Luca Weiss
2024-12-06 19:26 ` Vikram Sharma
0 siblings, 1 reply; 17+ messages in thread
From: Luca Weiss @ 2024-12-06 7:51 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh,
krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On Wed Dec 4, 2024 at 11:00 AM CET, Vikram Sharma wrote:
> From: Suresh Vankadara <quic_svankada@quicinc.com>
>
> Add support for the camss driver on the sc7280 soc.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Hi Vikram,
This is working on QCM6490 Fairphone 5 smartphone with WIP drivers for
IMX858 and S5KJN1, thanks!
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5
Regards
Luca
> ---
> .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 +
> .../media/platform/qcom/camss/camss-csiphy.c | 5 +
> .../media/platform/qcom/camss/camss-csiphy.h | 1 +
> drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
> drivers/media/platform/qcom/camss/camss.c | 319 ++++++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 6 files changed, 333 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index 7d2490c9de01..f341f7b7fd8a 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
> u32 val;
>
> switch (csiphy->camss->res->version) {
> + case CAMSS_7280:
> + r = &lane_regs_sm8250[0][0];
> + array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
> + break;
> case CAMSS_8250:
> r = &lane_regs_sm8250[0][0];
> array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
> @@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version)
> bool ret = false;
>
> switch (version) {
> + case CAMSS_7280:
> case CAMSS_8250:
> case CAMSS_8280XP:
> case CAMSS_845:
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
> index 5af2b382a843..3791c2d8a6cf 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
> @@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = {
> .formats = formats_8x96
> };
>
> +const struct csiphy_formats csiphy_formats_sc7280 = {
> + .nformats = ARRAY_SIZE(formats_sdm845),
> + .formats = formats_sdm845
> +};
> +
> const struct csiphy_formats csiphy_formats_sdm845 = {
> .nformats = ARRAY_SIZE(formats_sdm845),
> .formats = formats_sdm845
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
> index eebc1ff1cfab..b6209bddfb61 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy.h
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
> @@ -111,6 +111,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
>
> extern const struct csiphy_formats csiphy_formats_8x16;
> extern const struct csiphy_formats csiphy_formats_8x96;
> +extern const struct csiphy_formats csiphy_formats_sc7280;
> extern const struct csiphy_formats csiphy_formats_sdm845;
>
> extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index fb3234c65403..95f6a1ac7eaf 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -335,6 +335,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> }
> break;
> case CAMSS_660:
> + case CAMSS_7280:
> case CAMSS_8x96:
> case CAMSS_8250:
> case CAMSS_8280XP:
> @@ -1693,6 +1694,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
> int ret = 8;
>
> switch (vfe->camss->res->version) {
> + case CAMSS_7280:
> case CAMSS_8250:
> case CAMSS_8280XP:
> case CAMSS_845:
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index f5704c23766a..4fa16ff6e614 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -1266,6 +1266,310 @@ static const struct resources_icc icc_res_sm8250[] = {
> },
> };
>
> +static const struct camss_subdev_resources csiphy_res_7280[] = {
> + /* CSIPHY0 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
> + .clock = { "csiphy0", "csiphy0_timer" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 300000000 } },
> + .reg = { "csiphy0" },
> + .interrupt = { "csiphy0" },
> + .csiphy = {
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sc7280
> + }
> + },
> + /* CSIPHY1 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
> + .clock = { "csiphy1", "csiphy1_timer" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 300000000 } },
> + .reg = { "csiphy1" },
> + .interrupt = { "csiphy1" },
> + .csiphy = {
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sc7280
> + }
> + },
> + /* CSIPHY2 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
> + .clock = { "csiphy2", "csiphy2_timer" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 300000000 } },
> + .reg = { "csiphy2" },
> + .interrupt = { "csiphy2" },
> + .csiphy = {
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sc7280
> + }
> + },
> + /* CSIPHY3 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
> + .clock = { "csiphy3", "csiphy3_timer" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 300000000 } },
> + .reg = { "csiphy3" },
> + .interrupt = { "csiphy3" },
> + .csiphy = {
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sc7280
> + }
> + },
> + /* CSIPHY4 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
> + .clock = { "csiphy4", "csiphy4_timer" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 300000000 } },
> + .reg = { "csiphy4" },
> + .interrupt = { "csiphy4" },
> + .csiphy = {
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sc7280
> + }
> + },
> +};
> +
> +static const struct camss_subdev_resources csid_res_7280[] = {
> + /* CSID0 */
> + {
> + .regulators = {},
> +
> + .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 0 },
> + { 380000000, 510000000, 637000000, 760000000 }
> + },
> +
> + .reg = { "csid0" },
> + .interrupt = { "csid0" },
> + .csid = {
> + .is_lite = false,
> + .hw_ops = &csid_ops_gen2,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID1 */
> + {
> + .regulators = {},
> +
> + .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 0 },
> + { 380000000, 510000000, 637000000, 760000000 }
> + },
> +
> + .reg = { "csid1" },
> + .interrupt = { "csid1" },
> + .csid = {
> + .is_lite = false,
> + .hw_ops = &csid_ops_gen2,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID2 */
> + {
> + .regulators = {},
> +
> + .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 0 },
> + { 380000000, 510000000, 637000000, 760000000 }
> + },
> +
> + .reg = { "csid2" },
> + .interrupt = { "csid2" },
> + .csid = {
> + .is_lite = false,
> + .hw_ops = &csid_ops_gen2,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID3 */
> + {
> + .regulators = {},
> +
> + .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 0 },
> + { 320000000, 400000000, 480000000, 600000000 }
> + },
> +
> + .reg = { "csid_lite0" },
> + .interrupt = { "csid_lite0" },
> + .csid = {
> + .is_lite = true,
> + .hw_ops = &csid_ops_gen2,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID4 */
> + {
> + .regulators = {},
> +
> + .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
> + .clock_rate = { { 300000000, 400000000 },
> + { 0 },
> + { 320000000, 400000000, 480000000, 600000000 }
> + },
> +
> + .reg = { "csid_lite1" },
> + .interrupt = { "csid_lite1" },
> + .csid = {
> + .is_lite = true,
> + .hw_ops = &csid_ops_gen2,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> +};
> +
> +static const struct camss_subdev_resources vfe_res_7280[] = {
> + /* VFE0 */
> + {
> + .regulators = {},
> +
> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe0",
> + "vfe0_axi", "gcc_cam_hf_axi" },
> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
> + { 80000000 },
> + { 0 },
> + { 380000000, 510000000, 637000000, 760000000 },
> + { 0 },
> + { 0 } },
> +
> + .reg = { "vfe0" },
> + .interrupt = { "vfe0" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .has_pd = true,
> + .pd_name = "ife0",
> + .hw_ops = &vfe_ops_170,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE1 */
> + {
> + .regulators = {},
> +
> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe1",
> + "vfe1_axi", "gcc_cam_hf_axi" },
> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
> + { 80000000 },
> + { 0 },
> + { 380000000, 510000000, 637000000, 760000000 },
> + { 0 },
> + { 0 } },
> +
> + .reg = { "vfe1" },
> + .interrupt = { "vfe1" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .has_pd = true,
> + .pd_name = "ife1",
> + .hw_ops = &vfe_ops_170,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE2 */
> + {
> + .regulators = {},
> +
> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe2",
> + "vfe2_axi", "gcc_cam_hf_axi" },
> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
> + { 80000000 },
> + { 0 },
> + { 380000000, 510000000, 637000000, 760000000 },
> + { 0 },
> + { 0 } },
> +
> + .reg = { "vfe2" },
> + .interrupt = { "vfe2" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .hw_ops = &vfe_ops_170,
> + .has_pd = true,
> + .pd_name = "ife2",
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE3 (lite) */
> + {
> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
> + "vfe_lite0", "gcc_cam_hf_axi" },
> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
> + { 80000000 },
> + { 0 },
> + { 320000000, 400000000, 480000000, 600000000 },
> + { 0 } },
> +
> + .regulators = {},
> + .reg = { "vfe_lite0" },
> + .interrupt = { "vfe_lite0" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_170,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE4 (lite) */
> + {
> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
> + "vfe_lite1", "gcc_cam_hf_axi" },
> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
> + { 80000000 },
> + { 0 },
> + { 320000000, 400000000, 480000000, 600000000 },
> + { 0 } },
> +
> + .regulators = {},
> + .reg = { "vfe_lite1" },
> + .interrupt = { "vfe_lite1" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_170,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> +};
> +
> +static const struct resources_icc icc_res_sc7280[] = {
> + {
> + .name = "ahb",
> + .icc_bw_tbl.avg = 38400,
> + .icc_bw_tbl.peak = 76800,
> + },
> + {
> + .name = "hf_0",
> + .icc_bw_tbl.avg = 2097152,
> + .icc_bw_tbl.peak = 2097152,
> + },
> +};
> +
> static const struct camss_subdev_resources csiphy_res_sc8280xp[] = {
> /* CSIPHY0 */
> {
> @@ -2622,10 +2926,25 @@ static const struct camss_resources sc8280xp_resources = {
> .link_entities = camss_link_entities
> };
>
> +static const struct camss_resources sc7280_resources = {
> + .version = CAMSS_7280,
> + .pd_name = "top",
> + .csiphy_res = csiphy_res_7280,
> + .csid_res = csid_res_7280,
> + .vfe_res = vfe_res_7280,
> + .icc_res = icc_res_sc7280,
> + .icc_path_num = ARRAY_SIZE(icc_res_sc7280),
> + .csiphy_num = ARRAY_SIZE(csiphy_res_7280),
> + .csid_num = ARRAY_SIZE(csid_res_7280),
> + .vfe_num = ARRAY_SIZE(vfe_res_7280),
> + .link_entities = camss_link_entities
> +};
> +
> static const struct of_device_id camss_dt_match[] = {
> { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
> { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
> { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
> + { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
> { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
> { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
> { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
> index ffce0a0edbc5..9a046eea334f 100644
> --- a/drivers/media/platform/qcom/camss/camss.h
> +++ b/drivers/media/platform/qcom/camss/camss.h
> @@ -78,6 +78,7 @@ enum pm_domain {
>
> enum camss_version {
> CAMSS_660,
> + CAMSS_7280,
> CAMSS_8x16,
> CAMSS_8x53,
> CAMSS_8x96,
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss
2024-12-04 10:00 ` [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
2024-12-05 9:35 ` Bryan O'Donoghue
2024-12-05 16:28 ` Konrad Dybcio
@ 2024-12-06 7:51 ` Luca Weiss
2 siblings, 0 replies; 17+ messages in thread
From: Luca Weiss @ 2024-12-06 7:51 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh,
krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On Wed Dec 4, 2024 at 11:00 AM CET, Vikram Sharma wrote:
> Add changes to support the camera subsystem on the SC7280.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Hi Vikram,
This is working on QCM6490 Fairphone 5 smartphone with WIP drivers for
IMX858 and S5KJN1, thanks!
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5
Regards
Luca
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 172 +++++++++++++++++++++++++++
> 1 file changed, 172 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 55db1c83ef55..e363996602d6 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -4426,6 +4426,178 @@ cci1_i2c1: i2c-bus@1 {
> };
> };
>
> + camss: camss@acb3000 {
> + compatible = "qcom,sc7280-camss";
> +
> + reg = <0x0 0x0acb3000 0x0 0x1000>,
> + <0x0 0x0acba000 0x0 0x1000>,
> + <0x0 0x0acc1000 0x0 0x1000>,
> + <0x0 0x0acc8000 0x0 0x1000>,
> + <0x0 0x0accf000 0x0 0x1000>,
> + <0x0 0x0ace0000 0x0 0x2000>,
> + <0x0 0x0ace2000 0x0 0x2000>,
> + <0x0 0x0ace4000 0x0 0x2000>,
> + <0x0 0x0ace6000 0x0 0x2000>,
> + <0x0 0x0ace8000 0x0 0x2000>,
> + <0x0 0x0acaf000 0x0 0x4000>,
> + <0x0 0x0acb6000 0x0 0x4000>,
> + <0x0 0x0acbd000 0x0 0x4000>,
> + <0x0 0x0acc4000 0x0 0x4000>,
> + <0x0 0x0accb000 0x0 0x4000>;
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_ICP_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_2_CLK>,
> + <&camcc CAM_CC_IFE_2_AXI_CLK>,
> + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_2_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "gcc_camera_ahb",
> + "gcc_cam_hf_axi",
> + "icp_ahb",
> + "vfe0",
> + "vfe0_axi",
> + "vfe0_cphy_rx",
> + "vfe0_csid",
> + "vfe1",
> + "vfe1_axi",
> + "vfe1_cphy_rx",
> + "vfe1_csid",
> + "vfe2",
> + "vfe2_axi",
> + "vfe2_cphy_rx",
> + "vfe2_csid",
> + "vfe_lite0",
> + "vfe_lite0_cphy_rx",
> + "vfe_lite0_csid",
> + "vfe_lite1",
> + "vfe_lite1_cphy_rx",
> + "vfe_lite1_csid";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
> + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "ahb", "hf_0";
> +
> + iommus = <&apps_smmu 0x800 0x4e0>;
> +
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_IFE_1_GDSC>,
> + <&camcc CAM_CC_IFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "ife0", "ife1", "ife2", "top";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + };
> +
> + port@4 {
> + reg = <4>;
> + };
> + };
> + };
> +
> camcc: clock-controller@ad00000 {
> compatible = "qcom,sc7280-camcc";
> reg = <0 0x0ad00000 0 0x10000>;
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 3/5] media: qcom: camss: Add support for camss driver on sc7280
2024-12-06 7:51 ` Luca Weiss
@ 2024-12-06 19:26 ` Vikram Sharma
0 siblings, 0 replies; 17+ messages in thread
From: Vikram Sharma @ 2024-12-06 19:26 UTC (permalink / raw)
To: Luca Weiss, rfoss, todor.too, bryan.odonoghue, mchehab, robh,
krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On 12/6/2024 1:21 PM, Luca Weiss wrote:
> On Wed Dec 4, 2024 at 11:00 AM CET, Vikram Sharma wrote:
>> From: Suresh Vankadara <quic_svankada@quicinc.com>
>>
>> Add support for the camss driver on the sc7280 soc.
>>
>> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
>> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Hi Vikram,
>
> This is working on QCM6490 Fairphone 5 smartphone with WIP drivers for
> IMX858 and S5KJN1, thanks!
>
> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5
>
> Regards
> Luca
Hi Luca,
Thanks for your help in testing this on 2 different sensors.
I have posted V8 for this adding "Tested-by" tag with your name.
Best Regards,
Vikram
>
>> ---
>> .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 +
>> .../media/platform/qcom/camss/camss-csiphy.c | 5 +
>> .../media/platform/qcom/camss/camss-csiphy.h | 1 +
>> drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
>> drivers/media/platform/qcom/camss/camss.c | 319 ++++++++++++++++++
>> drivers/media/platform/qcom/camss/camss.h | 1 +
>> 6 files changed, 333 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> index 7d2490c9de01..f341f7b7fd8a 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> @@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
>> u32 val;
>>
>> switch (csiphy->camss->res->version) {
>> + case CAMSS_7280:
>> + r = &lane_regs_sm8250[0][0];
>> + array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
>> + break;
>> case CAMSS_8250:
>> r = &lane_regs_sm8250[0][0];
>> array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
>> @@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version)
>> bool ret = false;
>>
>> switch (version) {
>> + case CAMSS_7280:
>> case CAMSS_8250:
>> case CAMSS_8280XP:
>> case CAMSS_845:
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
>> index 5af2b382a843..3791c2d8a6cf 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
>> @@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = {
>> .formats = formats_8x96
>> };
>>
>> +const struct csiphy_formats csiphy_formats_sc7280 = {
>> + .nformats = ARRAY_SIZE(formats_sdm845),
>> + .formats = formats_sdm845
>> +};
>> +
>> const struct csiphy_formats csiphy_formats_sdm845 = {
>> .nformats = ARRAY_SIZE(formats_sdm845),
>> .formats = formats_sdm845
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
>> index eebc1ff1cfab..b6209bddfb61 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy.h
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
>> @@ -111,6 +111,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
>>
>> extern const struct csiphy_formats csiphy_formats_8x16;
>> extern const struct csiphy_formats csiphy_formats_8x96;
>> +extern const struct csiphy_formats csiphy_formats_sc7280;
>> extern const struct csiphy_formats csiphy_formats_sdm845;
>>
>> extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
>> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
>> index fb3234c65403..95f6a1ac7eaf 100644
>> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
>> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
>> @@ -335,6 +335,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
>> }
>> break;
>> case CAMSS_660:
>> + case CAMSS_7280:
>> case CAMSS_8x96:
>> case CAMSS_8250:
>> case CAMSS_8280XP:
>> @@ -1693,6 +1694,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
>> int ret = 8;
>>
>> switch (vfe->camss->res->version) {
>> + case CAMSS_7280:
>> case CAMSS_8250:
>> case CAMSS_8280XP:
>> case CAMSS_845:
>> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
>> index f5704c23766a..4fa16ff6e614 100644
>> --- a/drivers/media/platform/qcom/camss/camss.c
>> +++ b/drivers/media/platform/qcom/camss/camss.c
>> @@ -1266,6 +1266,310 @@ static const struct resources_icc icc_res_sm8250[] = {
>> },
>> };
>>
>> +static const struct camss_subdev_resources csiphy_res_7280[] = {
>> + /* CSIPHY0 */
>> + {
>> + .regulators = { "vdda-phy", "vdda-pll" },
>> +
>> + .clock = { "csiphy0", "csiphy0_timer" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 300000000 } },
>> + .reg = { "csiphy0" },
>> + .interrupt = { "csiphy0" },
>> + .csiphy = {
>> + .hw_ops = &csiphy_ops_3ph_1_0,
>> + .formats = &csiphy_formats_sc7280
>> + }
>> + },
>> + /* CSIPHY1 */
>> + {
>> + .regulators = { "vdda-phy", "vdda-pll" },
>> +
>> + .clock = { "csiphy1", "csiphy1_timer" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 300000000 } },
>> + .reg = { "csiphy1" },
>> + .interrupt = { "csiphy1" },
>> + .csiphy = {
>> + .hw_ops = &csiphy_ops_3ph_1_0,
>> + .formats = &csiphy_formats_sc7280
>> + }
>> + },
>> + /* CSIPHY2 */
>> + {
>> + .regulators = { "vdda-phy", "vdda-pll" },
>> +
>> + .clock = { "csiphy2", "csiphy2_timer" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 300000000 } },
>> + .reg = { "csiphy2" },
>> + .interrupt = { "csiphy2" },
>> + .csiphy = {
>> + .hw_ops = &csiphy_ops_3ph_1_0,
>> + .formats = &csiphy_formats_sc7280
>> + }
>> + },
>> + /* CSIPHY3 */
>> + {
>> + .regulators = { "vdda-phy", "vdda-pll" },
>> +
>> + .clock = { "csiphy3", "csiphy3_timer" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 300000000 } },
>> + .reg = { "csiphy3" },
>> + .interrupt = { "csiphy3" },
>> + .csiphy = {
>> + .hw_ops = &csiphy_ops_3ph_1_0,
>> + .formats = &csiphy_formats_sc7280
>> + }
>> + },
>> + /* CSIPHY4 */
>> + {
>> + .regulators = { "vdda-phy", "vdda-pll" },
>> +
>> + .clock = { "csiphy4", "csiphy4_timer" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 300000000 } },
>> + .reg = { "csiphy4" },
>> + .interrupt = { "csiphy4" },
>> + .csiphy = {
>> + .hw_ops = &csiphy_ops_3ph_1_0,
>> + .formats = &csiphy_formats_sc7280
>> + }
>> + },
>> +};
>> +
>> +static const struct camss_subdev_resources csid_res_7280[] = {
>> + /* CSID0 */
>> + {
>> + .regulators = {},
>> +
>> + .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 0 },
>> + { 380000000, 510000000, 637000000, 760000000 }
>> + },
>> +
>> + .reg = { "csid0" },
>> + .interrupt = { "csid0" },
>> + .csid = {
>> + .is_lite = false,
>> + .hw_ops = &csid_ops_gen2,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> + /* CSID1 */
>> + {
>> + .regulators = {},
>> +
>> + .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 0 },
>> + { 380000000, 510000000, 637000000, 760000000 }
>> + },
>> +
>> + .reg = { "csid1" },
>> + .interrupt = { "csid1" },
>> + .csid = {
>> + .is_lite = false,
>> + .hw_ops = &csid_ops_gen2,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> + /* CSID2 */
>> + {
>> + .regulators = {},
>> +
>> + .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 0 },
>> + { 380000000, 510000000, 637000000, 760000000 }
>> + },
>> +
>> + .reg = { "csid2" },
>> + .interrupt = { "csid2" },
>> + .csid = {
>> + .is_lite = false,
>> + .hw_ops = &csid_ops_gen2,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> + /* CSID3 */
>> + {
>> + .regulators = {},
>> +
>> + .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 0 },
>> + { 320000000, 400000000, 480000000, 600000000 }
>> + },
>> +
>> + .reg = { "csid_lite0" },
>> + .interrupt = { "csid_lite0" },
>> + .csid = {
>> + .is_lite = true,
>> + .hw_ops = &csid_ops_gen2,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> + /* CSID4 */
>> + {
>> + .regulators = {},
>> +
>> + .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
>> + .clock_rate = { { 300000000, 400000000 },
>> + { 0 },
>> + { 320000000, 400000000, 480000000, 600000000 }
>> + },
>> +
>> + .reg = { "csid_lite1" },
>> + .interrupt = { "csid_lite1" },
>> + .csid = {
>> + .is_lite = true,
>> + .hw_ops = &csid_ops_gen2,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> +};
>> +
>> +static const struct camss_subdev_resources vfe_res_7280[] = {
>> + /* VFE0 */
>> + {
>> + .regulators = {},
>> +
>> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe0",
>> + "vfe0_axi", "gcc_cam_hf_axi" },
>> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
>> + { 80000000 },
>> + { 0 },
>> + { 380000000, 510000000, 637000000, 760000000 },
>> + { 0 },
>> + { 0 } },
>> +
>> + .reg = { "vfe0" },
>> + .interrupt = { "vfe0" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .has_pd = true,
>> + .pd_name = "ife0",
>> + .hw_ops = &vfe_ops_170,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE1 */
>> + {
>> + .regulators = {},
>> +
>> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe1",
>> + "vfe1_axi", "gcc_cam_hf_axi" },
>> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
>> + { 80000000 },
>> + { 0 },
>> + { 380000000, 510000000, 637000000, 760000000 },
>> + { 0 },
>> + { 0 } },
>> +
>> + .reg = { "vfe1" },
>> + .interrupt = { "vfe1" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .has_pd = true,
>> + .pd_name = "ife1",
>> + .hw_ops = &vfe_ops_170,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE2 */
>> + {
>> + .regulators = {},
>> +
>> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe2",
>> + "vfe2_axi", "gcc_cam_hf_axi" },
>> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
>> + { 80000000 },
>> + { 0 },
>> + { 380000000, 510000000, 637000000, 760000000 },
>> + { 0 },
>> + { 0 } },
>> +
>> + .reg = { "vfe2" },
>> + .interrupt = { "vfe2" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .hw_ops = &vfe_ops_170,
>> + .has_pd = true,
>> + .pd_name = "ife2",
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE3 (lite) */
>> + {
>> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
>> + "vfe_lite0", "gcc_cam_hf_axi" },
>> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
>> + { 80000000 },
>> + { 0 },
>> + { 320000000, 400000000, 480000000, 600000000 },
>> + { 0 } },
>> +
>> + .regulators = {},
>> + .reg = { "vfe_lite0" },
>> + .interrupt = { "vfe_lite0" },
>> + .vfe = {
>> + .line_num = 4,
>> + .is_lite = true,
>> + .hw_ops = &vfe_ops_170,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE4 (lite) */
>> + {
>> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
>> + "vfe_lite1", "gcc_cam_hf_axi" },
>> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
>> + { 80000000 },
>> + { 0 },
>> + { 320000000, 400000000, 480000000, 600000000 },
>> + { 0 } },
>> +
>> + .regulators = {},
>> + .reg = { "vfe_lite1" },
>> + .interrupt = { "vfe_lite1" },
>> + .vfe = {
>> + .line_num = 4,
>> + .is_lite = true,
>> + .hw_ops = &vfe_ops_170,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> +};
>> +
>> +static const struct resources_icc icc_res_sc7280[] = {
>> + {
>> + .name = "ahb",
>> + .icc_bw_tbl.avg = 38400,
>> + .icc_bw_tbl.peak = 76800,
>> + },
>> + {
>> + .name = "hf_0",
>> + .icc_bw_tbl.avg = 2097152,
>> + .icc_bw_tbl.peak = 2097152,
>> + },
>> +};
>> +
>> static const struct camss_subdev_resources csiphy_res_sc8280xp[] = {
>> /* CSIPHY0 */
>> {
>> @@ -2622,10 +2926,25 @@ static const struct camss_resources sc8280xp_resources = {
>> .link_entities = camss_link_entities
>> };
>>
>> +static const struct camss_resources sc7280_resources = {
>> + .version = CAMSS_7280,
>> + .pd_name = "top",
>> + .csiphy_res = csiphy_res_7280,
>> + .csid_res = csid_res_7280,
>> + .vfe_res = vfe_res_7280,
>> + .icc_res = icc_res_sc7280,
>> + .icc_path_num = ARRAY_SIZE(icc_res_sc7280),
>> + .csiphy_num = ARRAY_SIZE(csiphy_res_7280),
>> + .csid_num = ARRAY_SIZE(csid_res_7280),
>> + .vfe_num = ARRAY_SIZE(vfe_res_7280),
>> + .link_entities = camss_link_entities
>> +};
>> +
>> static const struct of_device_id camss_dt_match[] = {
>> { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
>> { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
>> { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
>> + { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
>> { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
>> { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
>> { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
>> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
>> index ffce0a0edbc5..9a046eea334f 100644
>> --- a/drivers/media/platform/qcom/camss/camss.h
>> +++ b/drivers/media/platform/qcom/camss/camss.h
>> @@ -78,6 +78,7 @@ enum pm_domain {
>>
>> enum camss_version {
>> CAMSS_660,
>> + CAMSS_7280,
>> CAMSS_8x16,
>> CAMSS_8x53,
>> CAMSS_8x96,
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss
2024-12-05 16:28 ` Konrad Dybcio
@ 2024-12-06 19:27 ` Vikram Sharma
0 siblings, 0 replies; 17+ messages in thread
From: Vikram Sharma @ 2024-12-06 19:27 UTC (permalink / raw)
To: Konrad Dybcio, rfoss, todor.too, bryan.odonoghue, mchehab, robh,
krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree,
linux-kernel, kernel
On 12/5/2024 9:58 PM, Konrad Dybcio wrote:
> On 4.12.2024 11:00 AM, Vikram Sharma wrote:
>> Add changes to support the camera subsystem on the SC7280.
>>
>> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
>> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com>
>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
>> ---
> [...]
>
> (isp@ as mentioned)
Hi Konrad,
Thanks for your review and comments.
I have posted V8 addressing these comments.
Best Regards,
Vikram
>
>> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
> QCOM_ICC_TAG_ACTIVE_ONLY
>
>> + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
> QCOM_ICC_TAG_ALWAYS
>
>> + interconnect-names = "ahb", "hf_0";
>> +
>> + iommus = <&apps_smmu 0x800 0x4e0>;
>> +
>> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
>> + <&camcc CAM_CC_IFE_1_GDSC>,
>> + <&camcc CAM_CC_IFE_2_GDSC>,
>> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
>> + power-domain-names = "ife0", "ife1", "ife2", "top";
> vertical list, please
>
> Konrad
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2024-12-06 19:28 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-12-04 9:59 [PATCH v7 0/5] media: qcom: camss: Add sc7280 support Vikram Sharma
2024-12-04 9:59 ` [PATCH v7 1/5] media: dt-bindings: Add qcom,sc7280-camss Vikram Sharma
2024-12-05 8:26 ` Krzysztof Kozlowski
[not found] ` <eaffa633-c3a4-4924-8ba7-694b18bf92ee@quicinc.com>
2024-12-05 11:56 ` Bryan O'Donoghue
2024-12-05 12:58 ` Vikram Sharma
2024-12-05 9:53 ` Bryan O'Donoghue
2024-12-04 10:00 ` [PATCH v7 2/5] media: qcom: camss: Sort camss version enums and compatible strings Vikram Sharma
2024-12-04 10:00 ` [PATCH v7 3/5] media: qcom: camss: Add support for camss driver on sc7280 Vikram Sharma
2024-12-06 7:51 ` Luca Weiss
2024-12-06 19:26 ` Vikram Sharma
2024-12-04 10:00 ` [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
2024-12-05 9:35 ` Bryan O'Donoghue
2024-12-05 16:28 ` Konrad Dybcio
2024-12-06 19:27 ` Vikram Sharma
2024-12-06 7:51 ` Luca Weiss
2024-12-04 10:00 ` [PATCH v7 5/5] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma
2024-12-05 16:30 ` Konrad Dybcio
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