* [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
2022-06-27 0:52 ` [PATCH 0/3] fixes for exynosautov9 clock Chanho Park
@ 2022-06-27 0:52 ` Chanho Park
2022-06-27 11:33 ` Krzysztof Kozlowski
2022-06-27 0:52 ` [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1 Chanho Park
2022-06-27 0:52 ` [PATCH 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1 Chanho Park
2 siblings, 1 reply; 12+ messages in thread
From: Chanho Park @ 2022-06-27 0:52 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel, Chanho Park
There are duplicated definitions of peric0 and peric1 cmu blocks. Thus,
they should be defined correctly as numerical order.
Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
.../dt-bindings/clock/samsung,exynosautov9.h | 56 +++++++++----------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index ea9f91b4eb1a..a7db6516593f 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -226,21 +226,21 @@
#define CLK_GOUT_PERIC0_IPCLK_8 28
#define CLK_GOUT_PERIC0_IPCLK_9 29
#define CLK_GOUT_PERIC0_IPCLK_10 30
-#define CLK_GOUT_PERIC0_IPCLK_11 30
-#define CLK_GOUT_PERIC0_PCLK_0 31
-#define CLK_GOUT_PERIC0_PCLK_1 32
-#define CLK_GOUT_PERIC0_PCLK_2 33
-#define CLK_GOUT_PERIC0_PCLK_3 34
-#define CLK_GOUT_PERIC0_PCLK_4 35
-#define CLK_GOUT_PERIC0_PCLK_5 36
-#define CLK_GOUT_PERIC0_PCLK_6 37
-#define CLK_GOUT_PERIC0_PCLK_7 38
-#define CLK_GOUT_PERIC0_PCLK_8 39
-#define CLK_GOUT_PERIC0_PCLK_9 40
-#define CLK_GOUT_PERIC0_PCLK_10 41
-#define CLK_GOUT_PERIC0_PCLK_11 42
+#define CLK_GOUT_PERIC0_IPCLK_11 31
+#define CLK_GOUT_PERIC0_PCLK_0 32
+#define CLK_GOUT_PERIC0_PCLK_1 33
+#define CLK_GOUT_PERIC0_PCLK_2 34
+#define CLK_GOUT_PERIC0_PCLK_3 35
+#define CLK_GOUT_PERIC0_PCLK_4 36
+#define CLK_GOUT_PERIC0_PCLK_5 37
+#define CLK_GOUT_PERIC0_PCLK_6 38
+#define CLK_GOUT_PERIC0_PCLK_7 39
+#define CLK_GOUT_PERIC0_PCLK_8 40
+#define CLK_GOUT_PERIC0_PCLK_9 41
+#define CLK_GOUT_PERIC0_PCLK_10 42
+#define CLK_GOUT_PERIC0_PCLK_11 43
-#define PERIC0_NR_CLK 43
+#define PERIC0_NR_CLK 44
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER 1
@@ -272,21 +272,21 @@
#define CLK_GOUT_PERIC1_IPCLK_8 28
#define CLK_GOUT_PERIC1_IPCLK_9 29
#define CLK_GOUT_PERIC1_IPCLK_10 30
-#define CLK_GOUT_PERIC1_IPCLK_11 30
-#define CLK_GOUT_PERIC1_PCLK_0 31
-#define CLK_GOUT_PERIC1_PCLK_1 32
-#define CLK_GOUT_PERIC1_PCLK_2 33
-#define CLK_GOUT_PERIC1_PCLK_3 34
-#define CLK_GOUT_PERIC1_PCLK_4 35
-#define CLK_GOUT_PERIC1_PCLK_5 36
-#define CLK_GOUT_PERIC1_PCLK_6 37
-#define CLK_GOUT_PERIC1_PCLK_7 38
-#define CLK_GOUT_PERIC1_PCLK_8 39
-#define CLK_GOUT_PERIC1_PCLK_9 40
-#define CLK_GOUT_PERIC1_PCLK_10 41
-#define CLK_GOUT_PERIC1_PCLK_11 42
+#define CLK_GOUT_PERIC1_IPCLK_11 31
+#define CLK_GOUT_PERIC1_PCLK_0 32
+#define CLK_GOUT_PERIC1_PCLK_1 33
+#define CLK_GOUT_PERIC1_PCLK_2 34
+#define CLK_GOUT_PERIC1_PCLK_3 35
+#define CLK_GOUT_PERIC1_PCLK_4 36
+#define CLK_GOUT_PERIC1_PCLK_5 37
+#define CLK_GOUT_PERIC1_PCLK_6 38
+#define CLK_GOUT_PERIC1_PCLK_7 39
+#define CLK_GOUT_PERIC1_PCLK_8 40
+#define CLK_GOUT_PERIC1_PCLK_9 41
+#define CLK_GOUT_PERIC1_PCLK_10 42
+#define CLK_GOUT_PERIC1_PCLK_11 43
-#define PERIC1_NR_CLK 43
+#define PERIC1_NR_CLK 44
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
2022-06-27 0:52 ` [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 Chanho Park
@ 2022-06-27 11:33 ` Krzysztof Kozlowski
2022-06-28 2:15 ` Chanho Park
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 11:33 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel
On 27/06/2022 02:52, Chanho Park wrote:
> There are duplicated definitions of peric0 and peric1 cmu blocks. Thus,
> they should be defined correctly as numerical order.
>
> Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9")
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> .../dt-bindings/clock/samsung,exynosautov9.h | 56 +++++++++----------
> 1 file changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index ea9f91b4eb1a..a7db6516593f 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -226,21 +226,21 @@
> #define CLK_GOUT_PERIC0_IPCLK_8 28
> #define CLK_GOUT_PERIC0_IPCLK_9 29
> #define CLK_GOUT_PERIC0_IPCLK_10 30
> -#define CLK_GOUT_PERIC0_IPCLK_11 30
> -#define CLK_GOUT_PERIC0_PCLK_0 31
> -#define CLK_GOUT_PERIC0_PCLK_1 32
> -#define CLK_GOUT_PERIC0_PCLK_2 33
> -#define CLK_GOUT_PERIC0_PCLK_3 34
> -#define CLK_GOUT_PERIC0_PCLK_4 35
> -#define CLK_GOUT_PERIC0_PCLK_5 36
> -#define CLK_GOUT_PERIC0_PCLK_6 37
> -#define CLK_GOUT_PERIC0_PCLK_7 38
> -#define CLK_GOUT_PERIC0_PCLK_8 39
> -#define CLK_GOUT_PERIC0_PCLK_9 40
> -#define CLK_GOUT_PERIC0_PCLK_10 41
> -#define CLK_GOUT_PERIC0_PCLK_11 42
> +#define CLK_GOUT_PERIC0_IPCLK_11 31
> +#define CLK_GOUT_PERIC0_PCLK_0 32
> +#define CLK_GOUT_PERIC0_PCLK_1 33
Is this a fix for current cycle? If yes, it's ok, otherwise all other
IDs should not be changed, because it's part of ABI.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
2022-06-27 11:33 ` Krzysztof Kozlowski
@ 2022-06-28 2:15 ` Chanho Park
2022-06-28 10:02 ` Krzysztof Kozlowski
0 siblings, 1 reply; 12+ messages in thread
From: Chanho Park @ 2022-06-28 2:15 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', 'Sylwester Nawrocki',
'Tomasz Figa', 'Chanwoo Choi',
'Stephen Boyd', 'Michael Turquette',
'Rob Herring', 'Krzysztof Kozlowski'
Cc: 'Alim Akhtar', linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel
> Subject: Re: [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock
> numbering of peric0/c1
>
> On 27/06/2022 02:52, Chanho Park wrote:
> > There are duplicated definitions of peric0 and peric1 cmu blocks.
> > Thus, they should be defined correctly as numerical order.
> >
> > Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding
> > definitions for Exynos Auto v9")
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > ---
> > .../dt-bindings/clock/samsung,exynosautov9.h | 56
> > +++++++++----------
> > 1 file changed, 28 insertions(+), 28 deletions(-)
> >
> > diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h
> > b/include/dt-bindings/clock/samsung,exynosautov9.h
> > index ea9f91b4eb1a..a7db6516593f 100644
> > --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> > +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> > @@ -226,21 +226,21 @@
> > #define CLK_GOUT_PERIC0_IPCLK_8 28
> > #define CLK_GOUT_PERIC0_IPCLK_9 29
> > #define CLK_GOUT_PERIC0_IPCLK_10 30
> > -#define CLK_GOUT_PERIC0_IPCLK_11 30
> > -#define CLK_GOUT_PERIC0_PCLK_0 31
> > -#define CLK_GOUT_PERIC0_PCLK_1 32
> > -#define CLK_GOUT_PERIC0_PCLK_2 33
> > -#define CLK_GOUT_PERIC0_PCLK_3 34
> > -#define CLK_GOUT_PERIC0_PCLK_4 35
> > -#define CLK_GOUT_PERIC0_PCLK_5 36
> > -#define CLK_GOUT_PERIC0_PCLK_6 37
> > -#define CLK_GOUT_PERIC0_PCLK_7 38
> > -#define CLK_GOUT_PERIC0_PCLK_8 39
> > -#define CLK_GOUT_PERIC0_PCLK_9 40
> > -#define CLK_GOUT_PERIC0_PCLK_10 41
> > -#define CLK_GOUT_PERIC0_PCLK_11 42
> > +#define CLK_GOUT_PERIC0_IPCLK_11 31
> > +#define CLK_GOUT_PERIC0_PCLK_0 32
> > +#define CLK_GOUT_PERIC0_PCLK_1 33
>
> Is this a fix for current cycle? If yes, it's ok, otherwise all other IDs
> should not be changed, because it's part of ABI.
What is the current cycle? 5.19-rc or 5.20?
I prefer this goes on 5.19-rc but if it's not possible due to the ABI breakage, I'm okay this can be going to v5.20.
Best Regards,
Chanho Park
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
2022-06-28 2:15 ` Chanho Park
@ 2022-06-28 10:02 ` Krzysztof Kozlowski
2022-07-04 7:32 ` Chanho Park
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-28 10:02 UTC (permalink / raw)
To: Chanho Park, 'Sylwester Nawrocki', 'Tomasz Figa',
'Chanwoo Choi', 'Stephen Boyd',
'Michael Turquette', 'Rob Herring',
'Krzysztof Kozlowski'
Cc: 'Alim Akhtar', linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel
On 28/06/2022 04:15, Chanho Park wrote:
>> Subject: Re: [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock
>> numbering of peric0/c1
>>
>> On 27/06/2022 02:52, Chanho Park wrote:
>>> There are duplicated definitions of peric0 and peric1 cmu blocks.
>>> Thus, they should be defined correctly as numerical order.
>>>
>>> Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding
>>> definitions for Exynos Auto v9")
>>> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>>> ---
>>> .../dt-bindings/clock/samsung,exynosautov9.h | 56
>>> +++++++++----------
>>> 1 file changed, 28 insertions(+), 28 deletions(-)
>>>
>>> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h
>>> b/include/dt-bindings/clock/samsung,exynosautov9.h
>>> index ea9f91b4eb1a..a7db6516593f 100644
>>> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
>>> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
>>> @@ -226,21 +226,21 @@
>>> #define CLK_GOUT_PERIC0_IPCLK_8 28
>>> #define CLK_GOUT_PERIC0_IPCLK_9 29
>>> #define CLK_GOUT_PERIC0_IPCLK_10 30
>>> -#define CLK_GOUT_PERIC0_IPCLK_11 30
>>> -#define CLK_GOUT_PERIC0_PCLK_0 31
>>> -#define CLK_GOUT_PERIC0_PCLK_1 32
>>> -#define CLK_GOUT_PERIC0_PCLK_2 33
>>> -#define CLK_GOUT_PERIC0_PCLK_3 34
>>> -#define CLK_GOUT_PERIC0_PCLK_4 35
>>> -#define CLK_GOUT_PERIC0_PCLK_5 36
>>> -#define CLK_GOUT_PERIC0_PCLK_6 37
>>> -#define CLK_GOUT_PERIC0_PCLK_7 38
>>> -#define CLK_GOUT_PERIC0_PCLK_8 39
>>> -#define CLK_GOUT_PERIC0_PCLK_9 40
>>> -#define CLK_GOUT_PERIC0_PCLK_10 41
>>> -#define CLK_GOUT_PERIC0_PCLK_11 42
>>> +#define CLK_GOUT_PERIC0_IPCLK_11 31
>>> +#define CLK_GOUT_PERIC0_PCLK_0 32
>>> +#define CLK_GOUT_PERIC0_PCLK_1 33
>>
>> Is this a fix for current cycle? If yes, it's ok, otherwise all other IDs
>> should not be changed, because it's part of ABI.
>
> What is the current cycle? 5.19-rc or 5.20?
> I prefer this goes on 5.19-rc but if it's not possible due to the ABI breakage, I'm okay this can be going to v5.20.
The change was introduced indeed in v5.19-rc1, so this should go to
current cycle as well (v5.19) and your patch is fine.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Sylwester or Stephen,
Please kindly grab it for fixes.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
2022-06-28 10:02 ` Krzysztof Kozlowski
@ 2022-07-04 7:32 ` Chanho Park
0 siblings, 0 replies; 12+ messages in thread
From: Chanho Park @ 2022-07-04 7:32 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', 'Sylwester Nawrocki',
'Tomasz Figa', 'Chanwoo Choi',
'Stephen Boyd', 'Michael Turquette',
'Rob Herring', 'Krzysztof Kozlowski'
Cc: 'Alim Akhtar', linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel
> Subject: Re: [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock
> numbering of peric0/c1
>
> On 28/06/2022 04:15, Chanho Park wrote:
> >> Subject: Re: [PATCH 1/3] dt-bindings: clock: exynosautov9: correct
> >> clock numbering of peric0/c1
> >>
> >> On 27/06/2022 02:52, Chanho Park wrote:
> >>> There are duplicated definitions of peric0 and peric1 cmu blocks.
> >>> Thus, they should be defined correctly as numerical order.
> >>>
> >>> Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding
> >>> definitions for Exynos Auto v9")
> >>> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> >>> ---
> >>> .../dt-bindings/clock/samsung,exynosautov9.h | 56
> >>> +++++++++----------
> >>> 1 file changed, 28 insertions(+), 28 deletions(-)
> >>>
> >>> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h
> >>> b/include/dt-bindings/clock/samsung,exynosautov9.h
> >>> index ea9f91b4eb1a..a7db6516593f 100644
> >>> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> >>> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> >>> @@ -226,21 +226,21 @@
> >>> #define CLK_GOUT_PERIC0_IPCLK_8 28
> >>> #define CLK_GOUT_PERIC0_IPCLK_9 29
> >>> #define CLK_GOUT_PERIC0_IPCLK_10 30
> >>> -#define CLK_GOUT_PERIC0_IPCLK_11 30
> >>> -#define CLK_GOUT_PERIC0_PCLK_0 31
> >>> -#define CLK_GOUT_PERIC0_PCLK_1 32
> >>> -#define CLK_GOUT_PERIC0_PCLK_2 33
> >>> -#define CLK_GOUT_PERIC0_PCLK_3 34
> >>> -#define CLK_GOUT_PERIC0_PCLK_4 35
> >>> -#define CLK_GOUT_PERIC0_PCLK_5 36
> >>> -#define CLK_GOUT_PERIC0_PCLK_6 37
> >>> -#define CLK_GOUT_PERIC0_PCLK_7 38
> >>> -#define CLK_GOUT_PERIC0_PCLK_8 39
> >>> -#define CLK_GOUT_PERIC0_PCLK_9 40
> >>> -#define CLK_GOUT_PERIC0_PCLK_10 41
> >>> -#define CLK_GOUT_PERIC0_PCLK_11 42
> >>> +#define CLK_GOUT_PERIC0_IPCLK_11 31
> >>> +#define CLK_GOUT_PERIC0_PCLK_0 32
> >>> +#define CLK_GOUT_PERIC0_PCLK_1 33
> >>
> >> Is this a fix for current cycle? If yes, it's ok, otherwise all other
> >> IDs should not be changed, because it's part of ABI.
> >
> > What is the current cycle? 5.19-rc or 5.20?
> > I prefer this goes on 5.19-rc but if it's not possible due to the ABI
> breakage, I'm okay this can be going to v5.20.
>
> The change was introduced indeed in v5.19-rc1, so this should go to
> current cycle as well (v5.19) and your patch is fine.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Sylwester or Stephen,
>
> Please kindly grab it for fixes.
Hi Sylwester or Stephen,
Gently ping to not miss this in v5.19 rc cycle.
Below patch as well.
https://lore.kernel.org/linux-clk/7415fba0-ac04-e764-aa46-2c63b8568ac3@gmail.com/
Thanks.
Best Regards,
Chanho Park
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1
2022-06-27 0:52 ` [PATCH 0/3] fixes for exynosautov9 clock Chanho Park
2022-06-27 0:52 ` [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 Chanho Park
@ 2022-06-27 0:52 ` Chanho Park
2022-06-27 11:30 ` Krzysztof Kozlowski
2022-06-27 0:52 ` [PATCH 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1 Chanho Park
2 siblings, 1 reply; 12+ messages in thread
From: Chanho Park @ 2022-06-27 0:52 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel, Chanho Park
"gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0
and peric1 respectively.
Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support")
Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index d9e1f8e4a7b4..c5a4e1bee711 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1330,6 +1330,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1",
+ "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
+ 21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
@@ -1581,6 +1585,10 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1",
+ "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
+ 21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1
2022-06-27 0:52 ` [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1 Chanho Park
@ 2022-06-27 11:30 ` Krzysztof Kozlowski
2022-06-28 2:10 ` Chanho Park
0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 11:30 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel
On 27/06/2022 02:52, Chanho Park wrote:
> "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0
> and peric1 respectively.
Where is exactly the bug? The commit msg suggests that they were added
to different block, but there is no code removal.
>
> Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support")
> Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support")
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1
2022-06-27 11:30 ` Krzysztof Kozlowski
@ 2022-06-28 2:10 ` Chanho Park
2022-06-28 6:58 ` Krzysztof Kozlowski
0 siblings, 1 reply; 12+ messages in thread
From: Chanho Park @ 2022-06-28 2:10 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', 'Sylwester Nawrocki',
'Tomasz Figa', 'Chanwoo Choi',
'Stephen Boyd', 'Michael Turquette',
'Rob Herring', 'Krzysztof Kozlowski'
Cc: 'Alim Akhtar', linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel
> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks
> for peric0/c1
>
> On 27/06/2022 02:52, Chanho Park wrote:
> > "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to
> > peric0 and peric1 respectively.
>
> Where is exactly the bug? The commit msg suggests that they were added to
> different block, but there is no code removal.
I thought they should be added from previous patch because clock IDs were existing without implementations.
I can drop fixes tags next patchset.
Best Regards,
Chanho Park
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1
2022-06-28 2:10 ` Chanho Park
@ 2022-06-28 6:58 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-28 6:58 UTC (permalink / raw)
To: Chanho Park, 'Sylwester Nawrocki', 'Tomasz Figa',
'Chanwoo Choi', 'Stephen Boyd',
'Michael Turquette', 'Rob Herring',
'Krzysztof Kozlowski'
Cc: 'Alim Akhtar', linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel
On 28/06/2022 04:10, Chanho Park wrote:
>> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks
>> for peric0/c1
>>
>> On 27/06/2022 02:52, Chanho Park wrote:
>>> "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to
>>> peric0 and peric1 respectively.
>>
>> Where is exactly the bug? The commit msg suggests that they were added to
>> different block, but there is no code removal.
>
> I thought they should be added from previous patch because clock IDs were existing without implementations.
> I can drop fixes tags next patchset.
The clock IDs as bindings can be added upfront - it's independent from
implementation. Please drop the fixes.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1
2022-06-27 0:52 ` [PATCH 0/3] fixes for exynosautov9 clock Chanho Park
2022-06-27 0:52 ` [PATCH 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 Chanho Park
2022-06-27 0:52 ` [PATCH 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1 Chanho Park
@ 2022-06-27 0:52 ` Chanho Park
2022-06-27 11:31 ` Krzysztof Kozlowski
2 siblings, 1 reply; 12+ messages in thread
From: Chanho Park @ 2022-06-27 0:52 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel, Chanho Park
Some register offsets of peric0 and peric1 cmu blocks need to be
corrected and re-ordered by numerical order.
Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support")
Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/samsung/clk-exynosautov9.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index c5a4e1bee711..76c4841f2970 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1170,9 +1170,9 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
-#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
@@ -1422,14 +1422,14 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2058
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x205c
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2060
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x206c
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2064
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2068
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2070
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2074
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
@@ -1467,9 +1467,9 @@ static const unsigned long peric1_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
- CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1
2022-06-27 0:52 ` [PATCH 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1 Chanho Park
@ 2022-06-27 11:31 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 11:31 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel
On 27/06/2022 02:52, Chanho Park wrote:
> Some register offsets of peric0 and peric1 cmu blocks need to be
> corrected and re-ordered by numerical order.
>
> Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support")
> Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support")
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread