Re: [PATCH v3 00/18] clk: qcom: Add support to attach multiple power domains in cc probe

["Rob Herring (Arm)" <robh@kernel.org>]

On Thu, 27 Mar 2025 15:22:20 +0530, Jagadeesh Kona wrote:
> In recent QCOM chipsets, PLLs require more than one power domain to be
> kept ON to configure the PLL. But the current code doesn't enable all
> the required power domains while configuring the PLLs, this leads to
> functional issues due to suboptimal settings of PLLs.
> 
> To address this, add support for handling runtime power management,
> configuring plls and enabling critical clocks from qcom_cc_really_probe.
> The clock controller can specify PLLs, critical clocks, and runtime PM
> requirements in the descriptor data. The code in qcom_cc_really_probe()
> ensures all necessary power domains are enabled before configuring PLLs
> or critical clocks.
> 
> This series fixes the below warning reported in SM8550 venus testing due
> to video_cc_pll0 not properly getting configured during videocc probe
> 
> [   46.535132] Lucid PLL latch failed. Output may be unstable!
> 
> The patch adding support to configure the PLLs from common code is
> picked from below series and updated it.
> https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/
> 
> This series is dependent on bindings patch in below Vladimir's series, hence
> included the Vladimir's series patches also in this series and updated them.
> https://lore.kernel.org/all/20250303225521.1780611-1-vladimir.zapolskiy@linaro.org/
> 
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
> Changes in v3:
>  - Updated the videocc bindings patch to add required-opps for MXC power domain [Dmitry]
>    and added Bryan & Rob R/A-By tags received for this patch on v1.
>  - Included the Vladimir's bindings patch for SM8450 camcc bindings to
>    add multiple PD support and updated them to fix the bot warnings.
>  - Moved SC8280XP camcc bindings to SA8775P camcc since SC8280XP only
>    require single MMCX power domain
>  - Split runtime PM and PLL configuration to separate patches [Dmitry]
>  - Removed direct regmap_update_bits to configure clock CBCR's and
>    using clock helpers to configure the CBCR registers [Dmitry, Bryan]
>  - Added new helpers to configure all PLLs & update misc clock
>    register settings from common code [Dmitry, Bryan]
>  - Updated the name of qcom_clk_cfg structure to qcom_clk_reg_setting [Konrad]
>  - Updated the fields in structure from unsigned int to u32 and added
>    val field to this structure [Konrad]
>  - Added a new u32 array for cbcr branch clocks & num_clk_cbcrs fields
>    to maintain the list of critical clock cbcrs in clock controller
>    descriptor [Konrad]
>  - Updated the plls field to alpha_plls in descriptor structure [Konrad]
>  - Added WARN() in PLL configure function if PLL type passed is not
>    supported. The suggestion is to use BUG(), but updated it to
>    WARN() to avoid checkpatch warning. [Bjorn]
>  - Moved the pll configure and helper macros to PLL code from common code [Bjorn]
>  - Updated camcc drivers for SM8450, SM8550, SM8650 and X1E80100 targets
>    with support to configure PLLs from common code and added MXC power
>    domain in corresponding camcc DT nodes. [Bryan]
>  - Added Dmitry and Bryan R-By tags received on videocc DT node changes in v1
>  - Link to v2: https://lore.kernel.org/r/20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com
> 
> Changes in v2:
>  - Added support to handle rpm, PLL configuration and enable critical
>    clocks from qcom_cc_really_probe() in common code as per v1 commments
>    from Bryan, Konrad and Dmitry
>  - Added patches to configure PLLs from common code
>  - Updated the SM8450, SM8550 videocc patches to use the newly
>    added support to handle rpm, configure PLLs from common code
>  - Split the DT change for each target separately as per
>    Dmitry comments
>  - Added R-By and A-By tags received on v1
> - Link to v1: https://lore.kernel.org/r/20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com
> 
> ---
> Jagadeesh Kona (15):
>       dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
>       dt-bindings: clock: qcom: Update sc8280xp camcc bindings
>       clk: qcom: common: Handle runtime power management in qcom_cc_really_probe
>       clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe
>       clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe
>       clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe
>       clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe
>       clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe
>       clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe
>       clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe
>       arm64: dts: qcom: Add MXC power domain to videocc node on SM8450
>       arm64: dts: qcom: Add MXC power domain to videocc node on SM8550
>       arm64: dts: qcom: Add MXC power domain to videocc node on SM8650
>       arm64: dts: qcom: Add MXC power domain to camcc node on SM8450
>       arm64: dts: qcom: Add MXC power domain to camcc node on SM8650
> 
> Taniya Das (1):
>       clk: qcom: clk-alpha-pll: Add support for common PLL configuration function
> 
> Vladimir Zapolskiy (2):
>       dt-bindings: clock: qcom: sm8450-camcc: Allow to specify two power domains
>       arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc
> 
>  .../bindings/clock/qcom,sa8775p-camcc.yaml         |  2 +
>  .../bindings/clock/qcom,sm8450-camcc.yaml          | 20 +++--
>  .../bindings/clock/qcom,sm8450-videocc.yaml        | 18 +++--
>  arch/arm64/boot/dts/qcom/sm8450.dtsi               | 12 ++-
>  arch/arm64/boot/dts/qcom/sm8550.dtsi               | 12 ++-
>  arch/arm64/boot/dts/qcom/sm8650.dtsi               |  6 +-
>  drivers/clk/qcom/camcc-sm8450.c                    | 85 ++++++++++------------
>  drivers/clk/qcom/camcc-sm8550.c                    | 81 ++++++++++-----------
>  drivers/clk/qcom/camcc-sm8650.c                    | 79 ++++++++++----------
>  drivers/clk/qcom/camcc-x1e80100.c                  | 63 +++++++---------
>  drivers/clk/qcom/clk-alpha-pll.c                   | 63 ++++++++++++++++
>  drivers/clk/qcom/clk-alpha-pll.h                   |  3 +
>  drivers/clk/qcom/common.c                          | 65 ++++++++++++++---
>  drivers/clk/qcom/common.h                          | 20 +++++
>  drivers/clk/qcom/videocc-sm8450.c                  | 54 ++++++--------
>  drivers/clk/qcom/videocc-sm8550.c                  | 55 ++++++--------
>  16 files changed, 377 insertions(+), 261 deletions(-)
> ---
> base-commit: 138cfc44b3c4a5fb800388c6e27be169970fb9f7
> change-id: 20250218-videocc-pll-multi-pd-voting-d614dce910e7
> 
> Best regards,
> --
> Jagadeesh Kona <quic_jkona@quicinc.com>
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: base-commit 138cfc44b3c4a5fb800388c6e27be169970fb9f7 not known, ignoring
 Base: attempting to guess base-commit...
 Base: tags/next-20250327 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com:

arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dtb: clock-controller@ad00000: Unevaluated properties are not allowed ('required-opps' was unexpected)
	from schema $id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dtb: clock-controller@ad00000: Unevaluated properties are not allowed ('required-opps' was unexpected)
	from schema $id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
arch/arm64/boot/dts/qcom/sa8295p-adp.dtb: clock-controller@ad00000: Unevaluated properties are not allowed ('required-opps' was unexpected)
	from schema $id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dtb: clock-controller@ad00000: Unevaluated properties are not allowed ('required-opps' was unexpected)
	from schema $id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dtb: clock-controller@ad00000: Unevaluated properties are not allowed ('required-opps' was unexpected)
	from schema $id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
arch/arm64/boot/dts/qcom/sc8280xp-crd.dtb: clock-controller@ad00000: Unevaluated properties are not allowed ('required-opps' was unexpected)
	from schema $id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: clock-controller@ad00000: Unevaluated properties are not allowed ('required-opps' was unexpected)
	from schema $id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#