[PATCH v2 0/3] clk: meson: Fix an issue with inaccurate hifi_pll frequency

[PATCH v2 0/3] clk: meson: Fix an issue with inaccurate hifi_pll frequency

[Chuan Liu via B4 Relay]

Some PLLS with fractional multipliers have fractional denominators with
fixed values, instead of the previous "(1 << pll-> frc.width)".

The hifi_pll for both C3 and S4 supports a fractional multiplier and has
a fixed fractional denominator of "100000".

Here are the results of the C3-based command tests (already defined
CLOCK_ALLOW_WRITE_DEBUGFS):
* echo 491520000 > /sys/kernel/debug/clk/hifi_pll/clk_rate
* cat /sys/kernel/debug/clk/hifi_pll/clk_rate
491520000
* echo 1 > /sys/kernel/debug/clk/hifi_pll/clk_prepare_enable
* cat /sys/kernel/debug/meson-clk-msr/clks/hifi_pll_clk
491515625       +/-15625Hz
* devmem 0xfe008100 32
0xD00304A3
* devmem 0xfe008104 32
0x00014820

Based on the register information read above, it can be obtained:
m = 0xA3 = 0d163;
n = 0x1 = 0d1
frac = 0x14820 = 0d84000
od = 0x3 = 0d3

hifi_pll calculates the output frequency:
calc_rate = xtal_rate / n * (m + (frac / frac_max)) >> od;
calc_rate = 24000000 / 1 * (163 + (84000 / 100000)) >> 3;
calc_rate = 491520000

clk_rate, msr_rate, and calc_rate all match.

The test and calculation results of S4 are consistent with those of C3,
which will not be repeated here.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
Changes in v2:
- Added frac_max to the pll parameter instead of flag.
- frac_max is added to hifi_pll for C3 and S4.
- Link to v1: https://lore.kernel.org/r/20240906-fix_clk-v1-0-2977ef0d72e7@amlogic.com

---
Chuan Liu (3):
      clk: meson: Support PLL with fixed fractional denominators
      clk: meson: c3: pll: fix frac maximum value for hifi_pll
      clk: meson: s4: pll: fix frac maximum value for hifi_pll

 drivers/clk/meson/c3-pll.c  | 1 +
 drivers/clk/meson/clk-pll.c | 8 +++++---
 drivers/clk/meson/clk-pll.h | 1 +
 drivers/clk/meson/s4-pll.c  | 1 +
 4 files changed, 8 insertions(+), 3 deletions(-)
---
base-commit: 80344f4c1a1edec507a20adca476af84ea58cd4c
change-id: 20240904-fix_clk-668f7a1a2b16

Best regards,
-- 
Chuan Liu <chuan.liu@amlogic.com>

[PATCH v2 1/3] clk: meson: Support PLL with fixed fractional denominators

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Some PLLS with fractional multipliers have fractional denominators with
fixed values, instead of the previous "(1 << pll-> frc.width)".

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 drivers/clk/meson/clk-pll.c | 8 +++++---
 drivers/clk/meson/clk-pll.h | 1 +
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index bc570a2ff3a3..a141ab450009 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -57,12 +57,13 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate,
 					  struct meson_clk_pll_data *pll)
 {
 	u64 rate = (u64)parent_rate * m;
+	unsigned int frac_max = unlikely(pll->frac_max) ? pll->frac_max :
+							  (1 << pll->frac.width);
 
 	if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
 		u64 frac_rate = (u64)parent_rate * frac;
 
-		rate += DIV_ROUND_UP_ULL(frac_rate,
-					 (1 << pll->frac.width));
+		rate += DIV_ROUND_UP_ULL(frac_rate, frac_max);
 	}
 
 	return DIV_ROUND_UP_ULL(rate, n);
@@ -100,7 +101,8 @@ static unsigned int __pll_params_with_frac(unsigned long rate,
 					   unsigned int n,
 					   struct meson_clk_pll_data *pll)
 {
-	unsigned int frac_max = (1 << pll->frac.width);
+	unsigned int frac_max = unlikely(pll->frac_max) ? pll->frac_max :
+							  (1 << pll->frac.width);
 	u64 val = (u64)rate * n;
 
 	/* Bail out if we are already over the requested rate */
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 7b6b87274073..949157fb7bf5 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -43,6 +43,7 @@ struct meson_clk_pll_data {
 	unsigned int init_count;
 	const struct pll_params_table *table;
 	const struct pll_mult_range *range;
+	unsigned int frac_max;
 	u8 flags;
 };
 

-- 
2.42.0

Re: [PATCH v2 1/3] clk: meson: Support PLL with fixed fractional denominators

[Jerome Brunet]

On Fri 06 Sep 2024 at 18:34, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org> wrote:

> From: Chuan Liu <chuan.liu@amlogic.com>
>
> Some PLLS with fractional multipliers have fractional denominators with
> fixed values, instead of the previous "(1 << pll-> frc.width)".
>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
>  drivers/clk/meson/clk-pll.c | 8 +++++---
>  drivers/clk/meson/clk-pll.h | 1 +
>  2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
> index bc570a2ff3a3..a141ab450009 100644
> --- a/drivers/clk/meson/clk-pll.c
> +++ b/drivers/clk/meson/clk-pll.c
> @@ -57,12 +57,13 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate,
>  					  struct meson_clk_pll_data *pll)
>  {
>  	u64 rate = (u64)parent_rate * m;
> +	unsigned int frac_max = unlikely(pll->frac_max) ? pll->frac_max
> :
                                 ^ Please don't play with this unless
                                 you've got justification a for it.

By justification, I mean actual numbers showing the difference it makes
and not just for the platforms listed in this series, but all the
platforms supported by this driver.

> +							  (1 << pll->frac.width);
>  
>  	if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
>  		u64 frac_rate = (u64)parent_rate * frac;
>  
> -		rate += DIV_ROUND_UP_ULL(frac_rate,
> -					 (1 << pll->frac.width));
> +		rate += DIV_ROUND_UP_ULL(frac_rate, frac_max);
>  	}
>  
>  	return DIV_ROUND_UP_ULL(rate, n);
> @@ -100,7 +101,8 @@ static unsigned int __pll_params_with_frac(unsigned long rate,
>  					   unsigned int n,
>  					   struct meson_clk_pll_data *pll)
>  {
> -	unsigned int frac_max = (1 << pll->frac.width);
> +	unsigned int frac_max = unlikely(pll->frac_max) ? pll->frac_max :
> +							  (1 << pll->frac.width);
>  	u64 val = (u64)rate * n;
>  
>  	/* Bail out if we are already over the requested rate */
> diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
> index 7b6b87274073..949157fb7bf5 100644
> --- a/drivers/clk/meson/clk-pll.h
> +++ b/drivers/clk/meson/clk-pll.h
> @@ -43,6 +43,7 @@ struct meson_clk_pll_data {
>  	unsigned int init_count;
>  	const struct pll_params_table *table;
>  	const struct pll_mult_range *range;
> +	unsigned int frac_max;
>  	u8 flags;
>  };

-- 
Jerome

Re: [PATCH v2 1/3] clk: meson: Support PLL with fixed fractional denominators

[Chuan Liu]

Hi, Jerome, Thank you for your quick reply! I didn't get back to you
because of the weekend.


On 2024/9/6 19:22, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Fri 06 Sep 2024 at 18:34, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org> wrote:
>
>> From: Chuan Liu <chuan.liu@amlogic.com>
>>
>> Some PLLS with fractional multipliers have fractional denominators with
>> fixed values, instead of the previous "(1 << pll-> frc.width)".
>>
>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
>> ---
>>   drivers/clk/meson/clk-pll.c | 8 +++++---
>>   drivers/clk/meson/clk-pll.h | 1 +
>>   2 files changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
>> index bc570a2ff3a3..a141ab450009 100644
>> --- a/drivers/clk/meson/clk-pll.c
>> +++ b/drivers/clk/meson/clk-pll.c
>> @@ -57,12 +57,13 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate,
>>                                          struct meson_clk_pll_data *pll)
>>   {
>>        u64 rate = (u64)parent_rate * m;
>> +     unsigned int frac_max = unlikely(pll->frac_max) ? pll->frac_max
>> :
>                                   ^ Please don't play with this unless
>                                   you've got justification a for it.


Sorry, I don't quite understand this one. Is it because you suggest keeping

"(1 << pll->frac_max)" here, followed by "if" to determine whether to assign

"pll->frac_max"?


"unlikely" is used here. My idea is that it will be possible to 
determine the value

of "frac_max" at compile time, which will result in one less "if" 
judgment and

slightly improve drive performance.


>
> By justification, I mean actual numbers showing the difference it makes
> and not just for the platforms listed in this series, but all the
> platforms supported by this driver.


You're right, In this way, even if the latter value changes, our driver 
will be

compatible.


>> +                                                       (1 << pll->frac.width);
>>
>>        if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
>>                u64 frac_rate = (u64)parent_rate * frac;
>>
>> -             rate += DIV_ROUND_UP_ULL(frac_rate,
>> -                                      (1 << pll->frac.width));
>> +             rate += DIV_ROUND_UP_ULL(frac_rate, frac_max);
>>        }
>>
>>        return DIV_ROUND_UP_ULL(rate, n);
>> @@ -100,7 +101,8 @@ static unsigned int __pll_params_with_frac(unsigned long rate,
>>                                           unsigned int n,
>>                                           struct meson_clk_pll_data *pll)
>>   {
>> -     unsigned int frac_max = (1 << pll->frac.width);
>> +     unsigned int frac_max = unlikely(pll->frac_max) ? pll->frac_max :
>> +                                                       (1 << pll->frac.width);
>>        u64 val = (u64)rate * n;
>>
>>        /* Bail out if we are already over the requested rate */
>> diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
>> index 7b6b87274073..949157fb7bf5 100644
>> --- a/drivers/clk/meson/clk-pll.h
>> +++ b/drivers/clk/meson/clk-pll.h
>> @@ -43,6 +43,7 @@ struct meson_clk_pll_data {
>>        unsigned int init_count;
>>        const struct pll_params_table *table;
>>        const struct pll_mult_range *range;
>> +     unsigned int frac_max;
>>        u8 flags;
>>   };
> --
> Jerome

Re: [PATCH v2 1/3] clk: meson: Support PLL with fixed fractional denominators

[Jerome Brunet]

On Mon 09 Sep 2024 at 09:55, Chuan Liu <chuan.liu@amlogic.com> wrote:

> Sorry, I don't quite understand this one. Is it because you suggest keeping
>
> "(1 << pll->frac_max)" here, followed by "if" to determine whether to assign
>
> "pll->frac_max"?
>
>
> "unlikely" is used here. My idea is that it will be possible to determine
> the value
>
> of "frac_max" at compile time, which will result in one less "if" judgment
> and
>
> slightly improve drive performance.

I'll rephrase.

Please drop the 'unlikely()' call.

You may add that :
 * in a separate change
 * if you really really wish to
 * if you provide profiling numbers for the different supported
   platforms and PLLs, not just the one targeted by this patchset.

Re: [PATCH v2 1/3] clk: meson: Support PLL with fixed fractional denominators

[Chuan Liu]

Hi, Jerome:

         Thank you for your meticulous explanation.


On 2024/9/9 15:40, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Mon 09 Sep 2024 at 09:55, Chuan Liu <chuan.liu@amlogic.com> wrote:
>
>> Sorry, I don't quite understand this one. Is it because you suggest keeping
>>
>> "(1 << pll->frac_max)" here, followed by "if" to determine whether to assign
>>
>> "pll->frac_max"?
>>
>>
>> "unlikely" is used here. My idea is that it will be possible to determine
>> the value
>>
>> of "frac_max" at compile time, which will result in one less "if" judgment
>> and
>>
>> slightly improve drive performance.
> I'll rephrase.
>
> Please drop the 'unlikely()' call.
>
> You may add that :
>   * in a separate change
>   * if you really really wish to
>   * if you provide profiling numbers for the different supported
>     platforms and PLLs, not just the one targeted by this patchset.


Okay, Understood. So you suggest like this?

static unsigned long __pll_params_to_rate(unsigned long parent_rate,
                                           struct meson_clk_pll_data *pll)
  {
         u64 rate = (u64)parent_rate * m;
+       unsigned int frac_max = (1 << pll->frac.width);

         if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
                 u64 frac_rate = (u64)parent_rate * frac;

-               rate += DIV_ROUND_UP_ULL(frac_rate,
-                                        (1 << pll->frac.width));
+               if (pll->frac_max)
+                       frac_max = pll->frac_max;
+
+               rate += DIV_ROUND_UP_ULL(frac_rate, frac_max);


In my opinion, this change seems more logical, but the amount of

change is larger?😮

Re: [PATCH v2 1/3] clk: meson: Support PLL with fixed fractional denominators

[Jerome Brunet]

On Mon 09 Sep 2024 at 16:46, Chuan Liu <chuan.liu@amlogic.com> wrote:

> Hi, Jerome:
>
>         Thank you for your meticulous explanation.
>
>
> On 2024/9/9 15:40, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On Mon 09 Sep 2024 at 09:55, Chuan Liu <chuan.liu@amlogic.com> wrote:
>>
>>> Sorry, I don't quite understand this one. Is it because you suggest keeping
>>>
>>> "(1 << pll->frac_max)" here, followed by "if" to determine whether to assign
>>>
>>> "pll->frac_max"?
>>>
>>>
>>> "unlikely" is used here. My idea is that it will be possible to determine
>>> the value
>>>
>>> of "frac_max" at compile time, which will result in one less "if" judgment
>>> and
>>>
>>> slightly improve drive performance.
>> I'll rephrase.
>>
>> Please drop the 'unlikely()' call.
>>
>> You may add that :
>>   * in a separate change
>>   * if you really really wish to
>>   * if you provide profiling numbers for the different supported
>>     platforms and PLLs, not just the one targeted by this patchset.
>
>
> Okay, Understood. So you suggest like this?

No. drop the call to unlikely(). Keep the rest. That's it.

>
> static unsigned long __pll_params_to_rate(unsigned long parent_rate,
>                                           struct meson_clk_pll_data *pll)
>  {
>         u64 rate = (u64)parent_rate * m;
> +       unsigned int frac_max = (1 << pll->frac.width);
>
>         if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
>                 u64 frac_rate = (u64)parent_rate * frac;
>
> -               rate += DIV_ROUND_UP_ULL(frac_rate,
> -                                        (1 << pll->frac.width));
> +               if (pll->frac_max)
> +                       frac_max = pll->frac_max;
> +
> +               rate += DIV_ROUND_UP_ULL(frac_rate, frac_max);
>
>
> In my opinion, this change seems more logical, but the amount of
>
> change is larger?😮

-- 
Jerome

[PATCH v2 2/3] clk: meson: c3: pll: fix frac maximum value for hifi_pll

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

The fractional denominator of C3's hifi_pll fractional multiplier is
fixed to 100000.

Fixes: 8a9a129dc565 ("clk: meson: c3: add support for the C3 SoC PLL clock")
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 drivers/clk/meson/c3-pll.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c
index 32bd2ed9d304..35fda31a19e2 100644
--- a/drivers/clk/meson/c3-pll.c
+++ b/drivers/clk/meson/c3-pll.c
@@ -361,6 +361,7 @@ static struct clk_regmap hifi_pll_dco = {
 		.range = &c3_gp0_pll_mult_range,
 		.init_regs = c3_hifi_init_regs,
 		.init_count = ARRAY_SIZE(c3_hifi_init_regs),
+		.frac_max = 100000,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "hifi_pll_dco",

-- 
2.42.0

[PATCH v2 3/3] clk: meson: s4: pll: fix frac maximum value for hifi_pll

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

The fractional denominator of S4's hifi_pll fractional multiplier is
fixed to 100000.

Fixes: 80344f4c1a1e ("clk: meson: s4: pll: hifi_pll support fractional multiplier")
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 drivers/clk/meson/s4-pll.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
index a97e19057b05..9697f6577e06 100644
--- a/drivers/clk/meson/s4-pll.c
+++ b/drivers/clk/meson/s4-pll.c
@@ -371,6 +371,7 @@ static struct clk_regmap s4_hifi_pll_dco = {
 		.range = &s4_gp0_pll_mult_range,
 		.init_regs = s4_hifi_init_regs,
 		.init_count = ARRAY_SIZE(s4_hifi_init_regs),
+		.frac_max = 100000,
 		.flags = CLK_MESON_PLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){

-- 
2.42.0