Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Marek Vasut <marex@denx.de>]

On 12/30/24 8:51 AM, Michael Walle wrote:
> Hi Marek,

Hi,

> On Thu Dec 26, 2024 at 5:22 PM CET, Marek Vasut wrote:
>> The driver currently supports generating BCLK.
> 
> I'd say the driver supports generating *any* clock on the BCLK pin.

The clock are coming out of the SAI 'BCLK' output and are controlled by 
the SAI BCLK control bits. Of course, it is possible to feed arbitrary 
upstream clock into the SAI and have those exposed on the BCLK pin. I'll 
try to reword the commit message to make that clearer.

> It's not necessarily the BCLK clock. I.e. on the board where this is
> used, this is the clock with a given frequency sourcing the PLL in
> the audio codec.

Right

>> There are systems which require generation of MCLK instead.
> 
> You mean systems that use the MCLK pin instead?

Yes

> ..Which is the
> normal use case for this pin. This driver was created because the
> LS1028A doesn't have a MCLK pin, so we've "misused" the BCLK pin,
> with the restriction that only integer dividers are possible.

I have a system that is wired a bit unfortunately, I need to source 
codec clock, where the codec is the clock consumer and needs to be able 
to control the clock (SGTL5000). SAI MCLK is the only way I can get them 
out of the pin I need, hence this patch.

> I
> haven't looked at the datasheet, but doesn't the MCLK has a PLL
> which could generate any frequency?

Audio PLL , sure.

> Also I'd expect that the imx
> SoCs already supports the MCLK for audio applications. Isn't that
> the case?

That does not work if the MCLK has to be enabled/disabled by the MCLK 
clock consumer .

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