Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

["Michael Walle" <michael@walle.cc>]

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Hi Marek,

On Thu Dec 26, 2024 at 5:22 PM CET, Marek Vasut wrote:
> The driver currently supports generating BCLK.

I'd say the driver supports generating *any* clock on the BCLK pin.
It's not necessarily the BCLK clock. I.e. on the board where this is
used, this is the clock with a given frequency sourcing the PLL in
the audio codec.

> There are systems which require generation of MCLK instead.

You mean systems that use the MCLK pin instead? ..Which is the
normal use case for this pin. This driver was created because the
LS1028A doesn't have a MCLK pin, so we've "misused" the BCLK pin,
with the restriction that only integer dividers are possible. I
haven't looked at the datasheet, but doesn't the MCLK has a PLL
which could generate any frequency? Also I'd expect that the imx
SoCs already supports the MCLK for audio applications. Isn't that
the case?

> Register new MCLK clock and handle
> clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
> legacy system with clock-cells = <0>, the driver behaves as before, i.e.
> always returns BCLK.

-michael

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