[PATCH v2 0/6] Add support for GPUCC, CAMCC and VIDEOCC on Qualcomm QCS8300 platform

[PATCH v2 0/6] Add support for GPUCC, CAMCC and VIDEOCC on Qualcomm QCS8300 platform

[Imran Shaik]

This patch series add support for GPUCC, CAMCC and VIDEOCC on Qualcomm
QCS8300 platform.

Please note that this series is dependent on [1] and [2], which adds support
for QCS8300 GCC and SA8775P multi media clock controllers respectively.

[1] https://lore.kernel.org/all/20240822-qcs8300-gcc-v2-0-b310dfa70ad8@quicinc.com/
[2] https://lore.kernel.org/all/20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com/

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
Changes in v2:
- Updated commit text details in bindings patches as per the review comments.
- Sorted the compatible order and updated comment in VideoCC driver patch as per the review comments.
- Added the R-By tags received in V1.
- Link to v1: https://lore.kernel.org/r/20241018-qcs8300-mm-patches-v1-0-859095e0776c@quicinc.com

---
Imran Shaik (6):
      dt-bindings: clock: qcom: Add GPU clocks for QCS8300
      clk: qcom: Add support for GPU Clock Controller on QCS8300
      dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300
      clk: qcom: Add support for Camera Clock Controller on QCS8300
      dt-bindings: clock: qcom: Add QCS8300 video clock controller
      clk: qcom: Add support for Video Clock Controller on QCS8300

 .../devicetree/bindings/clock/qcom,gpucc.yaml      |  1 +
 .../bindings/clock/qcom,sa8775p-camcc.yaml         |  1 +
 .../bindings/clock/qcom,sa8775p-videocc.yaml       |  1 +
 drivers/clk/qcom/camcc-sa8775p.c                   | 99 +++++++++++++++++++++-
 drivers/clk/qcom/gpucc-sa8775p.c                   | 47 ++++++++++
 drivers/clk/qcom/videocc-sa8775p.c                 |  8 ++
 include/dt-bindings/clock/qcom,sa8775p-camcc.h     |  1 +
 include/dt-bindings/clock/qcom,sa8775p-gpucc.h     |  4 +-
 8 files changed, 157 insertions(+), 5 deletions(-)
---
base-commit: 891a4dc5705df4de9a258accef31786b46700394
change-id: 20241016-qcs8300-mm-patches-fc01e8c75ed4

Best regards,
-- 
Imran Shaik <quic_imrashai@quicinc.com>

[PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Imran Shaik]

The QCS8300 GPU clock controller is mostly identical to SA8775P, but
QCS8300 has few additional clocks and minor differences. Hence, reuse
SA8775P gpucc bindings and add additional clocks required for QCS8300.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
 Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 1 +
 include/dt-bindings/clock/qcom,sa8775p-gpucc.h          | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 0858fd635282..b2b8a1e0297f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -27,6 +27,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-gpucc
       - qcom,sdm845-gpucc
       - qcom,sa8775p-gpucc
       - qcom,sc7180-gpucc
diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h
index a5fd784b1ea2..54eaaf1c4e52 100644
--- a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h
+++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2023, Linaro Limited
  */
 
@@ -31,6 +31,8 @@
 #define GPU_CC_MEMNOC_GFX_CLK			20
 #define GPU_CC_SLEEP_CLK			21
 #define GPU_CC_XO_CLK_SRC			22
+#define GPU_CC_CX_ACCU_SHIFT_CLK		23
+#define GPU_CC_GX_ACCU_SHIFT_CLK		24
 
 /* GPU_CC resets */
 #define GPUCC_GPU_CC_ACD_BCR			0

-- 
2.25.1

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Krzysztof Kozlowski]

On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
> QCS8300 has few additional clocks and minor differences. Hence, reuse
> SA8775P gpucc bindings and add additional clocks required for QCS8300.

IIUC, these clocks are not valid for SA8775p. How do we deal with such
cases for other Qualcomm SoCs?

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Imran Shaik]

On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
> 
> IIUC, these clocks are not valid for SA8775p. How do we deal with such
> cases for other Qualcomm SoCs?
> 

These newly added clocks are not applicable to SA8755P. In the 
gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P, 
ensuring they are not registered to the CCF.

Thanks,
Imran

> Best regards,
> Krzysztof
> 

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Krzysztof Kozlowski]

On 28/10/2024 06:15, Imran Shaik wrote:
> 
> 
> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>
>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>> cases for other Qualcomm SoCs?
>>
> 
> These newly added clocks are not applicable to SA8755P. In the 
> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P, 
> ensuring they are not registered to the CCF.

I meant bindings. And existing practice.

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Imran Shaik]

On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote:
> On 28/10/2024 06:15, Imran Shaik wrote:
>>
>>
>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>>
>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>>> cases for other Qualcomm SoCs?
>>>
>>
>> These newly added clocks are not applicable to SA8755P. In the
>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P,
>> ensuring they are not registered to the CCF.
> 
> I meant bindings. And existing practice.
> 

In the bindings, the same approach is followed in other Qualcomm SoCs as 
well, where additional clocks are added to the existing identical SoC’s 
bindings.

https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com

Thanks,
Imran

> Best regards,
> Krzysztof
> 

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Krzysztof Kozlowski]

On 29/10/2024 10:23, Imran Shaik wrote:
> 
> 
> On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote:
>> On 28/10/2024 06:15, Imran Shaik wrote:
>>>
>>>
>>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
>>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>>>
>>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>>>> cases for other Qualcomm SoCs?
>>>>
>>>
>>> These newly added clocks are not applicable to SA8755P. In the
>>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P,
>>> ensuring they are not registered to the CCF.
>>
>> I meant bindings. And existing practice.
>>
> 
> In the bindings, the same approach is followed in other Qualcomm SoCs as 
> well, where additional clocks are added to the existing identical SoC’s 
> bindings.
> 
> https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com

Exactly, defines are very different, so no, it is not the same approach.

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Imran Shaik]

On 10/29/2024 3:06 PM, Krzysztof Kozlowski wrote:
> On 29/10/2024 10:23, Imran Shaik wrote:
>>
>>
>> On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote:
>>> On 28/10/2024 06:15, Imran Shaik wrote:
>>>>
>>>>
>>>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
>>>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>>>>
>>>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>>>>> cases for other Qualcomm SoCs?
>>>>>
>>>>
>>>> These newly added clocks are not applicable to SA8755P. In the
>>>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P,
>>>> ensuring they are not registered to the CCF.
>>>
>>> I meant bindings. And existing practice.
>>>
>>
>> In the bindings, the same approach is followed in other Qualcomm SoCs as
>> well, where additional clocks are added to the existing identical SoC’s
>> bindings.
>>
>> https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com
> 
> Exactly, defines are very different, so no, it is not the same approach.
> 

I believe the QCS8300 approach is same as that of SM8475. In the SM8475 
SoC, GPLL2 and GPLL3 are the additional clock bindings compared to the 
SM8450. Similarly, in the QCS8300, the GPU_CC_*_ACCU_SHIFT_CLK clock 
bindings are additional to the SA8775P.

We are also following this approach across all SoCs in the downstream 
msm-kernel as well.

Please let me know if I am missing anything here.

Thanks,
Imran

> Best regards,
> Krzysztof
> 

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Krzysztof Kozlowski]

On 30/10/2024 07:59, Imran Shaik wrote:
> 
> 
> On 10/29/2024 3:06 PM, Krzysztof Kozlowski wrote:
>> On 29/10/2024 10:23, Imran Shaik wrote:
>>>
>>>
>>> On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote:
>>>> On 28/10/2024 06:15, Imran Shaik wrote:
>>>>>
>>>>>
>>>>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
>>>>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>>>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>>>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>>>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>>>>>
>>>>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>>>>>> cases for other Qualcomm SoCs?
>>>>>>
>>>>>
>>>>> These newly added clocks are not applicable to SA8755P. In the
>>>>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P,
>>>>> ensuring they are not registered to the CCF.
>>>>
>>>> I meant bindings. And existing practice.
>>>>
>>>
>>> In the bindings, the same approach is followed in other Qualcomm SoCs as
>>> well, where additional clocks are added to the existing identical SoC’s
>>> bindings.
>>>
>>> https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com
>>
>> Exactly, defines are very different, so no, it is not the same approach.
>>
> 
> I believe the QCS8300 approach is same as that of SM8475. In the SM8475 
> SoC, GPLL2 and GPLL3 are the additional clock bindings compared to the 
> SM8450. Similarly, in the QCS8300, the GPU_CC_*_ACCU_SHIFT_CLK clock 
> bindings are additional to the SA8775P.
> 
> We are also following this approach across all SoCs in the downstream 
> msm-kernel as well.
> 
> Please let me know if I am missing anything here.

Not sure, please take the same approach as SM8475, not a different one.

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Imran Shaik]

On 10/30/2024 1:00 PM, Krzysztof Kozlowski wrote:
> On 30/10/2024 07:59, Imran Shaik wrote:
>>
>>
>> On 10/29/2024 3:06 PM, Krzysztof Kozlowski wrote:
>>> On 29/10/2024 10:23, Imran Shaik wrote:
>>>>
>>>>
>>>> On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote:
>>>>> On 28/10/2024 06:15, Imran Shaik wrote:
>>>>>>
>>>>>>
>>>>>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
>>>>>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>>>>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>>>>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>>>>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>>>>>>
>>>>>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>>>>>>> cases for other Qualcomm SoCs?
>>>>>>>
>>>>>>
>>>>>> These newly added clocks are not applicable to SA8755P. In the
>>>>>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P,
>>>>>> ensuring they are not registered to the CCF.
>>>>>
>>>>> I meant bindings. And existing practice.
>>>>>
>>>>
>>>> In the bindings, the same approach is followed in other Qualcomm SoCs as
>>>> well, where additional clocks are added to the existing identical SoC’s
>>>> bindings.
>>>>
>>>> https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com
>>>
>>> Exactly, defines are very different, so no, it is not the same approach.
>>>
>>
>> I believe the QCS8300 approach is same as that of SM8475. In the SM8475
>> SoC, GPLL2 and GPLL3 are the additional clock bindings compared to the
>> SM8450. Similarly, in the QCS8300, the GPU_CC_*_ACCU_SHIFT_CLK clock
>> bindings are additional to the SA8775P.
>>
>> We are also following this approach across all SoCs in the downstream
>> msm-kernel as well.
>>
>> Please let me know if I am missing anything here.
> 
> Not sure, please take the same approach as SM8475, not a different one.
> 

Yes, it is the same approach as SM8475.

Thanks,
Imran

> Best regards,
> Krzysztof
> 

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Krzysztof Kozlowski]

On 30/10/2024 11:14, Imran Shaik wrote:
> 
> 
> On 10/30/2024 1:00 PM, Krzysztof Kozlowski wrote:
>> On 30/10/2024 07:59, Imran Shaik wrote:
>>>
>>>
>>> On 10/29/2024 3:06 PM, Krzysztof Kozlowski wrote:
>>>> On 29/10/2024 10:23, Imran Shaik wrote:
>>>>>
>>>>>
>>>>> On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote:
>>>>>> On 28/10/2024 06:15, Imran Shaik wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
>>>>>>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>>>>>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>>>>>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>>>>>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>>>>>>>
>>>>>>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>>>>>>>> cases for other Qualcomm SoCs?
>>>>>>>>
>>>>>>>
>>>>>>> These newly added clocks are not applicable to SA8755P. In the
>>>>>>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P,
>>>>>>> ensuring they are not registered to the CCF.
>>>>>>
>>>>>> I meant bindings. And existing practice.
>>>>>>
>>>>>
>>>>> In the bindings, the same approach is followed in other Qualcomm SoCs as
>>>>> well, where additional clocks are added to the existing identical SoC’s
>>>>> bindings.
>>>>>
>>>>> https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com
>>>>
>>>> Exactly, defines are very different, so no, it is not the same approach.
>>>>
>>>
>>> I believe the QCS8300 approach is same as that of SM8475. In the SM8475
>>> SoC, GPLL2 and GPLL3 are the additional clock bindings compared to the
>>> SM8450. Similarly, in the QCS8300, the GPU_CC_*_ACCU_SHIFT_CLK clock
>>> bindings are additional to the SA8775P.
>>>
>>> We are also following this approach across all SoCs in the downstream
>>> msm-kernel as well.
>>>
>>> Please let me know if I am missing anything here.
>>
>> Not sure, please take the same approach as SM8475, not a different one.
>>
> 
> Yes, it is the same approach as SM8475.

I already said:
"Exactly, defines are very different, so no, it is not the same approach."

and this discussion leads nowhere. Don't answer with useless responses
just so reviewer will go away.

NAK. I am going away.


Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Dmitry Baryshkov]

On Wed, Oct 30, 2024 at 08:30:59AM +0100, Krzysztof Kozlowski wrote:
> On 30/10/2024 07:59, Imran Shaik wrote:
> > 
> > 
> > On 10/29/2024 3:06 PM, Krzysztof Kozlowski wrote:
> >> On 29/10/2024 10:23, Imran Shaik wrote:
> >>>
> >>>
> >>> On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote:
> >>>> On 28/10/2024 06:15, Imran Shaik wrote:
> >>>>>
> >>>>>
> >>>>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
> >>>>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
> >>>>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
> >>>>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
> >>>>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
> >>>>>>
> >>>>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
> >>>>>> cases for other Qualcomm SoCs?
> >>>>>>
> >>>>>
> >>>>> These newly added clocks are not applicable to SA8755P. In the
> >>>>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P,
> >>>>> ensuring they are not registered to the CCF.
> >>>>
> >>>> I meant bindings. And existing practice.
> >>>>
> >>>
> >>> In the bindings, the same approach is followed in other Qualcomm SoCs as
> >>> well, where additional clocks are added to the existing identical SoC’s
> >>> bindings.
> >>>
> >>> https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com
> >>
> >> Exactly, defines are very different, so no, it is not the same approach.
> >>
> > 
> > I believe the QCS8300 approach is same as that of SM8475. In the SM8475 
> > SoC, GPLL2 and GPLL3 are the additional clock bindings compared to the 
> > SM8450. Similarly, in the QCS8300, the GPU_CC_*_ACCU_SHIFT_CLK clock 
> > bindings are additional to the SA8775P.
> > 
> > We are also following this approach across all SoCs in the downstream 
> > msm-kernel as well.
> > 
> > Please let me know if I am missing anything here.
> 
> Not sure, please take the same approach as SM8475, not a different one.

Just for my understanding, are you proposing to prefix the
platform-specific defines with platform name (like it was done for
SM8475)?

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Krzysztof Kozlowski]

On 30/10/2024 12:23, Dmitry Baryshkov wrote:
> On Wed, Oct 30, 2024 at 08:30:59AM +0100, Krzysztof Kozlowski wrote:
>> On 30/10/2024 07:59, Imran Shaik wrote:
>>>
>>>
>>> On 10/29/2024 3:06 PM, Krzysztof Kozlowski wrote:
>>>> On 29/10/2024 10:23, Imran Shaik wrote:
>>>>>
>>>>>
>>>>> On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote:
>>>>>> On 28/10/2024 06:15, Imran Shaik wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote:
>>>>>>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>>>>>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>>>>>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>>>>>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>>>>>>>
>>>>>>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>>>>>>>> cases for other Qualcomm SoCs?
>>>>>>>>
>>>>>>>
>>>>>>> These newly added clocks are not applicable to SA8755P. In the
>>>>>>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P,
>>>>>>> ensuring they are not registered to the CCF.
>>>>>>
>>>>>> I meant bindings. And existing practice.
>>>>>>
>>>>>
>>>>> In the bindings, the same approach is followed in other Qualcomm SoCs as
>>>>> well, where additional clocks are added to the existing identical SoC’s
>>>>> bindings.
>>>>>
>>>>> https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com
>>>>
>>>> Exactly, defines are very different, so no, it is not the same approach.
>>>>
>>>
>>> I believe the QCS8300 approach is same as that of SM8475. In the SM8475 
>>> SoC, GPLL2 and GPLL3 are the additional clock bindings compared to the 
>>> SM8450. Similarly, in the QCS8300, the GPU_CC_*_ACCU_SHIFT_CLK clock 
>>> bindings are additional to the SA8775P.
>>>
>>> We are also following this approach across all SoCs in the downstream 
>>> msm-kernel as well.
>>>
>>> Please let me know if I am missing anything here.
>>
>> Not sure, please take the same approach as SM8475, not a different one.
> 
> Just for my understanding, are you proposing to prefix the
> platform-specific defines with platform name (like it was done for
> SM8475)?

Yes. Maybe SM8475 did something more, so let's take similar approach.

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Vladimir Zapolskiy]

On 10/26/24 15:20, Krzysztof Kozlowski wrote:
> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
> 
> IIUC, these clocks are not valid for SA8775p. How do we deal with such
> cases for other Qualcomm SoCs?
> 

It always possible to add a new platform specific header file and
include the old one.

For reference see commit a6a61b9701d1 ("dt-bindings: clock: qcom: Add
SM8650 video clock controller"), I believe that's the preferred way
of adding new platform clocks whenever technically possible.

--
Best wishes,
Vladimir

Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300

[Imran Shaik]

On 10/30/2024 4:29 PM, Vladimir Zapolskiy wrote:
> On 10/26/24 15:20, Krzysztof Kozlowski wrote:
>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote:
>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but
>>> QCS8300 has few additional clocks and minor differences. Hence, reuse
>>> SA8775P gpucc bindings and add additional clocks required for QCS8300.
>>
>> IIUC, these clocks are not valid for SA8775p. How do we deal with such
>> cases for other Qualcomm SoCs?
>>
> 
> It always possible to add a new platform specific header file and
> include the old one.
> 
> For reference see commit a6a61b9701d1 ("dt-bindings: clock: qcom: Add
> SM8650 video clock controller"), I believe that's the preferred way
> of adding new platform clocks whenever technically possible.
> 

Sure, I will follow the same approach as the commit a6a61b9701d1 and 
post next series.

Thanks,
Imran

> -- 
> Best wishes,
> Vladimir

[PATCH v2 2/6] clk: qcom: Add support for GPU Clock Controller on QCS8300

[Imran Shaik]

Add support to the QCS8300 GPU clock controller by extending
the SA8775P GPU clock controller, which is mostly identical
but QCS8300 has few additional clocks and minor differences.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
 drivers/clk/qcom/gpucc-sa8775p.c | 47 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index f8a8ac343d70..99a8344b00db 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -317,6 +317,24 @@ static struct clk_branch gpu_cc_crc_ahb_clk = {
 	},
 };
 
+static struct clk_branch gpu_cc_cx_accu_shift_clk = {
+	.halt_reg = 0x95e8,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x95e8,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data){
+			.name = "gpu_cc_cx_accu_shift_clk",
+			.parent_hws = (const struct clk_hw*[]){
+				&gpu_cc_xo_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gpu_cc_cx_ff_clk = {
 	.halt_reg = 0x914c,
 	.halt_check = BRANCH_HALT,
@@ -420,6 +438,24 @@ static struct clk_branch gpu_cc_demet_clk = {
 	},
 };
 
+static struct clk_branch gpu_cc_gx_accu_shift_clk = {
+	.halt_reg = 0x95e4,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x95e4,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data){
+			.name = "gpu_cc_gx_accu_shift_clk",
+			.parent_hws = (const struct clk_hw*[]){
+				&gpu_cc_xo_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
 	.halt_reg = 0x7000,
 	.halt_check = BRANCH_HALT_VOTED,
@@ -499,6 +535,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
 	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
 	[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
 	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
+	[GPU_CC_CX_ACCU_SHIFT_CLK] = NULL,
 	[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
 	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
 	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
@@ -508,6 +545,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
 	[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
 	[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
 	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
+	[GPU_CC_GX_ACCU_SHIFT_CLK] = NULL,
 	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
 	[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
 	[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
@@ -583,6 +621,7 @@ static const struct qcom_cc_desc gpu_cc_sa8775p_desc = {
 };
 
 static const struct of_device_id gpu_cc_sa8775p_match_table[] = {
+	{ .compatible = "qcom,qcs8300-gpucc" },
 	{ .compatible = "qcom,sa8775p-gpucc" },
 	{ }
 };
@@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) {
+		gpu_cc_pll0_config.l = 0x31;
+		gpu_cc_pll0_config.alpha = 0xe555;
+
+		gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr;
+		gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr;
+	}
+
 	clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
 	clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
 

-- 
2.25.1

[PATCH v2 3/6] dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300

[Imran Shaik]

The QCS8300 camera clock controller is mostly identical to SA8775P, but
QCS8300 has one additional clock and minor differences. Hence, reuse the
SA8775P camera bindings and add additional clock required for QCS8300.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
 Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml | 1 +
 include/dt-bindings/clock/qcom,sa8775p-camcc.h                  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
index 36a60d8f5ae3..18cbc23b9a07 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
@@ -18,6 +18,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-camcc
       - qcom,sa8775p-camcc
 
   clocks:
diff --git a/include/dt-bindings/clock/qcom,sa8775p-camcc.h b/include/dt-bindings/clock/qcom,sa8775p-camcc.h
index 38531acd699f..36ac587a981a 100644
--- a/include/dt-bindings/clock/qcom,sa8775p-camcc.h
+++ b/include/dt-bindings/clock/qcom,sa8775p-camcc.h
@@ -93,6 +93,7 @@
 #define CAM_CC_SM_OBS_CLK					83
 #define CAM_CC_XO_CLK_SRC					84
 #define CAM_CC_QDSS_DEBUG_XO_CLK				85
+#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK				86
 
 /* CAM_CC power domains */
 #define CAM_CC_TITAN_TOP_GDSC					0

-- 
2.25.1

Re: [PATCH v2 3/6] dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300

[Krzysztof Kozlowski]

On 24/10/2024 15:31, Imran Shaik wrote:
> The QCS8300 camera clock controller is mostly identical to SA8775P, but
> QCS8300 has one additional clock and minor differences. Hence, reuse the
> SA8775P camera bindings and add additional clock required for QCS8300.
> 
> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
> ---
>  Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml | 1 +
>  include/dt-bindings/clock/qcom,sa8775p-camcc.h                  | 1 +
>  2 files changed, 2 insertions(+)

To clarify - first patch was NAKed, which applies to other bindings here
as well.

Best regards,
Krzysztof

Re: [PATCH v2 3/6] dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300

[Vladimir Zapolskiy]

Imran, Krzysztof,

On 10/24/24 16:31, Imran Shaik wrote:
> The QCS8300 camera clock controller is mostly identical to SA8775P, but
> QCS8300 has one additional clock and minor differences. Hence, reuse the
> SA8775P camera bindings and add additional clock required for QCS8300.
> 
> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
> ---
>   Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml | 1 +
>   include/dt-bindings/clock/qcom,sa8775p-camcc.h                  | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
> index 36a60d8f5ae3..18cbc23b9a07 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
> @@ -18,6 +18,7 @@ description: |
>   properties:
>     compatible:
>       enum:
> +      - qcom,qcs8300-camcc
>         - qcom,sa8775p-camcc
>   
>     clocks:
> diff --git a/include/dt-bindings/clock/qcom,sa8775p-camcc.h b/include/dt-bindings/clock/qcom,sa8775p-camcc.h
> index 38531acd699f..36ac587a981a 100644
> --- a/include/dt-bindings/clock/qcom,sa8775p-camcc.h
> +++ b/include/dt-bindings/clock/qcom,sa8775p-camcc.h
> @@ -93,6 +93,7 @@
>   #define CAM_CC_SM_OBS_CLK					83
>   #define CAM_CC_XO_CLK_SRC					84
>   #define CAM_CC_QDSS_DEBUG_XO_CLK				85
> +#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK				86
>   
>   /* CAM_CC power domains */
>   #define CAM_CC_TITAN_TOP_GDSC					0
> 

I greately dislike this change, and the reasons are the same as already
given by Krzysztof.

If you find it possible, please follow an approach by adding a new
header file and include a platform ancestor headder file from it, like
it's done in commit a6a61b9701d1.

--
Best wishes,
Vladimir

[PATCH v2 4/6] clk: qcom: Add support for Camera Clock Controller on QCS8300

[Imran Shaik]

Add support to the QCS8300 Camera clock controller by extending
the SA8775P Camera clock controller, which is mostly identical
but QCS8300 has few additional clocks and few other differences.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
 drivers/clk/qcom/camcc-sa8775p.c | 99 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 95 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa8775p.c
index c04801a5af35..0ef3c6015c34 100644
--- a/drivers/clk/qcom/camcc-sa8775p.c
+++ b/drivers/clk/qcom/camcc-sa8775p.c
@@ -1682,6 +1682,24 @@ static struct clk_branch cam_cc_sm_obs_clk = {
 	},
 };
 
+static struct clk_branch cam_cc_titan_top_accu_shift_clk = {
+	.halt_reg = 0x131f0,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x131f0,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "cam_cc_titan_top_accu_shift_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&cam_cc_xo_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct gdsc cam_cc_titan_top_gdsc = {
 	.gdscr = 0x131bc,
 	.en_rest_wait_val = 0x2,
@@ -1776,6 +1794,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = {
 	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
 	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
 	[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
+	[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL,
 	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
 	[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
 };
@@ -1812,6 +1831,7 @@ static struct qcom_cc_desc cam_cc_sa8775p_desc = {
 };
 
 static const struct of_device_id cam_cc_sa8775p_match_table[] = {
+	{ .compatible = "qcom,qcs8300-camcc" },
 	{ .compatible = "qcom,sa8775p-camcc" },
 	{ }
 };
@@ -1842,10 +1862,81 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev)
 	clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
 	clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
 
-	/* Keep some clocks always enabled */
-	qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
-	qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
-	qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-camcc")) {
+		cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154;
+		cam_cc_camnoc_axi_clk.halt_reg = 0x1316c;
+		cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c;
+		cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174;
+		cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174;
+
+		cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054;
+		cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078;
+		cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098;
+		cam_cc_csid_clk_src.cmd_rcgr = 0x13134;
+
+		cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000;
+		cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c;
+		cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038;
+
+		cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104;
+		cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c;
+		cam_cc_xo_clk_src.cmd_rcgr = 0x131b8;
+		cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4;
+
+		cam_cc_core_ahb_clk.halt_reg = 0x131b4;
+		cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4;
+
+		cam_cc_cpas_ahb_clk.halt_reg = 0x130f4;
+		cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4;
+		cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc;
+		cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc;
+
+		cam_cc_csi0phytimer_clk.halt_reg = 0x1506c;
+		cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c;
+		cam_cc_csi1phytimer_clk.halt_reg = 0x15090;
+		cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090;
+		cam_cc_csi2phytimer_clk.halt_reg = 0x150b0;
+		cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0;
+		cam_cc_csid_clk.halt_reg = 0x1314c;
+		cam_cc_csid_clk.clkr.enable_reg = 0x1314c;
+		cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074;
+		cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074;
+		cam_cc_csiphy0_clk.halt_reg = 0x15070;
+		cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070;
+		cam_cc_csiphy1_clk.halt_reg = 0x15094;
+		cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094;
+		cam_cc_csiphy2_clk.halt_reg = 0x150b4;
+		cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4;
+
+		cam_cc_mclk0_clk.halt_reg = 0x15018;
+		cam_cc_mclk0_clk.clkr.enable_reg = 0x15018;
+		cam_cc_mclk1_clk.halt_reg = 0x15034;
+		cam_cc_mclk1_clk.clkr.enable_reg = 0x15034;
+		cam_cc_mclk2_clk.halt_reg = 0x15050;
+		cam_cc_mclk2_clk.clkr.enable_reg = 0x15050;
+
+		cam_cc_titan_top_gdsc.gdscr = 0x131a0;
+
+		cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL;
+		cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL;
+		cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL;
+		cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL;
+		cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL;
+		cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL;
+		cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL;
+		cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =
+				&cam_cc_titan_top_accu_shift_clk.clkr;
+
+		/* Keep some clocks always enabled */
+		qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */
+		qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */
+		qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */
+	} else {
+		/* Keep some clocks always enabled */
+		qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
+		qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
+		qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
+	}
 
 	ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);
 

-- 
2.25.1

[PATCH v2 5/6] dt-bindings: clock: qcom: Add QCS8300 video clock controller

[Imran Shaik]

The QCS8300 video clock controller is mostly identical to SA8775P, but
QCS8300 has minor difference. Hence, reuse the SA8775P videocc bindings
for QCS8300 platform.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
 Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml
index 928131bff4c1..07e5d811d816 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml
@@ -18,6 +18,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-videocc
       - qcom,sa8775p-videocc
 
   clocks:

-- 
2.25.1

Re: [PATCH v2 5/6] dt-bindings: clock: qcom: Add QCS8300 video clock controller

[Krzysztof Kozlowski]

On Thu, Oct 24, 2024 at 07:01:18PM +0530, Imran Shaik wrote:
> The QCS8300 video clock controller is mostly identical to SA8775P, but
> QCS8300 has minor difference. Hence, reuse the SA8775P videocc bindings
> for QCS8300 platform.
> 
> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
> ---
>  Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 6/6] clk: qcom: Add support for Video Clock Controller on QCS8300

[Imran Shaik]

Add support to the QCS8300 Video clock controller by extending
the SA8775P Video clock controller, which is mostly identical
but QCS8300 has minor difference.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
 drivers/clk/qcom/videocc-sa8775p.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/qcom/videocc-sa8775p.c b/drivers/clk/qcom/videocc-sa8775p.c
index bf5de411fd5d..db492984fd7d 100644
--- a/drivers/clk/qcom/videocc-sa8775p.c
+++ b/drivers/clk/qcom/videocc-sa8775p.c
@@ -523,6 +523,7 @@ static struct qcom_cc_desc video_cc_sa8775p_desc = {
 };
 
 static const struct of_device_id video_cc_sa8775p_match_table[] = {
+	{ .compatible = "qcom,qcs8300-videocc" },
 	{ .compatible = "qcom,sa8775p-videocc" },
 	{ }
 };
@@ -550,6 +551,13 @@ static int video_cc_sa8775p_probe(struct platform_device *pdev)
 	clk_lucid_evo_pll_configure(&video_pll0, regmap, &video_pll0_config);
 	clk_lucid_evo_pll_configure(&video_pll1, regmap, &video_pll1_config);
 
+	/*
+	 * Set mvs0c clock divider to div-3 to make the mvs0 and
+	 * mvs0c clocks to run at the same frequency on QCS8300
+	 */
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-videocc"))
+		regmap_write(regmap, video_cc_mvs0c_div2_div_clk_src.reg, 2);
+
 	/* Keep some clocks always enabled */
 	qcom_branch_set_clk_en(regmap, 0x80ec); /* VIDEO_CC_AHB_CLK */
 	qcom_branch_set_clk_en(regmap, 0x8144); /* VIDEO_CC_SLEEP_CLK */

-- 
2.25.1

Re: [PATCH v2 6/6] clk: qcom: Add support for Video Clock Controller on QCS8300

[Dmitry Baryshkov]

On Thu, Oct 24, 2024 at 07:01:19PM +0530, Imran Shaik wrote:
> Add support to the QCS8300 Video clock controller by extending
> the SA8775P Video clock controller, which is mostly identical
> but QCS8300 has minor difference.
> 
> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
> ---
>  drivers/clk/qcom/videocc-sa8775p.c | 8 ++++++++
>  1 file changed, 8 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry