* [PATCH] clk: renesas: r8a779g0: Fix PCIe clock name
@ 2024-01-30 9:47 Geert Uytterhoeven
2024-01-30 9:53 ` Wolfram Sang
0 siblings, 1 reply; 2+ messages in thread
From: Geert Uytterhoeven @ 2024-01-30 9:47 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Yoshihiro Shimoda
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Fix a typo in the name of the module clock for the second PCIe channel.
Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-clk for v6.9.
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 0acc301221e552f7..c4b1938db76b35f4 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -194,7 +194,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
DEF_MOD("pciec0", 624, R8A779G0_CLK_S0D2_HSC),
- DEF_MOD("pscie1", 625, R8A779G0_CLK_S0D2_HSC),
+ DEF_MOD("pciec1", 625, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] clk: renesas: r8a779g0: Fix PCIe clock name
2024-01-30 9:47 [PATCH] clk: renesas: r8a779g0: Fix PCIe clock name Geert Uytterhoeven
@ 2024-01-30 9:53 ` Wolfram Sang
0 siblings, 0 replies; 2+ messages in thread
From: Wolfram Sang @ 2024-01-30 9:53 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Yoshihiro Shimoda, linux-clk,
linux-renesas-soc
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On Tue, Jan 30, 2024 at 10:47:49AM +0100, Geert Uytterhoeven wrote:
> Fix a typo in the name of the module clock for the second PCIe channel.
>
> Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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2024-01-30 9:47 [PATCH] clk: renesas: r8a779g0: Fix PCIe clock name Geert Uytterhoeven
2024-01-30 9:53 ` Wolfram Sang
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