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From: Xu Yilun <yilun.xu@linux.intel.com>
To: Alexey Kardashevskiy <aik@amd.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
	linux-coco@lists.linux.dev, linux-pci@vger.kernel.org,
	gregkh@linuxfoundation.org
Subject: Re: [PATCH 04/11] PCI/IDE: Selective Stream IDE enumeration
Date: Thu, 12 Dec 2024 14:06:55 +0800	[thread overview]
Message-ID: <Z1p9f6HHkjlOw5Fc@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <2e7f85ea-40ce-4b38-acd9-56c02718771c@amd.com>

> > +/* Selective IDE Stream Capability Register */
> > +#define  PCI_IDE_SEL_CAP		 0
> > +#define  PCI_IDE_SEL_CAP_ASSOC_NUM(x)	 ((x) & 0xf) /* Address Association Register Blocks Number */
> > +#define  PCI_IDE_SEL_CAP_ASSOC_MASK	 0xf

PCI_IDE_SEL_CAP_ASSOC_NUM_MASK is better?

> > +/* Selective IDE Stream Control Register */
> > +#define  PCI_IDE_SEL_CTL		 4
> > +#define   PCI_IDE_SEL_CTL_EN		 0x1	/* Selective IDE Stream Enable */
> > +#define   PCI_IDE_SEL_CTL_TX_AGGR_NPR(x) (((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */
> > +#define   PCI_IDE_SEL_CTL_TX_AGGR_PR(x)	 (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */
> > +#define   PCI_IDE_SEL_CTL_TX_AGGR_CPL(x) (((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */

These fields are more likely to be written to the register than read
out, so may need other definitions.

I think generally _XXX(x) Macros are less useful than _MASK because of
FIELD_PREP/GET(), so maybe by default we define _MASK Macros and on
demand define _XXX(x) Macros for all registers.

> > +#define   PCI_IDE_SEL_CTL_PCRC_EN	 0x100	/* PCRC Enable */
> > +#define   PCI_IDE_SEL_CTL_CFG_EN	 0x200	/* Selective IDE for Configuration Requests */
> > +#define   PCI_IDE_SEL_CTL_PART_ENC(x)	 (((x) >> 10) & 0xf)  /* Partial Header Encryption Mode */
> > +#define   PCI_IDE_SEL_CTL_ALG(x)	 (((x) >> 14) & 0x1f) /* Selected Algorithm */
> > +#define   PCI_IDE_SEL_CTL_TC(x)		 (((x) >> 19) & 0x7)  /* Traffic Class */
> > +#define   PCI_IDE_SEL_CTL_DEFAULT	 0x400000 /* Default Stream */
> > +#define   PCI_IDE_SEL_CTL_TEE_LIMITED	 (1 << 23) /* TEE-Limited Stream */
> > +#define   PCI_IDE_SEL_CTL_ID_MASK	 0xff000000
> > +#define   PCI_IDE_SEL_CTL_ID_MAX	 255
> > +/* Selective IDE Stream Status Register */
> > +#define  PCI_IDE_SEL_STS		 8
> > +#define   PCI_IDE_SEL_STS_STATUS(x)	((x) & 0xf) /* Selective IDE Stream State */
> > +#define   PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK	0x80000000 /* Received Integrity Check Fail Msg */
> > +/* IDE RID Association Register 1 */
> > +#define  PCI_IDE_SEL_RID_1		 12
> > +#define   PCI_IDE_SEL_RID_1_LIMIT_MASK	 0xffff00
> > +/* IDE RID Association Register 2 */
> > +#define  PCI_IDE_SEL_RID_2		 16
> > +#define   PCI_IDE_SEL_RID_2_VALID	 0x1
> > +#define   PCI_IDE_SEL_RID_2_BASE_MASK	 0x00ffff00
> > +#define   PCI_IDE_SEL_RID_2_SEG_MASK	 0xff000000
> > +/* Selective IDE Address Association Register Block, up to PCI_IDE_SEL_CAP_ASSOC_NUM */
> > +#define  PCI_IDE_SEL_ADDR_1(x)		     (20 + (x) * 12)
> > +#define   PCI_IDE_SEL_ADDR_1_VALID	     0x1
> > +#define   PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK   0x000fff0
> 
> 0x000fff00 (missing a zero)
> 
> > +#define   PCI_IDE_SEL_ADDR_1_BASE_LOW_SHIFT  20
> > +#define   PCI_IDE_SEL_ADDR_1_LIMIT_LOW_MASK  0xfff0000
> 
> 
> 0xfff00000
> 
> 31:20 Memory Limit Lower – Corresponds to Address bits [31:20]. Address bits
> [19:0] are implicitly F_FFFFh. RW
> 19:8 Memory Base Lower – Corresponds to Address bits [31:20]. Address[19:0]
> bits are implicitly 0_0000h.
> 
> 
> > +#define   PCI_IDE_SEL_ADDR_1_LIMIT_LOW_SHIFT 20

I don't think _SHIFT MACRO is needed, also because of FIELD_PREP/GET().

> 
> I like mine better :) Shows in one place how addr_1 is made:
> 
> #define  PCI_IDE_SEL_ADDR_1(v, base, limit) \
> 	((FIELD_GET(0xfff00000, (limit))  << 20) | \
> 	(FIELD_GET(0xfff00000, (base)) << 8) | \
> 	((v) ? 1 : 0))

This Macro is useful for SEL_ADDR_1 but not generally useful for other
registers like SEL_CTRL, which has far more fields to input. So I'd
rather have only _MASK Macros here to make things simpler. This
specific Macro for SEL_ADDR_1 could be put in like pci-ide.h if really
needed.

Thanks,
Yilun

> 
> Also, when something uses "SHIFT", I expect left shift (like, PAGE_SHIFT),
> but this is right shift.
> 
> Otherwise, looks good. Thanks,
> 
> > +/* IDE Address Association Register 2 is "Memory Limit Upper" */
> > +/* IDE Address Association Register 3 is "Memory Base Upper" */
> > +#define  PCI_IDE_SEL_ADDR_2(x)		(24 + (x) * 12)
> > +#define  PCI_IDE_SEL_ADDR_3(x)		(28 + (x) * 12)
> > +
> >   #endif /* LINUX_PCI_REGS_H */
> > 
> 
> -- 
> Alexey
> 
> 

  reply	other threads:[~2024-12-12  6:10 UTC|newest]

Thread overview: 125+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-05 22:23 [PATCH 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2024-12-05 22:23 ` [PATCH 01/11] configfs-tsm: Namespace TSM report symbols Dan Williams
2024-12-10  6:08   ` Alexey Kardashevskiy
2024-12-11 13:55   ` Suzuki K Poulose
2024-12-05 22:23 ` [PATCH 02/11] coco/guest: Move shared guest CC infrastructure to drivers/virt/coco/guest/ Dan Williams
2024-12-10  6:09   ` Alexey Kardashevskiy
2024-12-05 22:23 ` [PATCH 03/11] coco/tsm: Introduce a class device for TEE Security Managers Dan Williams
2025-01-28 12:17   ` Jonathan Cameron
2025-02-25 21:08     ` Dan Williams
2024-12-05 22:23 ` [PATCH 04/11] PCI/IDE: Selective Stream IDE enumeration Dan Williams
2024-12-10  3:08   ` Aneesh Kumar K.V
2024-12-12  6:32     ` Xu Yilun
2025-02-22  0:42       ` Dan Williams
2025-02-20  3:17     ` Dan Williams
2024-12-10  6:18   ` Alexey Kardashevskiy
2025-02-20  3:59     ` Dan Williams
2024-12-10  7:05   ` Alexey Kardashevskiy
2024-12-12  6:06     ` Xu Yilun [this message]
2024-12-18 10:35       ` Alexey Kardashevskiy
2025-02-22  0:30       ` Dan Williams
2025-02-20 18:07     ` Dan Williams
2025-02-21  0:53       ` Alexey Kardashevskiy
2025-02-27 23:46         ` Dan Williams
2024-12-10 19:24   ` Bjorn Helgaas
2025-02-22  0:13     ` Dan Williams
2025-01-30 10:45   ` Jonathan Cameron
2025-02-26  0:21     ` Dan Williams
2024-12-05 22:23 ` [PATCH 05/11] PCI/TSM: Authenticate devices via platform TSM Dan Williams
2024-12-10 10:18   ` Alexey Kardashevskiy
2025-02-21  8:13     ` Aneesh Kumar K.V
2025-02-25  7:17       ` Xu Yilun
2025-02-26 12:10         ` Aneesh Kumar K.V
2025-02-26 12:13           ` [RFC PATCH 1/7] tsm: Select PCI_DOE which is required for PCI_TSM Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 2/7] tsm: Move tsm core outside the host directory Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 3/7] tsm: vfio: Add tsm bind/unbind support Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 4/7] tsm: Allow tsm ops function to be called for multi-function devices Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 5/7] tsm: Don't error out for doe mailbox failure Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 6/7] tsm: Allow tsm connect ops to be used for multiple operations Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 7/7] tsm: Add secure SPDM support Aneesh Kumar K.V (Arm)
2025-02-27  6:50               ` Xu Yilun
2025-02-27  6:35           ` [PATCH 05/11] PCI/TSM: Authenticate devices via platform TSM Xu Yilun
2025-02-27 13:57             ` Aneesh Kumar K.V
2025-02-28  1:26               ` Xu Yilun
2025-02-28  9:48                 ` Aneesh Kumar K.V
2025-03-01  7:50                   ` Xu Yilun
2025-03-07  3:07                   ` Alexey Kardashevskiy
2025-02-27 19:53           ` Dan Williams
2025-02-28 10:06             ` Aneesh Kumar K.V
2025-02-21 20:42     ` Dan Williams
2025-02-25  4:45       ` Alexey Kardashevskiy
2025-02-28  3:09         ` Dan Williams
2024-12-10 18:52   ` Bjorn Helgaas
2025-02-21 22:32     ` Dan Williams
2024-12-12  9:50   ` Xu Yilun
2025-02-22  1:15     ` Dan Williams
2025-02-24 11:02       ` Xu Yilun
2025-02-28  0:15         ` Dan Williams
2025-02-28  9:39           ` Xu Yilun
2025-01-30 11:45   ` Jonathan Cameron
2025-02-26  0:50     ` Dan Williams
2024-12-05 22:23 ` [PATCH 06/11] samples/devsec: PCI device-security bus / endpoint sample Dan Williams
2024-12-06  4:23   ` kernel test robot
2024-12-09  3:40   ` kernel test robot
2025-01-30 13:21   ` Jonathan Cameron
2025-02-26  2:00     ` Dan Williams
2024-12-05 22:23 ` [PATCH 07/11] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2024-12-09 13:17   ` Ilpo Järvinen
2025-02-20  3:05     ` Dan Williams
2025-02-20  3:09       ` Dan Williams
2024-12-10 19:21   ` Bjorn Helgaas
2024-12-11 13:22     ` Ilpo Järvinen
2025-02-22  0:15       ` Dan Williams
2025-02-24 15:09         ` Ilpo Järvinen
2025-02-28  0:29           ` Dan Williams
2025-02-21 23:34     ` Dan Williams
2025-02-25  2:25       ` Alexey Kardashevskiy
2024-12-05 22:24 ` [PATCH 08/11] PCI/IDE: Add IDE establishment helpers Dan Williams
2024-12-10  3:19   ` Aneesh Kumar K.V
2024-12-10  3:37     ` Aneesh Kumar K.V
2025-02-20  3:39       ` Dan Williams
2025-02-21 15:53         ` Aneesh Kumar K.V
2025-02-25  0:46           ` Dan Williams
2025-01-07 20:19     ` Xu Yilun
2025-01-10 13:25       ` Aneesh Kumar K.V
2025-02-24 22:31         ` Dan Williams
2025-02-25  2:29           ` Alexey Kardashevskiy
2025-02-20  3:28     ` Dan Williams
2024-12-10  7:07   ` Alexey Kardashevskiy
2025-02-20 21:44     ` Dan Williams
2024-12-10 18:47   ` Bjorn Helgaas
2025-02-21 22:02     ` Dan Williams
2024-12-12 10:50   ` Xu Yilun
2024-12-19  7:25   ` Alexey Kardashevskiy
2024-12-19 10:05     ` Alexey Kardashevskiy
2025-01-07 20:00       ` Xu Yilun
2025-01-09  2:35         ` Alexey Kardashevskiy
2025-01-09 21:28           ` Xu Yilun
2025-01-15  0:20             ` Alexey Kardashevskiy
2025-02-25  0:06               ` Dan Williams
2025-02-25  3:39                 ` Alexey Kardashevskiy
2025-02-28  2:26                   ` Dan Williams
2025-03-04  0:03                     ` Alexey Kardashevskiy
2025-03-04  0:57                       ` Dan Williams
2025-03-04  1:31                         ` Alexey Kardashevskiy
2025-03-04 17:59                           ` Dan Williams
2025-02-20  4:19             ` Alexey Kardashevskiy
2025-02-24 22:24         ` Dan Williams
2025-02-25  2:45           ` Xu Yilun
2025-02-24 20:28       ` Dan Williams
2025-02-26  1:54         ` Alexey Kardashevskiy
2025-02-24 20:24     ` Dan Williams
2025-02-25  5:01       ` Xu Yilun
2024-12-05 22:24 ` [PATCH 09/11] PCI/IDE: Report available IDE streams Dan Williams
2024-12-06  0:12   ` kernel test robot
2024-12-06  0:43   ` kernel test robot
2025-02-11  6:10   ` Alexey Kardashevskiy
2025-02-27 23:35     ` Dan Williams
2024-12-05 22:24 ` [PATCH 10/11] PCI/TSM: Report active " Dan Williams
2024-12-10 18:49   ` Bjorn Helgaas
2025-02-21 22:28     ` Dan Williams
2024-12-05 22:24 ` [PATCH 11/11] samples/devsec: Add sample IDE establishment Dan Williams
2025-01-30 13:39   ` Jonathan Cameron
2025-02-27 23:27     ` Dan Williams
2024-12-06  6:05 ` [PATCH 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP) Greg KH
2024-12-06  8:44   ` Dan Williams

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