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From: Xu Yilun <yilun.xu@linux.intel.com>
To: Alexey Kardashevskiy <aik@amd.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
	linux-coco@lists.linux.dev, Bjorn Helgaas <bhelgaas@google.com>,
	Lukas Wunner <lukas@wunner.de>, Samuel Ortiz <sameo@rivosinc.com>,
	linux-pci@vger.kernel.org, gregkh@linuxfoundation.org
Subject: Re: [PATCH 08/11] PCI/IDE: Add IDE establishment helpers
Date: Wed, 8 Jan 2025 04:00:25 +0800	[thread overview]
Message-ID: <Z32H2Tzd1UHCQEt5@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <6d50f215-93c4-49a5-9ee2-f9775b740f92@amd.com>

> > > +static void __pci_ide_stream_setup(struct pci_dev *pdev, struct
> > > pci_ide *ide)
> > > +{
> > > +    int pos;
> > > +    u32 val;
> > > +
> > > +    pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id,
> > > +                 pdev->nr_ide_mem);
> > > +
> > > +    val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT_MASK, ide->devid_end);
> > > +    pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, val);
> > > +
> > > +    val = FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) |
> > > +          FIELD_PREP(PCI_IDE_SEL_RID_2_BASE_MASK, ide->devid_start) |
> > > +          FIELD_PREP(PCI_IDE_SEL_RID_2_SEG_MASK, ide->domain);
> > > +    pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, val);
> > > +
> > > +    for (int i = 0; i < ide->nr_mem; i++) {
> > 
> > 
> > This needs to test that (pdev->nr_ide_mem >= ide->nr_mem), easy to miss
> > especially when PCI_IDE_SETUP_ROOT_PORT. Thanks,

Yes, but nr_ide_mem is limited HW resource and may easily smaller than
device memory region number. In this case, maybe we have to merge the
memory regions into one big range.

> > 
> > 
> > 
> > > +        val = FIELD_PREP(PCI_IDE_SEL_ADDR_1_VALID, 1) |
> > > +              FIELD_PREP(PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK,
> > > +                 lower_32_bits(ide->mem[i].start) >>
> > > +                     PCI_IDE_SEL_ADDR_1_BASE_LOW_SHIFT) |
> > > +              FIELD_PREP(PCI_IDE_SEL_ADDR_1_LIMIT_LOW_MASK,
> > > +                 lower_32_bits(ide->mem[i].end) >>
> > > +                     PCI_IDE_SEL_ADDR_1_LIMIT_LOW_SHIFT);
> > > +        pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), val);
> > > +
> > > +        val = upper_32_bits(ide->mem[i].end);
> > > +        pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), val);
> > > +
> > > +        val = upper_32_bits(ide->mem[i].start);
> > > +        pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), val);
> > > +    }
> > > +}
> > > +
> > > +/*
> > > + * Establish IDE stream parameters in @pdev and, optionally, its
> > > root port
> > > + */
> > > +int pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide,
> > > +             enum pci_ide_flags flags)
> > > +{
> > > +    struct pci_host_bridge *hb = pci_find_host_bridge(pdev->bus);
> > > +    struct pci_dev *rp = pcie_find_root_port(pdev);
> > > +    int mem = 0, rc;
> > > +
> > > +    if (ide->stream_id < 0 || ide->stream_id > U8_MAX) {
> > > +        pci_err(pdev, "Setup fail: Invalid stream id: %d\n",
> > > ide->stream_id);
> > > +        return -ENXIO;
> > > +    }
> > > +
> > > +    if (test_and_set_bit_lock(ide->stream_id, hb->ide_stream_ids)) {
> > > +        pci_err(pdev, "Setup fail: Busy stream id: %d\n",
> > > +            ide->stream_id);
> > > +        return -EBUSY;
> > > +    }
> > > +
> > > +    ide->name = kasprintf(GFP_KERNEL, "stream%d:%s", ide->stream_id,
> > > +                  dev_name(&pdev->dev));
> > > +    if (!ide->name) {
> > > +        rc = -ENOMEM;
> > > +        goto err_name;
> > > +    }
> > > +
> > > +    rc = sysfs_create_link(&hb->dev.kobj, &pdev->dev.kobj, ide->name);
> > > +    if (rc)
> > > +        goto err_link;
> > > +
> > > +    for (mem = 0; mem < ide->nr_mem; mem++)
> > > +        if (!__request_region(&hb->ide_stream_res, ide->mem[mem].start,
> > > +                      range_len(&ide->mem[mem]), ide->name,
> > > +                      0)) {
> > > +            pci_err(pdev,
> > > +                "Setup fail: stream%d: address association conflict
> > > [%#llx-%#llx]\n",
> > > +                ide->stream_id, ide->mem[mem].start,
> > > +                ide->mem[mem].end);
> > > +
> > > +            rc = -EBUSY;
> > > +            goto err;
> > > +        }
> > > +
> > > +    __pci_ide_stream_setup(pdev, ide);
> > > +    if (flags & PCI_IDE_SETUP_ROOT_PORT)
> > > +        __pci_ide_stream_setup(rp, ide);
> 
> Oh, when we do this, the root port gets the same devid_start/end as the
> device which is not correct, what should be there, the rootport bdfn? Need

"Indicates the lowest/highest value RID in the range
associated with this Stream ID at the IDE *Partner* Port"

My understanding is that device should fill the RP bdfn, and the RP
should fill the device bdfn for RID association registers. Same for Addr
association registers.

Thanks,
Yilun

> to dig that but PCI_IDE_SETUP_ROOT_PORT should detect that it is a root
> port. Thanks,
> 

  reply	other threads:[~2025-01-08  8:01 UTC|newest]

Thread overview: 125+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-05 22:23 [PATCH 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2024-12-05 22:23 ` [PATCH 01/11] configfs-tsm: Namespace TSM report symbols Dan Williams
2024-12-10  6:08   ` Alexey Kardashevskiy
2024-12-11 13:55   ` Suzuki K Poulose
2024-12-05 22:23 ` [PATCH 02/11] coco/guest: Move shared guest CC infrastructure to drivers/virt/coco/guest/ Dan Williams
2024-12-10  6:09   ` Alexey Kardashevskiy
2024-12-05 22:23 ` [PATCH 03/11] coco/tsm: Introduce a class device for TEE Security Managers Dan Williams
2025-01-28 12:17   ` Jonathan Cameron
2025-02-25 21:08     ` Dan Williams
2024-12-05 22:23 ` [PATCH 04/11] PCI/IDE: Selective Stream IDE enumeration Dan Williams
2024-12-10  3:08   ` Aneesh Kumar K.V
2024-12-12  6:32     ` Xu Yilun
2025-02-22  0:42       ` Dan Williams
2025-02-20  3:17     ` Dan Williams
2024-12-10  6:18   ` Alexey Kardashevskiy
2025-02-20  3:59     ` Dan Williams
2024-12-10  7:05   ` Alexey Kardashevskiy
2024-12-12  6:06     ` Xu Yilun
2024-12-18 10:35       ` Alexey Kardashevskiy
2025-02-22  0:30       ` Dan Williams
2025-02-20 18:07     ` Dan Williams
2025-02-21  0:53       ` Alexey Kardashevskiy
2025-02-27 23:46         ` Dan Williams
2024-12-10 19:24   ` Bjorn Helgaas
2025-02-22  0:13     ` Dan Williams
2025-01-30 10:45   ` Jonathan Cameron
2025-02-26  0:21     ` Dan Williams
2024-12-05 22:23 ` [PATCH 05/11] PCI/TSM: Authenticate devices via platform TSM Dan Williams
2024-12-10 10:18   ` Alexey Kardashevskiy
2025-02-21  8:13     ` Aneesh Kumar K.V
2025-02-25  7:17       ` Xu Yilun
2025-02-26 12:10         ` Aneesh Kumar K.V
2025-02-26 12:13           ` [RFC PATCH 1/7] tsm: Select PCI_DOE which is required for PCI_TSM Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 2/7] tsm: Move tsm core outside the host directory Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 3/7] tsm: vfio: Add tsm bind/unbind support Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 4/7] tsm: Allow tsm ops function to be called for multi-function devices Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 5/7] tsm: Don't error out for doe mailbox failure Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 6/7] tsm: Allow tsm connect ops to be used for multiple operations Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 7/7] tsm: Add secure SPDM support Aneesh Kumar K.V (Arm)
2025-02-27  6:50               ` Xu Yilun
2025-02-27  6:35           ` [PATCH 05/11] PCI/TSM: Authenticate devices via platform TSM Xu Yilun
2025-02-27 13:57             ` Aneesh Kumar K.V
2025-02-28  1:26               ` Xu Yilun
2025-02-28  9:48                 ` Aneesh Kumar K.V
2025-03-01  7:50                   ` Xu Yilun
2025-03-07  3:07                   ` Alexey Kardashevskiy
2025-02-27 19:53           ` Dan Williams
2025-02-28 10:06             ` Aneesh Kumar K.V
2025-02-21 20:42     ` Dan Williams
2025-02-25  4:45       ` Alexey Kardashevskiy
2025-02-28  3:09         ` Dan Williams
2024-12-10 18:52   ` Bjorn Helgaas
2025-02-21 22:32     ` Dan Williams
2024-12-12  9:50   ` Xu Yilun
2025-02-22  1:15     ` Dan Williams
2025-02-24 11:02       ` Xu Yilun
2025-02-28  0:15         ` Dan Williams
2025-02-28  9:39           ` Xu Yilun
2025-01-30 11:45   ` Jonathan Cameron
2025-02-26  0:50     ` Dan Williams
2024-12-05 22:23 ` [PATCH 06/11] samples/devsec: PCI device-security bus / endpoint sample Dan Williams
2024-12-06  4:23   ` kernel test robot
2024-12-09  3:40   ` kernel test robot
2025-01-30 13:21   ` Jonathan Cameron
2025-02-26  2:00     ` Dan Williams
2024-12-05 22:23 ` [PATCH 07/11] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2024-12-09 13:17   ` Ilpo Järvinen
2025-02-20  3:05     ` Dan Williams
2025-02-20  3:09       ` Dan Williams
2024-12-10 19:21   ` Bjorn Helgaas
2024-12-11 13:22     ` Ilpo Järvinen
2025-02-22  0:15       ` Dan Williams
2025-02-24 15:09         ` Ilpo Järvinen
2025-02-28  0:29           ` Dan Williams
2025-02-21 23:34     ` Dan Williams
2025-02-25  2:25       ` Alexey Kardashevskiy
2024-12-05 22:24 ` [PATCH 08/11] PCI/IDE: Add IDE establishment helpers Dan Williams
2024-12-10  3:19   ` Aneesh Kumar K.V
2024-12-10  3:37     ` Aneesh Kumar K.V
2025-02-20  3:39       ` Dan Williams
2025-02-21 15:53         ` Aneesh Kumar K.V
2025-02-25  0:46           ` Dan Williams
2025-01-07 20:19     ` Xu Yilun
2025-01-10 13:25       ` Aneesh Kumar K.V
2025-02-24 22:31         ` Dan Williams
2025-02-25  2:29           ` Alexey Kardashevskiy
2025-02-20  3:28     ` Dan Williams
2024-12-10  7:07   ` Alexey Kardashevskiy
2025-02-20 21:44     ` Dan Williams
2024-12-10 18:47   ` Bjorn Helgaas
2025-02-21 22:02     ` Dan Williams
2024-12-12 10:50   ` Xu Yilun
2024-12-19  7:25   ` Alexey Kardashevskiy
2024-12-19 10:05     ` Alexey Kardashevskiy
2025-01-07 20:00       ` Xu Yilun [this message]
2025-01-09  2:35         ` Alexey Kardashevskiy
2025-01-09 21:28           ` Xu Yilun
2025-01-15  0:20             ` Alexey Kardashevskiy
2025-02-25  0:06               ` Dan Williams
2025-02-25  3:39                 ` Alexey Kardashevskiy
2025-02-28  2:26                   ` Dan Williams
2025-03-04  0:03                     ` Alexey Kardashevskiy
2025-03-04  0:57                       ` Dan Williams
2025-03-04  1:31                         ` Alexey Kardashevskiy
2025-03-04 17:59                           ` Dan Williams
2025-02-20  4:19             ` Alexey Kardashevskiy
2025-02-24 22:24         ` Dan Williams
2025-02-25  2:45           ` Xu Yilun
2025-02-24 20:28       ` Dan Williams
2025-02-26  1:54         ` Alexey Kardashevskiy
2025-02-24 20:24     ` Dan Williams
2025-02-25  5:01       ` Xu Yilun
2024-12-05 22:24 ` [PATCH 09/11] PCI/IDE: Report available IDE streams Dan Williams
2024-12-06  0:12   ` kernel test robot
2024-12-06  0:43   ` kernel test robot
2025-02-11  6:10   ` Alexey Kardashevskiy
2025-02-27 23:35     ` Dan Williams
2024-12-05 22:24 ` [PATCH 10/11] PCI/TSM: Report active " Dan Williams
2024-12-10 18:49   ` Bjorn Helgaas
2025-02-21 22:28     ` Dan Williams
2024-12-05 22:24 ` [PATCH 11/11] samples/devsec: Add sample IDE establishment Dan Williams
2025-01-30 13:39   ` Jonathan Cameron
2025-02-27 23:27     ` Dan Williams
2024-12-06  6:05 ` [PATCH 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP) Greg KH
2024-12-06  8:44   ` Dan Williams

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