Re: [PATCH v4 04/10] cpu/bugs: Allow spectre_v2=ibrs on x86 vendors other than Intel

[Kim Phillips <kim.phillips@amd.com>]

On 8/18/26 8:17 PM, Pawan Gupta wrote:
> On Tue, Aug 04, 2026 at 06:56:05PM -0500, Kim Phillips wrote:
> ...
>> @@ -2297,13 +2299,26 @@ static void __init spectre_v2_apply_mitigation(void)
>>   	if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
>>   		pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
>>   
>> -	if (spectre_v2_in_ibrs_mode(spectre_v2_enabled)) {
>> -		if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) {
>> +	/*
>> +	 * head_64.S preserves EFER.AUTOIBRS across boot, so a kexec from a
>> +	 * kernel that ran in AutoIBRS mode carries the bit into the new kernel.
>> +	 * Explicitly set or clear it to match the selected mitigation, regardless
>> +	 * of which mode is in effect.  The boot CPU does this before
>> +	 * init_real_mode() snapshots EFER for the AP trampoline, so APs inherit
>> +	 * the correct value too.
>> +	 */
>> +	if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) {
>> +		if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
>>   			msr_set_bit(MSR_EFER, _EFER_AUTOIBRS);
>> -		} else {
>> -			x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
>> -			update_spec_ctrl(x86_spec_ctrl_base);
>> -		}
>> +		else
>> +			msr_clear_bit(MSR_EFER, _EFER_AUTOIBRS);
> Clearing the old kernel state should be done well before the mitigation
> selection starts, below already does it for the SPEC_CTRL MSR:
>
>    void __init cpu_select_mitigations(void)
>    {
>            /*
>             * Read the SPEC_CTRL MSR to account for reserved bits which may
>             * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
>             * init code as it is not enumerated and depends on the family.
>             */
>            if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
>                    rdmsrq(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
>
>                    /*
>                     * Previously running kernel (kexec), may have some controls
>                     * turned ON. Clear them and let the mitigations setup below
>                     * rediscover them based on configuration.
>                     */
>                    x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
>            }

Thanks, I've addressed this in v5.

>> +	}
>> +
>> +	if (spectre_v2_in_ibrs_mode(spectre_v2_enabled) &&
>> +	    !(boot_cpu_has(X86_FEATURE_AUTOIBRS) &&
>> +	      spectre_v2_in_eibrs_mode(spectre_v2_enabled))) {
>> +		x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
>> +		update_spec_ctrl(x86_spec_ctrl_base);
>>   	}
> Nit, I find this a bit confusing. IIUC when AutoIBRS is supported, you want
> SPEC_CTRL[IBRS] to be set when legacy IBRS mitigation is deployed. If you
> move MSR write down after legacy IBRS mode is set(KERNEL_IBRS), you can do:
>
>            if (spectre_v2_in_ibrs_mode(spectre_v2_enabled)) {
>                   if (boot_cpu_has(X86_FEATURE_AUTOIBRS) &&
>                       !boot_cpu_has(X86_FEATURE_KERNEL_IBRS)) {    <---- just adding KERNEL_IBRS check to existing code
>                            msr_set_bit(MSR_EFER, _EFER_AUTOIBRS);
>                    } else {
>                            x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
>                            update_spec_ctrl(x86_spec_ctrl_base);
>                    }
>            }
>
> Otherwise, a comment explaining the intent would be helpful.

Right, also addressed in v5.

Please take another look.

Thanks,

Kim