Re: [PATCH 3/3] tools/testing/cxl: Add interleave check support to mock cxl port device

[Dave Jiang <dave.jiang@intel.com>]

On 8/9/2022 9:21 AM, Dan Williams wrote:
> Dave Jiang wrote:
>> Attach the cxl mock hdm to the port device to allow cxl_interleave_verify()
>> to check the interleave configuration. Set the interleave_mask as well
>> to support the new verification code.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>>   tools/testing/cxl/test/cxl.c |    2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
>> index a072b2d3e726..5a9f33703ee7 100644
>> --- a/tools/testing/cxl/test/cxl.c
>> +++ b/tools/testing/cxl/test/cxl.c
>> @@ -398,6 +398,8 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port)
>>   		return ERR_PTR(-ENOMEM);
>>   
>>   	cxlhdm->port = port;
>> +	cxlhdm->interleave_mask = GENMASK(14, 8);
>> +	dev_set_drvdata(&port->dev, cxlhdm);
> This would also need to set cxlhdm->interleave_cap.
Yes with the suggested change in the previous patch, we need to set the 
default 1, 2, 4, 8 bits.
>
> I accidentally called it port->interleave_cap in the last mail, but it
> belong in cxlhdm.