From: Alison Schofield <alison.schofield@intel.com>
To: "Jiang, Dave" <dave.jiang@intel.com>
Cc: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"Williams, Dan J" <dan.j.williams@intel.com>,
"Verma, Vishal L" <vishal.l.verma@intel.com>,
"Weiny, Ira" <ira.weiny@intel.com>,
"Jonathan.Cameron@huawei.com" <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH 1/3] cxl: Add check for result of interleave ways plus granularity combo
Date: Tue, 9 Aug 2022 10:06:30 -0700 [thread overview]
Message-ID: <20220809170630.GA1756195@alison-desk> (raw)
In-Reply-To: <165999281717.493131.1159254270127915425.stgit@djiang5-desk4.jf.intel.com>
Dave - Haven't reviewed yet, but wanted to drop this tidbit -
On Mon, Aug 08, 2022 at 02:06:57PM -0700, Dave Jiang wrote:
> Add a helper function to check the combination of interleave ways and
> interleave granularity together is sane against the interleave mask from
> the HDM decoder. Add the check to cxl_region_attach() to make sure the
> region config is sane. Add the check to cxl_port_setup_targets() to make
> sure the port setup config is also sane.
>
> Calculation refers to CXL spec v3 8.2.4.19.13 implementation note #3.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
snip
> +static inline int cxl_interleave_verify(struct cxl_port *port,
> + int ways, int granularity)
> +{
> + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
> + unsigned int addr_mask;
> + u16 ig;
> + u8 iw;
s/ig/eig
s/iw/eiw
For consistency, let's use the "e" version of these names to mean
encoded value.
> + int rc;
> +
> + rc = granularity_to_cxl(granularity, &ig);
> + if (rc)
> + return rc;
> +
> + rc = ways_to_cxl(ways, &iw);
> + if (rc)
> + return rc;
> +
> + if (iw == 0)
> + return 0;
> +
> + if (iw < CXL_INTERLEAVE_3_WAY)
> + addr_mask = GENMASK(ig + 8 + iw - 1, ig + 8);
> + else
> + addr_mask = GENMASK((ig + iw) / 3 - 1, ig + 8);
> +
> + if (~cxlhdm->interleave_mask & addr_mask)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> struct seq_file;
> struct dentry *cxl_debugfs_create_dir(const char *dir);
> void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
>
>
next prev parent reply other threads:[~2022-08-09 17:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-08 21:06 [PATCH 0/3] Add sanity check for interleave setup Dave Jiang
2022-08-08 21:06 ` [PATCH 1/3] cxl: Add check for result of interleave ways plus granularity combo Dave Jiang
2022-08-09 16:18 ` Dan Williams
2022-08-11 23:18 ` Dave Jiang
2022-08-09 17:06 ` Alison Schofield [this message]
2022-08-11 23:33 ` Dave Jiang
2022-08-08 21:07 ` [PATCH 2/3] cxl: Add CXL spec v3.0 interleave support Dave Jiang
2022-08-09 16:20 ` Dan Williams
2022-08-11 23:19 ` Dave Jiang
2022-08-08 21:07 ` [PATCH 3/3] tools/testing/cxl: Add interleave check support to mock cxl port device Dave Jiang
2022-08-09 16:21 ` Dan Williams
2022-08-11 23:22 ` Dave Jiang
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