From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <linuxarm@huawei.com>, <qemu-devel@nongnu.org>,
<alex.bennee@linaro.org>, Marcel Apfelbaum <marcel@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Igor Mammedov <imammedo@redhat.com>,
Markus Armbruster <armbru@redhat.com>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Adam Manzanares <a.manzanares@samsung.com>,
Tong Zhang <ztong0001@gmail.com>
Cc: <linux-cxl@vger.kernel.org>,
Ben Widawsky <ben.widawsky@intel.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
<f4bug@amsat.org>, Peter Xu <peterx@redhat.com>,
David Hildenbrand <david@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Saransh Gupta1 <saransh@ibm.com>,
Shreyas Shah <shreyas.shah@elastics.cloud>,
Chris Browy <cbrowy@avery-design.com>,
"Samarth Saxena" <samarths@cadence.com>,
Dan Williams <dan.j.williams@intel.com>, <k.jensen@samsung.com>,
<dave@stgolabs.net>,
Alison Schofield <alison.schofield@intel.com>
Subject: [PATCH v10 09/45] hw/cxl/device: Timestamp implementation (8.2.9.3)
Date: Fri, 29 Apr 2022 15:40:34 +0100 [thread overview]
Message-ID: <20220429144110.25167-10-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220429144110.25167-1-Jonathan.Cameron@huawei.com>
From: Ben Widawsky <ben.widawsky@intel.com>
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/cxl/cxl-mailbox-utils.c | 42 +++++++++++++++++++++++++++++++++++++
include/hw/cxl/cxl_device.h | 6 ++++++
2 files changed, 48 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index fb1f53f48e..4584aa31f7 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -44,6 +44,9 @@ enum {
#define CLEAR_RECORDS 0x1
#define GET_INTERRUPT_POLICY 0x2
#define SET_INTERRUPT_POLICY 0x3
+ TIMESTAMP = 0x03,
+ #define GET 0x0
+ #define SET 0x1
};
/* 8.2.8.4.5.1 Command Return Codes */
@@ -106,9 +109,46 @@ DEFINE_MAILBOX_HANDLER_NOP(events_clear_records);
DEFINE_MAILBOX_HANDLER_ZEROED(events_get_interrupt_policy, 4);
DEFINE_MAILBOX_HANDLER_NOP(events_set_interrupt_policy);
+/* 8.2.9.3.1 */
+static ret_code cmd_timestamp_get(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
+{
+ uint64_t time, delta;
+ uint64_t final_time = 0;
+
+ if (cxl_dstate->timestamp.set) {
+ /* First find the delta from the last time the host set the time. */
+ time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ delta = time - cxl_dstate->timestamp.last_set;
+ final_time = cxl_dstate->timestamp.host_set + delta;
+ }
+
+ /* Then adjust the actual time */
+ stq_le_p(cmd->payload, final_time);
+ *len = 8;
+
+ return CXL_MBOX_SUCCESS;
+}
+
+/* 8.2.9.3.2 */
+static ret_code cmd_timestamp_set(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
+{
+ cxl_dstate->timestamp.set = true;
+ cxl_dstate->timestamp.last_set = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+ cxl_dstate->timestamp.host_set = le64_to_cpu(*(uint64_t *)cmd->payload);
+
+ *len = 0;
+ return CXL_MBOX_SUCCESS;
+}
+
static QemuUUID cel_uuid;
#define IMMEDIATE_CONFIG_CHANGE (1 << 1)
+#define IMMEDIATE_POLICY_CHANGE (1 << 3)
#define IMMEDIATE_LOG_CHANGE (1 << 4)
static struct cxl_cmd cxl_cmd_set[256][256] = {
@@ -120,6 +160,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
cmd_events_get_interrupt_policy, 0, 0 },
[EVENTS][SET_INTERRUPT_POLICY] = { "EVENTS_SET_INTERRUPT_POLICY",
cmd_events_set_interrupt_policy, 4, IMMEDIATE_CONFIG_CHANGE },
+ [TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 },
+ [TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set, 8, IMMEDIATE_POLICY_CHANGE },
};
void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 954205653e..797a22ddb4 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -111,6 +111,12 @@ typedef struct cxl_device_state {
size_t cel_size;
};
+ struct {
+ bool set;
+ uint64_t last_set;
+ uint64_t host_set;
+ } timestamp;
+
/* memory region for persistent memory, HDM */
uint64_t pmem_size;
} CXLDeviceState;
--
2.32.0
next prev parent reply other threads:[~2022-04-29 14:46 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-29 14:40 [PATCH v10 00/45] CXl 2.0 emulation Support Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 01/45] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 02/45] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-05-30 17:50 ` Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 03/45] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 04/45] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 05/45] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 06/45] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 07/45] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 08/45] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-04-29 14:40 ` Jonathan Cameron [this message]
2022-04-29 14:40 ` [PATCH v10 10/45] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 11/45] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 12/45] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 13/45] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-05-21 9:11 ` Paolo Bonzini
2022-04-29 14:40 ` [PATCH v10 14/45] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 15/45] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 16/45] hw/cxl/rp: Add a root port Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 17/45] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2023-09-13 12:20 ` Philippe Mathieu-Daudé
2022-04-29 14:40 ` [PATCH v10 18/45] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 19/45] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 20/45] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 21/45] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 22/45] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 23/45] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 24/45] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 25/45] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 26/45] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 27/45] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-05-21 9:07 ` Paolo Bonzini
2022-05-23 15:15 ` Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 28/45] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 29/45] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 30/45] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 31/45] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 32/45] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 33/45] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 34/45] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 35/45] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 36/45] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 37/45] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 38/45] tests/acpi: Add tables " Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 39/45] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 40/45] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 41/45] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 42/45] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 43/45] pci-bridge/cxl_upstream: Add a CXL switch upstream port Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 44/45] pci-bridge/cxl_downstream: Add a CXL switch downstream port Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 45/45] docs/cxl: Add switch documentation Jonathan Cameron
2022-05-13 10:16 ` [PATCH v10 00/45] CXl 2.0 emulation Support Michael S. Tsirkin
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