From: Paolo Bonzini <pbonzini@redhat.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linuxarm@huawei.com, qemu-devel@nongnu.org,
alex.bennee@linaro.org, Marcel Apfelbaum <marcel@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Igor Mammedov <imammedo@redhat.com>,
Markus Armbruster <armbru@redhat.com>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Adam Manzanares <a.manzanares@samsung.com>,
Tong Zhang <ztong0001@gmail.com>
Cc: linux-cxl@vger.kernel.org, Ben Widawsky <ben.widawsky@intel.com>,
Peter Maydell <peter.maydell@linaro.org>,
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
f4bug@amsat.org, Peter Xu <peterx@redhat.com>,
David Hildenbrand <david@redhat.com>,
Saransh Gupta1 <saransh@ibm.com>,
Shreyas Shah <shreyas.shah@elastics.cloud>,
Chris Browy <cbrowy@avery-design.com>,
Samarth Saxena <samarths@cadence.com>,
Dan Williams <dan.j.williams@intel.com>,
k.jensen@samsung.com, dave@stgolabs.net,
Alison Schofield <alison.schofield@intel.com>
Subject: Re: [PATCH v10 13/45] cxl: Machine level control on whether CXL support is enabled
Date: Sat, 21 May 2022 11:11:00 +0200 [thread overview]
Message-ID: <c3dcb335-1a7f-b8d4-ee77-8b00aefcb274@redhat.com> (raw)
In-Reply-To: <20220429144110.25167-14-Jonathan.Cameron@huawei.com>
On 4/29/22 16:40, Jonathan Cameron via wrote:
> From: Jonathan Cameron <jonathan.cameron@huawei.com>
>
> There are going to be some potential overheads to CXL enablement,
> for example the host bridge region reserved in memory maps.
> Add a machine level control so that CXL is disabled by default.
>
> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/core/machine.c | 28 ++++++++++++++++++++++++++++
> hw/i386/pc.c | 1 +
> include/hw/boards.h | 2 ++
> include/hw/cxl/cxl.h | 4 ++++
> 4 files changed, 35 insertions(+)
Another belated review, I think this shouldn't be added to machines that
do not support CXL (yes, there are options like -M usb but they are from
olden times---and CXL is a little more niche, too :)).
Can you move the CXL code for machines to e.g. hw/cxl/machine.c and have
the various machines call back into hooks to add the properties, resolve
the memory window targets etc.?. A CXLState* like cxl_devices_state can
be added to the machines and passed as CXLState** to one of these hooks.
Thanks,
Paolo
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index cb9bbc844d..6ae2997f16 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -31,6 +31,7 @@
> #include "sysemu/qtest.h"
> #include "hw/pci/pci.h"
> #include "hw/mem/nvdimm.h"
> +#include "hw/cxl/cxl.h"
> #include "migration/global_state.h"
> #include "migration/vmstate.h"
> #include "exec/confidential-guest-support.h"
> @@ -550,6 +551,20 @@ static void machine_set_nvdimm_persistence(Object *obj, const char *value,
> nvdimms_state->persistence_string = g_strdup(value);
> }
>
> +static bool machine_get_cxl(Object *obj, Error **errp)
> +{
> + MachineState *ms = MACHINE(obj);
> +
> + return ms->cxl_devices_state->is_enabled;
> +}
> +
> +static void machine_set_cxl(Object *obj, bool value, Error **errp)
> +{
> + MachineState *ms = MACHINE(obj);
> +
> + ms->cxl_devices_state->is_enabled = value;
> +}
> +
> void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
> {
> QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
> @@ -782,6 +797,8 @@ static void machine_class_init(ObjectClass *oc, void *data)
> mc->default_ram_size = 128 * MiB;
> mc->rom_file_has_mr = true;
>
> + /* Few machines support CXL, so default to off */
> + mc->cxl_supported = false;
> /* numa node memory size aligned on 8MB by default.
> * On Linux, each node's border has to be 8MB aligned
> */
> @@ -927,6 +944,16 @@ static void machine_initfn(Object *obj)
> "Valid values are cpu, mem-ctrl");
> }
>
> + if (mc->cxl_supported) {
> + Object *obj = OBJECT(ms);
> +
> + ms->cxl_devices_state = g_new0(CXLState, 1);
> + object_property_add_bool(obj, "cxl", machine_get_cxl, machine_set_cxl);
> + object_property_set_description(obj, "cxl",
> + "Set on/off to enable/disable "
> + "CXL instantiation");
> + }
> +
> if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
> ms->numa_state = g_new0(NumaState, 1);
> object_property_add_bool(obj, "hmat",
> @@ -961,6 +988,7 @@ static void machine_finalize(Object *obj)
> g_free(ms->device_memory);
> g_free(ms->nvdimms_state);
> g_free(ms->numa_state);
> + g_free(ms->cxl_devices_state);
> }
>
> bool machine_usb(MachineState *machine)
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 23bba9d82c..b752339beb 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1761,6 +1761,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
> mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
> mc->nvdimm_supported = true;
> mc->smp_props.dies_supported = true;
> + mc->cxl_supported = true;
> mc->default_ram_id = "pc.ram";
>
> object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
> diff --git a/include/hw/boards.h b/include/hw/boards.h
> index d64b5481e8..f756a1d5fc 100644
> --- a/include/hw/boards.h
> +++ b/include/hw/boards.h
> @@ -269,6 +269,7 @@ struct MachineClass {
> bool ignore_boot_device_suffixes;
> bool smbus_no_migration_support;
> bool nvdimm_supported;
> + bool cxl_supported;
> bool numa_mem_supported;
> bool auto_enable_numa;
> SMPCompatProps smp_props;
> @@ -360,6 +361,7 @@ struct MachineState {
> CPUArchIdList *possible_cpus;
> CpuTopology smp;
> struct NVDIMMState *nvdimms_state;
> + struct CXLState *cxl_devices_state;
> struct NumaState *numa_state;
> };
>
> diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
> index 554ad93b6b..31af92fd5e 100644
> --- a/include/hw/cxl/cxl.h
> +++ b/include/hw/cxl/cxl.h
> @@ -17,4 +17,8 @@
> #define CXL_COMPONENT_REG_BAR_IDX 0
> #define CXL_DEVICE_REG_BAR_IDX 2
>
> +typedef struct CXLState {
> + bool is_enabled;
> +} CXLState;
> +
> #endif
next prev parent reply other threads:[~2022-05-21 9:11 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-29 14:40 [PATCH v10 00/45] CXl 2.0 emulation Support Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 01/45] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 02/45] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-05-30 17:50 ` Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 03/45] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 04/45] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 05/45] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 06/45] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 07/45] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 08/45] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 09/45] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 10/45] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 11/45] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 12/45] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 13/45] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-05-21 9:11 ` Paolo Bonzini [this message]
2022-04-29 14:40 ` [PATCH v10 14/45] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 15/45] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 16/45] hw/cxl/rp: Add a root port Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 17/45] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2023-09-13 12:20 ` Philippe Mathieu-Daudé
2022-04-29 14:40 ` [PATCH v10 18/45] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 19/45] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 20/45] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 21/45] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 22/45] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 23/45] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 24/45] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 25/45] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 26/45] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 27/45] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-05-21 9:07 ` Paolo Bonzini
2022-05-23 15:15 ` Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 28/45] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 29/45] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 30/45] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 31/45] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 32/45] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 33/45] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 34/45] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 35/45] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 36/45] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 37/45] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 38/45] tests/acpi: Add tables " Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 39/45] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 40/45] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 41/45] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 42/45] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 43/45] pci-bridge/cxl_upstream: Add a CXL switch upstream port Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 44/45] pci-bridge/cxl_downstream: Add a CXL switch downstream port Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 45/45] docs/cxl: Add switch documentation Jonathan Cameron
2022-05-13 10:16 ` [PATCH v10 00/45] CXl 2.0 emulation Support Michael S. Tsirkin
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