From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <linuxarm@huawei.com>, <qemu-devel@nongnu.org>,
<alex.bennee@linaro.org>, Marcel Apfelbaum <marcel@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Igor Mammedov <imammedo@redhat.com>,
Markus Armbruster <armbru@redhat.com>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Adam Manzanares <a.manzanares@samsung.com>,
Tong Zhang <ztong0001@gmail.com>
Cc: <linux-cxl@vger.kernel.org>,
Ben Widawsky <ben.widawsky@intel.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
<f4bug@amsat.org>, Peter Xu <peterx@redhat.com>,
David Hildenbrand <david@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Saransh Gupta1 <saransh@ibm.com>,
Shreyas Shah <shreyas.shah@elastics.cloud>,
Chris Browy <cbrowy@avery-design.com>,
"Samarth Saxena" <samarths@cadence.com>,
Dan Williams <dan.j.williams@intel.com>, <k.jensen@samsung.com>,
<dave@stgolabs.net>,
Alison Schofield <alison.schofield@intel.com>
Subject: [PATCH v10 26/45] hw/cxl/component: Add utils for interleave parameter encoding/decoding
Date: Fri, 29 Apr 2022 15:40:51 +0100 [thread overview]
Message-ID: <20220429144110.25167-27-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220429144110.25167-1-Jonathan.Cameron@huawei.com>
From: Jonathan Cameron <jonathan.cameron@huawei.com>
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/cxl/cxl-component-utils.c | 34 ++++++++++++++++++++++++++++++++++
include/hw/cxl/cxl_component.h | 8 ++++++++
2 files changed, 42 insertions(+)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index afc97b17c2..69cb07171c 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -9,6 +9,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "qapi/error.h"
#include "hw/pci/pci.h"
#include "hw/cxl/cxl.h"
@@ -329,3 +330,36 @@ void cxl_component_create_dvsec(CXLComponentState *cxl,
range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length);
cxl->dvsec_offset += length;
}
+
+uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
+{
+ switch (iw) {
+ case 1: return 0x0;
+ case 2: return 0x1;
+ case 4: return 0x2;
+ case 8: return 0x3;
+ case 16: return 0x4;
+ case 3: return 0x8;
+ case 6: return 0x9;
+ case 12: return 0xa;
+ default:
+ error_setg(errp, "Interleave ways: %d not supported", iw);
+ return 0;
+ }
+}
+
+uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
+{
+ switch (gran) {
+ case 256: return 0;
+ case 512: return 1;
+ case 1024: return 2;
+ case 2048: return 3;
+ case 4096: return 4;
+ case 8192: return 5;
+ case 16384: return 6;
+ default:
+ error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran);
+ return 0;
+ }
+}
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 7d8f395cbe..4f69688c47 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -210,4 +210,12 @@ static inline int cxl_decoder_count_enc(int count)
return 0;
}
+uint8_t cxl_interleave_ways_enc(int iw, Error **errp);
+uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp);
+
+static inline hwaddr cxl_decode_ig(int ig)
+{
+ return 1 << (ig + 8);
+}
+
#endif
--
2.32.0
next prev parent reply other threads:[~2022-04-29 14:54 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-29 14:40 [PATCH v10 00/45] CXl 2.0 emulation Support Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 01/45] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 02/45] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-05-30 17:50 ` Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 03/45] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 04/45] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 05/45] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 06/45] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 07/45] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 08/45] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 09/45] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 10/45] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 11/45] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 12/45] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 13/45] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-05-21 9:11 ` Paolo Bonzini
2022-04-29 14:40 ` [PATCH v10 14/45] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 15/45] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 16/45] hw/cxl/rp: Add a root port Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 17/45] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2023-09-13 12:20 ` Philippe Mathieu-Daudé
2022-04-29 14:40 ` [PATCH v10 18/45] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 19/45] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 20/45] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 21/45] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 22/45] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 23/45] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 24/45] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 25/45] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-04-29 14:40 ` Jonathan Cameron [this message]
2022-04-29 14:40 ` [PATCH v10 27/45] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-05-21 9:07 ` Paolo Bonzini
2022-05-23 15:15 ` Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 28/45] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 29/45] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 30/45] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 31/45] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 32/45] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 33/45] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-04-29 14:40 ` [PATCH v10 34/45] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 35/45] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 36/45] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 37/45] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 38/45] tests/acpi: Add tables " Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 39/45] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 40/45] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 41/45] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 42/45] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 43/45] pci-bridge/cxl_upstream: Add a CXL switch upstream port Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 44/45] pci-bridge/cxl_downstream: Add a CXL switch downstream port Jonathan Cameron
2022-04-29 14:41 ` [PATCH v10 45/45] docs/cxl: Add switch documentation Jonathan Cameron
2022-05-13 10:16 ` [PATCH v10 00/45] CXl 2.0 emulation Support Michael S. Tsirkin
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