Re: [PATCH v4 6/6] cxl: export intereleave capability as port sysfs attribute

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Wed, 17 Aug 2022 14:22:09 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Export the interleave capability as a sysfs attribute for a port. The
> exported mask is interpreted from the CXL HDM Decoder Capability Register
> (CXL spec v 8.2.4.19.1). Each bit in the mask represents the number of

State which spec in all references (this one is rev3.0)

Otherwise, whilst it's not a particularly intuitive interface, I guess it
works reasonably well.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> interleave ways the decoder supports. For example, CXL devices designed
> from CXL spec v2.0 supports 1, 2, 4, and 8 interleave ways. The exported
> mask would show 0x116. The exported sysfs attribute will help user region
> creation to do more valid configuration checking.
> 
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  Documentation/ABI/testing/sysfs-bus-cxl |   13 +++++++++++++
>  drivers/cxl/port.c                      |   10 ++++++++++
>  2 files changed, 23 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index c6f533f47e50..5a13806a77ab 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -203,6 +203,19 @@ Description:
>  		Interleave Capable" bit and the "AA14to12 Interleave Capable" bits
>  		are set.
>  
> +What:		/sys/bus/cxl/devices/endpointX/interleave_cap
> +		/sys/bus/cxl/devices/portX/interleave_cap
> +Date:		Aug, 2020
> +KernelVersion:	v6.1
> +Contact:	linux-cxl@vger.kernel.org
> +Description:
> +		(RO) Interleave capability mask from the HDM decoder attached to the
> +		port. Each bit in the mask represents the number of interleave ways
> +		the decoder supports. For CXL devices designed from CXL spec v2.0 or
> +		earlier, 1, 2, 4, and 8 interleave ways are supported. With CXL spec
> +		v3.0 or later, the capability register (CXL spec v3 8.2.4.19.1)
> +		indicates 3, 6, and 12 ways supported or 16 ways supported.
> +
>  What:		/sys/bus/cxl/devices/decoderX.Y/mode
>  Date:		May, 2022
>  KernelVersion:	v5.20
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 567f62fd4ded..f856a31bec65 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -132,8 +132,18 @@ static ssize_t interleave_mask_show(struct device *dev,
>  }
>  static DEVICE_ATTR_RO(interleave_mask);
>  
> +static ssize_t interleave_cap_show(struct device *dev, struct device_attribute *attr,
> +				   char *buf)
> +{
> +	struct cxl_hdm *cxlhdm = dev_get_drvdata(dev);
> +
> +	return sysfs_emit(buf, "%#lx\n", cxlhdm->interleave_cap);
> +}
> +static DEVICE_ATTR_RO(interleave_cap);
> +
>  static struct attribute *cxl_port_info_attributes[] = {
>  	&dev_attr_interleave_mask.attr,
> +	&dev_attr_interleave_cap.attr,
>  	NULL,
>  };
>  
> 
>