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From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: linux-cxl@vger.kernel.org, dan.j.williams@intel.com,
	vishal.l.verma@intel.com, ira.weiny@intel.com,
	alison.schofield@intel.com
Subject: Re: [PATCH v4 3/6] tools/testing/cxl: Add interleave check support to mock cxl port device
Date: Wed, 24 Aug 2022 14:13:54 -0700	[thread overview]
Message-ID: <a1f87adb-fe54-be84-5bdb-52dc27417474@intel.com> (raw)
In-Reply-To: <20220824155902.00007b3c@huawei.com>


On 8/24/2022 7:59 AM, Jonathan Cameron wrote:
> On Wed, 17 Aug 2022 14:21:53 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
>> Attach the cxl mock hdm to the port device to allow cxl_interleave_verify()
> I couldn't follow what was going on here, until I realized you've renamed
> this function.  Now cxl_interleave_capable().
>
> Are the tests broken (null dereference) between patch 1 and 3?
>
> Seem like dev_set_drvdata() should move to patch 1.
You are right. Will move.
>
>> to check the interleave configuration. Set the interleave_mask as well
>> to support the new verification code.
>>
>> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>>   tools/testing/cxl/test/cxl.c |    3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
>> index a072b2d3e726..3ce353a20b80 100644
>> --- a/tools/testing/cxl/test/cxl.c
>> +++ b/tools/testing/cxl/test/cxl.c
>> @@ -398,6 +398,9 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port)
>>   		return ERR_PTR(-ENOMEM);
>>   
>>   	cxlhdm->port = port;
>> +	cxlhdm->interleave_mask = GENMASK(14, 8);
>> +	cxlhdm->interleave_cap = CXL_HDM_INTERLEAVE_CAP_DEFAULT;
>> +	dev_set_drvdata(&port->dev, cxlhdm);
>>   	return cxlhdm;
>>   }
>>   
>>
>>

  reply	other threads:[~2022-08-24 21:13 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-17 21:21 [PATCH v4 0/6] Add sanity check for interleave setup Dave Jiang
2022-08-17 21:21 ` [PATCH v4 1/6] cxl: Add check for result of interleave ways plus granularity combo Dave Jiang
2022-08-17 21:21 ` [PATCH v4 2/6] cxl: Add CXL spec v3.0 interleave support Dave Jiang
2022-08-24 14:46   ` Jonathan Cameron
2022-08-24 21:03     ` Dave Jiang
2022-08-24 14:56   ` Jonathan Cameron
2022-08-24 21:04     ` Dave Jiang
2022-08-17 21:21 ` [PATCH v4 3/6] tools/testing/cxl: Add interleave check support to mock cxl port device Dave Jiang
2022-08-24 14:59   ` Jonathan Cameron
2022-08-24 21:13     ` Dave Jiang [this message]
2022-08-17 21:21 ` [PATCH v4 4/6] cxl: change cxl_port_attribute_groups naming to avoid confusion Dave Jiang
2022-08-24 14:48   ` Jonathan Cameron
2022-08-17 21:22 ` [PATCH v4 5/6] cxl: export interleave address mask as port sysfs attribute Dave Jiang
2022-08-24 14:34   ` Jonathan Cameron
2022-08-17 21:22 ` [PATCH v4 6/6] cxl: export intereleave capability " Dave Jiang
2022-08-24 14:28   ` Jonathan Cameron

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