From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<alison.schofield@intel.com>
Subject: Re: [PATCH v4 4/6] cxl: change cxl_port_attribute_groups naming to avoid confusion
Date: Wed, 24 Aug 2022 15:48:59 +0100 [thread overview]
Message-ID: <20220824154859.000006ca@huawei.com> (raw)
In-Reply-To: <166077131892.1743055.1029132844466334751.stgit@djiang5-desk4.jf.intel.com>
On Wed, 17 Aug 2022 14:21:58 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Both cxl/port.c and cxl/core/port.c have cxl_port_attribute_groups. Change
> cxl_port_attribute_groups in cxl/port.c to cxl_port_dynamic_attr_groups in
> order to avoid confusion.
>
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Fair enough I guess.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/port.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 5453771bf330..c4aa073b7e31 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -123,7 +123,7 @@ static struct attribute_group cxl_cdat_attribute_group = {
> .is_bin_visible = cxl_port_bin_attr_is_visible,
> };
>
> -static const struct attribute_group *cxl_port_attribute_groups[] = {
> +static const struct attribute_group *cxl_port_dynamic_attr_groups[] = {
> &cxl_cdat_attribute_group,
> NULL,
> };
> @@ -133,7 +133,7 @@ static struct cxl_driver cxl_port_driver = {
> .probe = cxl_port_probe,
> .id = CXL_DEVICE_PORT,
> .drv = {
> - .dev_groups = cxl_port_attribute_groups,
> + .dev_groups = cxl_port_dynamic_attr_groups,
> },
> };
>
>
>
next prev parent reply other threads:[~2022-08-24 14:49 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-17 21:21 [PATCH v4 0/6] Add sanity check for interleave setup Dave Jiang
2022-08-17 21:21 ` [PATCH v4 1/6] cxl: Add check for result of interleave ways plus granularity combo Dave Jiang
2022-08-17 21:21 ` [PATCH v4 2/6] cxl: Add CXL spec v3.0 interleave support Dave Jiang
2022-08-24 14:46 ` Jonathan Cameron
2022-08-24 21:03 ` Dave Jiang
2022-08-24 14:56 ` Jonathan Cameron
2022-08-24 21:04 ` Dave Jiang
2022-08-17 21:21 ` [PATCH v4 3/6] tools/testing/cxl: Add interleave check support to mock cxl port device Dave Jiang
2022-08-24 14:59 ` Jonathan Cameron
2022-08-24 21:13 ` Dave Jiang
2022-08-17 21:21 ` [PATCH v4 4/6] cxl: change cxl_port_attribute_groups naming to avoid confusion Dave Jiang
2022-08-24 14:48 ` Jonathan Cameron [this message]
2022-08-17 21:22 ` [PATCH v4 5/6] cxl: export interleave address mask as port sysfs attribute Dave Jiang
2022-08-24 14:34 ` Jonathan Cameron
2022-08-17 21:22 ` [PATCH v4 6/6] cxl: export intereleave capability " Dave Jiang
2022-08-24 14:28 ` Jonathan Cameron
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