From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
Ira Weiny <ira.weiny@intel.com>, <dan.j.williams@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
<rafael@kernel.org>, <lukas@wunner.de>
Subject: Re: [PATCH v4 01/23] cxl: Export QTG ids from CFMWS to sysfs
Date: Thu, 20 Apr 2023 09:51:52 +0100 [thread overview]
Message-ID: <20230420095152.00007ce3@Huawei.com> (raw)
In-Reply-To: <168193566778.1178687.6009753728429815467.stgit@djiang5-mobl3>
On Wed, 19 Apr 2023 13:21:07 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Export the QoS Throttling Group ID from the CXL Fixed Memory Window
> Structure (CFMWS) under the root decoder sysfs attributes.
> CXL rev3.0 9.17.1.3 CXL Fixed Memory Window Structure (CFMWS)
>
> cxl cli will use this QTG ID to match with the _DSM retrieved QTG ID for a
> hot-plugged CXL memory device DPA memory range to make sure that the DPA range
> is under the right CFMWS window.
>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
Bikeshedding alert:
Why not just call it qtg? What does the _id add?
I don't really care either way...
LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
One (more) completely trivial comment inline.
Jonathan
> ---
> v4:
> - Change kernel version for documentation to v6.5
> v2:
> - Add explanation commit header (Jonathan)
> ---
> Documentation/ABI/testing/sysfs-bus-cxl | 9 +++++++++
> drivers/cxl/acpi.c | 3 +++
> drivers/cxl/core/port.c | 14 ++++++++++++++
> drivers/cxl/cxl.h | 3 +++
> 4 files changed, 29 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index 3acf2f17a73f..bd2b59784979 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -309,6 +309,15 @@ Description:
> (WO) Write a string in the form 'regionZ' to delete that region,
> provided it is currently idle / not bound to a driver.
>
> +What: /sys/bus/cxl/devices/decoderX.Y/qtg_id
> +Date: Jan, 2023
> +KernelVersion: v6.5
> +Contact: linux-cxl@vger.kernel.org
> +Description:
> + (RO) Shows the QoS Throttling Group ID. The QTG ID for a root
> + decoder comes from the CFMWS structure of the CEDT. A value of
> + -1 indicates that no QTG ID was retrieved. The QTG ID is used as
> + guidance to match against the QTG ID of a hot-plugged device.
>
> What: /sys/bus/cxl/devices/regionZ/uuid
> Date: May, 2022
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index 7e1765b09e04..abc24137c291 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -289,6 +289,9 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
> }
> }
> }
> +
> + cxld->qtg_id = cfmws->qtg_id;
> +
> rc = cxl_decoder_add(cxld, target_map);
> err_xormap:
> if (rc)
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 4d1f9c5b5029..024d4178f557 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -276,6 +276,16 @@ static ssize_t interleave_ways_show(struct device *dev,
>
> static DEVICE_ATTR_RO(interleave_ways);
>
> +static ssize_t qtg_id_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct cxl_decoder *cxld = to_cxl_decoder(dev);
> +
> + return sysfs_emit(buf, "%d\n", cxld->qtg_id);
> +}
> +
No blank line here would be more consistent with local style (based on
a really quick look).
> +static DEVICE_ATTR_RO(qtg_id);
> +
> static struct attribute *cxl_decoder_base_attrs[] = {
> &dev_attr_start.attr,
> &dev_attr_size.attr,
> @@ -295,6 +305,7 @@ static struct attribute *cxl_decoder_root_attrs[] = {
> &dev_attr_cap_type2.attr,
> &dev_attr_cap_type3.attr,
> &dev_attr_target_list.attr,
> + &dev_attr_qtg_id.attr,
> SET_CXL_REGION_ATTR(create_pmem_region)
> SET_CXL_REGION_ATTR(create_ram_region)
> SET_CXL_REGION_ATTR(delete_region)
> @@ -1625,6 +1636,7 @@ struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
> }
>
> atomic_set(&cxlrd->region_id, rc);
> + cxld->qtg_id = CXL_QTG_ID_INVALID;
> return cxlrd;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_root_decoder_alloc, CXL);
> @@ -1662,6 +1674,7 @@ struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
>
> cxld = &cxlsd->cxld;
> cxld->dev.type = &cxl_decoder_switch_type;
> + cxld->qtg_id = CXL_QTG_ID_INVALID;
> return cxlsd;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_switch_decoder_alloc, CXL);
> @@ -1694,6 +1707,7 @@ struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)
> }
>
> cxld->dev.type = &cxl_decoder_endpoint_type;
> + cxld->qtg_id = CXL_QTG_ID_INVALID;
> return cxled;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_alloc, CXL);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 044a92d9813e..278ab6952332 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -300,6 +300,7 @@ enum cxl_decoder_type {
> */
> #define CXL_DECODER_MAX_INTERLEAVE 16
>
> +#define CXL_QTG_ID_INVALID -1
>
> /**
> * struct cxl_decoder - Common CXL HDM Decoder Attributes
> @@ -311,6 +312,7 @@ enum cxl_decoder_type {
> * @target_type: accelerator vs expander (type2 vs type3) selector
> * @region: currently assigned region for this decoder
> * @flags: memory type capabilities and locking
> + * @qtg_id: QoS Throttling Group ID
> * @commit: device/decoder-type specific callback to commit settings to hw
> * @reset: device/decoder-type specific callback to reset hw settings
> */
> @@ -323,6 +325,7 @@ struct cxl_decoder {
> enum cxl_decoder_type target_type;
> struct cxl_region *region;
> unsigned long flags;
> + int qtg_id;
> int (*commit)(struct cxl_decoder *cxld);
> int (*reset)(struct cxl_decoder *cxld);
> };
>
>
next prev parent reply other threads:[~2023-04-20 8:54 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 20:21 [PATCH v4 00/23] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-04-19 20:21 ` [PATCH v4 01/23] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-04-20 8:51 ` Jonathan Cameron [this message]
2023-04-20 20:53 ` Dave Jiang
2023-04-24 21:46 ` Dan Williams
2023-04-26 23:14 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 02/23] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-04-20 8:55 ` Jonathan Cameron
2023-04-24 22:01 ` Dan Williams
2023-04-26 23:24 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 03/23] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-04-20 9:25 ` Jonathan Cameron
2023-04-24 22:08 ` Dan Williams
2023-04-27 15:55 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 04/23] cxl: Add common helpers for cdat parsing Dave Jiang
2023-04-20 9:41 ` Jonathan Cameron
2023-04-20 21:05 ` Dave Jiang
2023-04-21 16:06 ` Jonathan Cameron
2023-04-21 16:12 ` Dave Jiang
2023-04-24 22:33 ` Dan Williams
2023-04-25 16:00 ` Dave Jiang
2023-04-27 0:09 ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 05/23] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-04-20 11:33 ` Jonathan Cameron
2023-04-20 11:35 ` Jonathan Cameron
2023-04-20 23:25 ` Dave Jiang
2023-04-24 22:38 ` Dan Williams
2023-04-26 3:44 ` Li, Ming
2023-04-26 18:27 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 06/23] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-04-20 11:40 ` Jonathan Cameron
2023-04-20 23:25 ` Dave Jiang
2023-04-24 22:46 ` Dan Williams
2023-04-24 22:59 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 07/23] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-04-20 11:50 ` Jonathan Cameron
2023-04-24 23:38 ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 08/23] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-04-20 12:00 ` Jonathan Cameron
2023-04-21 0:11 ` Dave Jiang
2023-04-21 16:07 ` Jonathan Cameron
2023-04-25 0:12 ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 09/23] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-04-20 12:06 ` Jonathan Cameron
2023-04-21 23:24 ` Dave Jiang
2023-04-25 0:18 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 10/23] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-04-20 12:15 ` Jonathan Cameron
2023-04-25 0:30 ` Dan Williams
2023-05-01 16:29 ` Dave Jiang
2023-04-19 20:22 ` [PATCH v4 11/23] cxl: Add helper function that calculates QoS values for switches Dave Jiang
2023-04-20 12:26 ` Jonathan Cameron
2023-04-24 17:09 ` Dave Jiang
2023-04-24 17:31 ` Dave Jiang
2023-04-24 21:59 ` Jonathan Cameron
2023-04-25 0:33 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 12/23] cxl: Add helper function that calculate QoS values for PCI path Dave Jiang
2023-04-20 12:32 ` Jonathan Cameron
2023-04-25 0:45 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 13/23] ACPI: NUMA: Create enum for memory_target hmem_attrs indexing Dave Jiang
2023-04-19 20:22 ` [PATCH v4 14/23] ACPI: NUMA: Add genport target allocation to the HMAT parsing Dave Jiang
2023-04-19 20:22 ` [PATCH v4 15/23] ACPI: NUMA: Add setting of generic port locality attributes Dave Jiang
2023-04-19 20:22 ` [PATCH v4 16/23] ACPI: NUMA: Add helper function to retrieve the performance attributes Dave Jiang
2023-04-19 20:22 ` [PATCH v4 17/23] cxl: Add helper function to retrieve generic port QoS Dave Jiang
2023-04-19 20:22 ` [PATCH v4 18/23] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-04-19 20:22 ` [PATCH v4 19/23] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-04-19 20:23 ` [PATCH v4 20/23] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-04-19 20:23 ` [PATCH v4 21/23] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-04-19 20:23 ` [PATCH v4 22/23] cxl: Export sysfs attributes for memory device QTG ID Dave Jiang
2023-04-19 20:23 ` [PATCH v4 23/23] cxl/mem: Add debugfs output for QTG related data Dave Jiang
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