From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
dan.j.williams@intel.com, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com,
rafael@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v4 04/23] cxl: Add common helpers for cdat parsing
Date: Thu, 20 Apr 2023 14:05:40 -0700 [thread overview]
Message-ID: <71fb1962-7029-119f-f12a-32849dff659a@intel.com> (raw)
In-Reply-To: <20230420104104.000065dd@Huawei.com>
On 4/20/23 2:41 AM, Jonathan Cameron wrote:
> On Wed, 19 Apr 2023 13:21:25 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
>> Add helper functions to parse the CDAT table and provide a callback to
>> parse the sub-table. Helpers are provided for DSMAS and DSLBIS sub-table
>> parsing. The code is patterned after the ACPI table parsing helpers.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>>
> A few minor things inline. More than possible you addressed them
> in earlier versions though.
>
> Jonathan
>
>> ---
>> v2:
>> - Use local headers to handle LE instead of ACPI header
>> - Reduce complexity of parser function. (Jonathan)
>> - Directly access header type. (Jonathan)
>> - Simplify header ptr math. (Jonathan)
>> - Move parsed counter to the correct location. (Jonathan)
>> - Add LE to host conversion for entry length
>> ---
>> drivers/cxl/core/Makefile | 1
>> drivers/cxl/core/cdat.c | 100 +++++++++++++++++++++++++++++++++++++++++++++
>> drivers/cxl/cxlpci.h | 29 +++++++++++++
>> 3 files changed, 130 insertions(+)
>> create mode 100644 drivers/cxl/core/cdat.c
>>
>> diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
>> index ca4ae31d8f57..867a8014b462 100644
>> --- a/drivers/cxl/core/Makefile
>> +++ b/drivers/cxl/core/Makefile
>> @@ -12,5 +12,6 @@ cxl_core-y += memdev.o
>> cxl_core-y += mbox.o
>> cxl_core-y += pci.o
>> cxl_core-y += hdm.o
>> +cxl_core-y += cdat.o
>> cxl_core-$(CONFIG_TRACING) += trace.o
>> cxl_core-$(CONFIG_CXL_REGION) += region.o
>> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
>> new file mode 100644
>> index 000000000000..210f4499bddb
>> --- /dev/null
>> +++ b/drivers/cxl/core/cdat.c
>> @@ -0,0 +1,100 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/* Copyright(c) 2023 Intel Corporation. All rights reserved. */
>> +#include "cxlpci.h"
>> +#include "cxl.h"
>> +
>> +static bool has_handler(struct cdat_subtable_proc *proc)
>
> Even though they are static, I'd add a cxl_ or cdat_ prefix
> to these to make it clear they are local.
Ok I'll change to cdat_*
>
>> +{
>> + return proc->handler;
>> +}
>> +
>> +static int call_handler(struct cdat_subtable_proc *proc,
>> + struct cdat_subtable_entry *ent)
>> +{
>> + if (has_handler(proc))
>
> Do we need to check this again? It's checked in the parse_entries code
> well before this point.
>
> Also, if moving to checking it once, then is it worth the
> little wrapper functions?
Ok I'll call it directly and remove the wrapper.
>
>
>> + return proc->handler(ent->hdr, proc->arg);
>> + return -EINVAL;
>> +}
>> +
>> +static bool cdat_is_subtable_match(struct cdat_subtable_entry *ent)
>> +{
>> + return ent->hdr->type == ent->type;
>> +}
>> +
>> +static int cdat_table_parse_entries(enum cdat_type type,
>> + struct cdat_header *table_header,
>> + struct cdat_subtable_proc *proc)
>> +{
>> + unsigned long table_end, entry_len;
>> + struct cdat_subtable_entry entry;
>> + int count = 0;
>> + int rc;
>> +
>> + if (!has_handler(proc))
>> + return -EINVAL;
>> +
>> + table_end = (unsigned long)table_header + table_header->length;
>> +
>> + if (type >= CDAT_TYPE_RESERVED)
>> + return -EINVAL;
>> +
>> + entry.type = type;
>> + entry.hdr = (struct cdat_entry_header *)(table_header + 1);
>> +
>> + while ((unsigned long)entry.hdr < table_end) {
>> + entry_len = le16_to_cpu(entry.hdr->length);
>> +
>> + if ((unsigned long)entry.hdr + entry_len > table_end)
>> + return -EINVAL;
>> +
>> + if (entry_len == 0)
>> + return -EINVAL;
>> +
>> + if (cdat_is_subtable_match(&entry)) {
>> + rc = call_handler(proc, &entry);
>> + if (rc)
>> + return rc;
>> + count++;
>> + }
>> +
>> + entry.hdr = (struct cdat_entry_header *)((unsigned long)entry.hdr + entry_len);
>> + }
>> +
>> + return count;
>> +}
>
> ...
>
>> +int cdat_table_parse_sslbis(struct cdat_header *table,
>> + cdat_tbl_entry_handler handler, void *arg)
>
> Feels like these ones should take a typed arg. Sure you'll loose
> that again to use the generic handling code, but at this level we can
> do it I think.
while DSMAS and DSLBIS takes a list_head, SSLBIS takes an xarray. I can
create a union.
>
>> +{
>> + struct cdat_subtable_proc proc = {
>> + .handler = handler,
>> + .arg = arg,
>> + };
>> +
>> + return cdat_table_parse_entries(CDAT_TYPE_SSLBIS, table, &proc);
>> +}
>
next prev parent reply other threads:[~2023-04-20 21:05 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 20:21 [PATCH v4 00/23] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-04-19 20:21 ` [PATCH v4 01/23] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-04-20 8:51 ` Jonathan Cameron
2023-04-20 20:53 ` Dave Jiang
2023-04-24 21:46 ` Dan Williams
2023-04-26 23:14 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 02/23] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-04-20 8:55 ` Jonathan Cameron
2023-04-24 22:01 ` Dan Williams
2023-04-26 23:24 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 03/23] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-04-20 9:25 ` Jonathan Cameron
2023-04-24 22:08 ` Dan Williams
2023-04-27 15:55 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 04/23] cxl: Add common helpers for cdat parsing Dave Jiang
2023-04-20 9:41 ` Jonathan Cameron
2023-04-20 21:05 ` Dave Jiang [this message]
2023-04-21 16:06 ` Jonathan Cameron
2023-04-21 16:12 ` Dave Jiang
2023-04-24 22:33 ` Dan Williams
2023-04-25 16:00 ` Dave Jiang
2023-04-27 0:09 ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 05/23] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-04-20 11:33 ` Jonathan Cameron
2023-04-20 11:35 ` Jonathan Cameron
2023-04-20 23:25 ` Dave Jiang
2023-04-24 22:38 ` Dan Williams
2023-04-26 3:44 ` Li, Ming
2023-04-26 18:27 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 06/23] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-04-20 11:40 ` Jonathan Cameron
2023-04-20 23:25 ` Dave Jiang
2023-04-24 22:46 ` Dan Williams
2023-04-24 22:59 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 07/23] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-04-20 11:50 ` Jonathan Cameron
2023-04-24 23:38 ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 08/23] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-04-20 12:00 ` Jonathan Cameron
2023-04-21 0:11 ` Dave Jiang
2023-04-21 16:07 ` Jonathan Cameron
2023-04-25 0:12 ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 09/23] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-04-20 12:06 ` Jonathan Cameron
2023-04-21 23:24 ` Dave Jiang
2023-04-25 0:18 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 10/23] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-04-20 12:15 ` Jonathan Cameron
2023-04-25 0:30 ` Dan Williams
2023-05-01 16:29 ` Dave Jiang
2023-04-19 20:22 ` [PATCH v4 11/23] cxl: Add helper function that calculates QoS values for switches Dave Jiang
2023-04-20 12:26 ` Jonathan Cameron
2023-04-24 17:09 ` Dave Jiang
2023-04-24 17:31 ` Dave Jiang
2023-04-24 21:59 ` Jonathan Cameron
2023-04-25 0:33 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 12/23] cxl: Add helper function that calculate QoS values for PCI path Dave Jiang
2023-04-20 12:32 ` Jonathan Cameron
2023-04-25 0:45 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 13/23] ACPI: NUMA: Create enum for memory_target hmem_attrs indexing Dave Jiang
2023-04-19 20:22 ` [PATCH v4 14/23] ACPI: NUMA: Add genport target allocation to the HMAT parsing Dave Jiang
2023-04-19 20:22 ` [PATCH v4 15/23] ACPI: NUMA: Add setting of generic port locality attributes Dave Jiang
2023-04-19 20:22 ` [PATCH v4 16/23] ACPI: NUMA: Add helper function to retrieve the performance attributes Dave Jiang
2023-04-19 20:22 ` [PATCH v4 17/23] cxl: Add helper function to retrieve generic port QoS Dave Jiang
2023-04-19 20:22 ` [PATCH v4 18/23] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-04-19 20:22 ` [PATCH v4 19/23] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-04-19 20:23 ` [PATCH v4 20/23] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-04-19 20:23 ` [PATCH v4 21/23] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-04-19 20:23 ` [PATCH v4 22/23] cxl: Export sysfs attributes for memory device QTG ID Dave Jiang
2023-04-19 20:23 ` [PATCH v4 23/23] cxl/mem: Add debugfs output for QTG related data Dave Jiang
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