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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
	Ira Weiny <ira.weiny@intel.com>, <dan.j.williams@intel.com>,
	<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
	<rafael@kernel.org>, <lukas@wunner.de>
Subject: Re: [PATCH v4 03/23] cxl: Add support for reading CXL switch CDAT table
Date: Thu, 20 Apr 2023 10:25:50 +0100	[thread overview]
Message-ID: <20230420102550.00000139@Huawei.com> (raw)
In-Reply-To: <168193567959.1178687.13133878561024203176.stgit@djiang5-mobl3>

On Wed, 19 Apr 2023 13:21:19 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Move read_cdat_data() from endpoint probe to general port probe to
> allow reading of CDAT data for CXL switches as well as CXL device.
> Add wrapper support for cxl_test to bypass the cdat reading.
> 
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

It might be worth a wrapper at somepoint for that dance
from port to the PCI device with the actual DOE etc.

Such a wrapp would provide somewhere to add a bit of
documentation on why the uport might be a platform device
(memX) or might be a PCI device thus explaining the two
different way it is handled.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> 
> ---
> v4:
> - Remove cxl_test wrapper. (Ira)
> ---
>  drivers/cxl/core/pci.c |   20 +++++++++++++++-----
>  drivers/cxl/port.c     |    6 +++---
>  2 files changed, 18 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 9c7e2f69d9ca..1c415b26e866 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -546,16 +546,26 @@ static unsigned char cdat_checksum(void *buf, size_t size)
>   */
>  void read_cdat_data(struct cxl_port *port)
>  {
> -	struct pci_doe_mb *cdat_doe;
> -	struct device *dev = &port->dev;
>  	struct device *uport = port->uport;
> -	struct cxl_memdev *cxlmd = to_cxl_memdev(uport);
> -	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> -	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
> +	struct device *dev = &port->dev;
> +	struct cxl_dev_state *cxlds;
> +	struct pci_doe_mb *cdat_doe;
> +	struct cxl_memdev *cxlmd;
> +	struct pci_dev *pdev;
>  	size_t cdat_length;
>  	void *cdat_table;
>  	int rc;
>  
> +	if (is_cxl_memdev(uport)) {
> +		cxlmd = to_cxl_memdev(uport);
> +		cxlds = cxlmd->cxlds;          
> +		pdev = to_pci_dev(cxlds->dev); 
> +	} else if (dev_is_pci(uport)) {
> +		pdev = to_pci_dev(uport);
> +	} else {
> +		return;
> +	}
> +
>  	cdat_doe = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL,
>  					CXL_DOE_PROTOCOL_TABLE_ACCESS);
>  	if (!cdat_doe) {
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 22a7ab2bae7c..615e0ef6b440 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -93,9 +93,6 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
>  	if (IS_ERR(cxlhdm))
>  		return PTR_ERR(cxlhdm);
>  
> -	/* Cache the data early to ensure is_visible() works */
> -	read_cdat_data(port);
> -
>  	get_device(&cxlmd->dev);
>  	rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd);
>  	if (rc)
> @@ -135,6 +132,9 @@ static int cxl_port_probe(struct device *dev)
>  {
>  	struct cxl_port *port = to_cxl_port(dev);
>  
> +	/* Cache the data early to ensure is_visible() works */
> +	read_cdat_data(port);
> +
>  	if (is_cxl_endpoint(port))
>  		return cxl_endpoint_port_probe(port);
>  	return cxl_switch_port_probe(port);
> 
> 


  reply	other threads:[~2023-04-20  9:25 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-19 20:21 [PATCH v4 00/23] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-04-19 20:21 ` [PATCH v4 01/23] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-04-20  8:51   ` Jonathan Cameron
2023-04-20 20:53     ` Dave Jiang
2023-04-24 21:46   ` Dan Williams
2023-04-26 23:14     ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 02/23] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-04-20  8:55   ` Jonathan Cameron
2023-04-24 22:01   ` Dan Williams
2023-04-26 23:24     ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 03/23] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-04-20  9:25   ` Jonathan Cameron [this message]
2023-04-24 22:08   ` Dan Williams
2023-04-27 15:55     ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 04/23] cxl: Add common helpers for cdat parsing Dave Jiang
2023-04-20  9:41   ` Jonathan Cameron
2023-04-20 21:05     ` Dave Jiang
2023-04-21 16:06       ` Jonathan Cameron
2023-04-21 16:12         ` Dave Jiang
2023-04-24 22:33   ` Dan Williams
2023-04-25 16:00     ` Dave Jiang
2023-04-27  0:09       ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 05/23] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-04-20 11:33   ` Jonathan Cameron
2023-04-20 11:35     ` Jonathan Cameron
2023-04-20 23:25       ` Dave Jiang
2023-04-24 22:38   ` Dan Williams
2023-04-26  3:44   ` Li, Ming
2023-04-26 18:27     ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 06/23] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-04-20 11:40   ` Jonathan Cameron
2023-04-20 23:25     ` Dave Jiang
2023-04-24 22:46   ` Dan Williams
2023-04-24 22:59     ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 07/23] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-04-20 11:50   ` Jonathan Cameron
2023-04-24 23:38   ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 08/23] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-04-20 12:00   ` Jonathan Cameron
2023-04-21  0:11     ` Dave Jiang
2023-04-21 16:07       ` Jonathan Cameron
2023-04-25  0:12   ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 09/23] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-04-20 12:06   ` Jonathan Cameron
2023-04-21 23:24     ` Dave Jiang
2023-04-25  0:18   ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 10/23] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-04-20 12:15   ` Jonathan Cameron
2023-04-25  0:30   ` Dan Williams
2023-05-01 16:29     ` Dave Jiang
2023-04-19 20:22 ` [PATCH v4 11/23] cxl: Add helper function that calculates QoS values for switches Dave Jiang
2023-04-20 12:26   ` Jonathan Cameron
2023-04-24 17:09     ` Dave Jiang
2023-04-24 17:31       ` Dave Jiang
2023-04-24 21:59         ` Jonathan Cameron
2023-04-25  0:33   ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 12/23] cxl: Add helper function that calculate QoS values for PCI path Dave Jiang
2023-04-20 12:32   ` Jonathan Cameron
2023-04-25  0:45   ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 13/23] ACPI: NUMA: Create enum for memory_target hmem_attrs indexing Dave Jiang
2023-04-19 20:22 ` [PATCH v4 14/23] ACPI: NUMA: Add genport target allocation to the HMAT parsing Dave Jiang
2023-04-19 20:22 ` [PATCH v4 15/23] ACPI: NUMA: Add setting of generic port locality attributes Dave Jiang
2023-04-19 20:22 ` [PATCH v4 16/23] ACPI: NUMA: Add helper function to retrieve the performance attributes Dave Jiang
2023-04-19 20:22 ` [PATCH v4 17/23] cxl: Add helper function to retrieve generic port QoS Dave Jiang
2023-04-19 20:22 ` [PATCH v4 18/23] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-04-19 20:22 ` [PATCH v4 19/23] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-04-19 20:23 ` [PATCH v4 20/23] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-04-19 20:23 ` [PATCH v4 21/23] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-04-19 20:23 ` [PATCH v4 22/23] cxl: Export sysfs attributes for memory device QTG ID Dave Jiang
2023-04-19 20:23 ` [PATCH v4 23/23] cxl/mem: Add debugfs output for QTG related data Dave Jiang

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