Re: [PATCH v2 11/12] cxl/port: Enumerate cxl link capabilities

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Fri, 16 Jun 2023 12:16:06 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> Dan Williams wrote:
> > Dan Williams wrote:  
> > > Per CXL 3.0 9.14 "Back-Invalidation Configuration", in order to enable
> > > an HDM-DB range (CXL.mem region with device initiated back-invalidation
> > > support), all ports in the path between the endpoint and the host bridge
> > > must be in 256-bit flit-mode.
> > > 
> > > Even for typical Type-3 class devices it is useful to enumerate link
> > > capabilities through the topology for debug purposes.
> > > 
> > > See CXL 3.0 Table-64 "256B Flit Mode vs. 68B Flit Mode Operation", for
> > > how to determine 64B vs 256B Flit mode operation.
> > > 
> > > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> > > ---
> > >  drivers/cxl/core/pci.c  |  113 +++++++++++++++++++++++++++++++++++++++++++++++
> > >  drivers/cxl/core/port.c |    6 ++
> > >  drivers/cxl/cxl.h       |    7 +++
> > >  drivers/cxl/cxlpci.h    |   24 +++++++++-
> > >  drivers/cxl/port.c      |    5 ++
> > >  5 files changed, 153 insertions(+), 2 deletions(-)  
> > 
> > Going back over this again I noticed that it fails to actually store the
> > "features" in the port object, and it fails to claim that the root CXL
> > device can support all the capabilities. Here are those fixups to fold
> > in:  
> 
> ...and now it occurs to me that this approach falls over for RCH
> topologies as the link status registers potentially move into the RCRB
> space. So I want to test this on an RCH topology before this moves
> forward. The cxl_test RCH topology does not suffice since it only
> emulates the topology, not the register behavior, and QEMU is VH only.

Indeed awkward to test. Other than that, LGTM but I'll wait for the update
for any tags.

Thanks,

Jonathan

p.s. still open to someone adding an RCH to QEMU if anyone wants to :)