From: Dave Jiang <dave.jiang@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, <linux-cxl@vger.kernel.org>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v2 07/12] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}
Date: Thu, 15 Jun 2023 14:31:25 -0700 [thread overview]
Message-ID: <f10eb10d-635b-4f76-5fa6-532fa268cc39@intel.com> (raw)
In-Reply-To: <168679261369.3436160.7042443847605280593.stgit@dwillia2-xfh.jf.intel.com>
On 6/14/23 18:30, Dan Williams wrote:
> In preparation for support for HDM-D and HDM-DB configuration
> (device-memory, and device-memory with back-invalidate). Rename the current
> type designators to use HOSTONLYMEM and DEVMEM as a suffix.
>
> HDM-DB can be supported by devices that are not accelerators, so DEVMEM is
> a more generic term for that case.
>
> Fixup one location where this type value was open coded.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/acpi.c | 2 +-
> drivers/cxl/core/hdm.c | 11 ++++++-----
> drivers/cxl/core/port.c | 6 +++---
> drivers/cxl/core/region.c | 2 +-
> drivers/cxl/cxl.h | 4 ++--
> tools/testing/cxl/test/cxl.c | 6 +++---
> 6 files changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index 7e1765b09e04..603e5df8aec0 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -258,7 +258,7 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
>
> cxld = &cxlrd->cxlsd.cxld;
> cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
> - cxld->target_type = CXL_DECODER_EXPANDER;
> + cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> cxld->hpa_range = (struct range) {
> .start = res->start,
> .end = res->end,
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 7889ff203a34..79170de13d89 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -570,7 +570,8 @@ static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl)
>
> static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl)
> {
> - u32p_replace_bits(ctrl, !!(cxld->target_type == 3),
> + u32p_replace_bits(ctrl,
> + !!(cxld->target_type == CXL_DECODER_HOSTONLYMEM),
> CXL_HDM_DECODER0_CTRL_TYPE);
> }
>
> @@ -764,7 +765,7 @@ static int cxl_setup_hdm_decoder_from_dvsec(
> if (!len)
> return -ENOENT;
>
> - cxld->target_type = CXL_DECODER_EXPANDER;
> + cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> cxld->commit = NULL;
> cxld->reset = NULL;
> cxld->hpa_range = info->dvsec_range[which];
> @@ -838,9 +839,9 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)
> cxld->flags |= CXL_DECODER_F_LOCK;
> if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl))
> - cxld->target_type = CXL_DECODER_EXPANDER;
> + cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> else
> - cxld->target_type = CXL_DECODER_ACCELERATOR;
> + cxld->target_type = CXL_DECODER_DEVMEM;
> if (cxld->id != port->commit_end + 1) {
> dev_warn(&port->dev,
> "decoder%d.%d: Committed out of order\n",
> @@ -861,7 +862,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> ctrl |= CXL_HDM_DECODER0_CTRL_TYPE;
> writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));
> }
> - cxld->target_type = CXL_DECODER_EXPANDER;
> + cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> }
> rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
> &cxld->interleave_ways);
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index e7c284c890bc..6d7811b26b5a 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -117,9 +117,9 @@ static ssize_t target_type_show(struct device *dev,
> struct cxl_decoder *cxld = to_cxl_decoder(dev);
>
> switch (cxld->target_type) {
> - case CXL_DECODER_ACCELERATOR:
> + case CXL_DECODER_DEVMEM:
> return sysfs_emit(buf, "accelerator\n");
> - case CXL_DECODER_EXPANDER:
> + case CXL_DECODER_HOSTONLYMEM:
> return sysfs_emit(buf, "expander\n");
> }
> return -ENXIO;
> @@ -1550,7 +1550,7 @@ static int cxl_decoder_init(struct cxl_port *port, struct cxl_decoder *cxld)
> /* Pre initialize an "empty" decoder */
> cxld->interleave_ways = 1;
> cxld->interleave_granularity = PAGE_SIZE;
> - cxld->target_type = CXL_DECODER_EXPANDER;
> + cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> cxld->hpa_range = (struct range) {
> .start = 0,
> .end = -1,
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index f822de44bee0..6a875f86901b 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -2103,7 +2103,7 @@ static struct cxl_region *__create_region(struct cxl_root_decoder *cxlrd,
> return ERR_PTR(-EBUSY);
> }
>
> - return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_EXPANDER);
> + return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_HOSTONLYMEM);
> }
>
> static ssize_t create_pmem_region_store(struct device *dev,
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index dfc94e76c7d6..ae0965ac8c5a 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -290,8 +290,8 @@ resource_size_t cxl_rcrb_to_component(struct device *dev,
> #define CXL_DECODER_F_MASK GENMASK(5, 0)
>
> enum cxl_decoder_type {
> - CXL_DECODER_ACCELERATOR = 2,
> - CXL_DECODER_EXPANDER = 3,
> + CXL_DECODER_DEVMEM = 2,
> + CXL_DECODER_HOSTONLYMEM = 3,
> };
>
> /*
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index bf00dc52fe96..5565164d6658 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -713,7 +713,7 @@ static void default_mock_decoder(struct cxl_decoder *cxld)
>
> cxld->interleave_ways = 1;
> cxld->interleave_granularity = 256;
> - cxld->target_type = CXL_DECODER_EXPANDER;
> + cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> cxld->commit = mock_decoder_commit;
> cxld->reset = mock_decoder_reset;
> }
> @@ -787,7 +787,7 @@ static void mock_init_hdm_decoder(struct cxl_decoder *cxld)
>
> cxld->interleave_ways = 2;
> eig_to_granularity(window->granularity, &cxld->interleave_granularity);
> - cxld->target_type = CXL_DECODER_EXPANDER;
> + cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> cxld->flags = CXL_DECODER_F_ENABLE;
> cxled->state = CXL_DECODER_STATE_AUTO;
> port->commit_end = cxld->id;
> @@ -820,7 +820,7 @@ static void mock_init_hdm_decoder(struct cxl_decoder *cxld)
> } else
> cxlsd->target[0] = dport;
> cxld = &cxlsd->cxld;
> - cxld->target_type = CXL_DECODER_EXPANDER;
> + cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> cxld->flags = CXL_DECODER_F_ENABLE;
> iter->commit_end = 0;
> /*
>
next prev parent reply other threads:[~2023-06-15 21:31 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 1:29 [PATCH v2 00/12] Device memory prep Dan Williams
2023-06-15 1:29 ` [PATCH v2 01/12] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output Dan Williams
2023-06-15 1:29 ` [PATCH v2 02/12] tools/testing/cxl: Remove unused @cxlds argument Dan Williams
2023-06-15 1:29 ` [PATCH v2 03/12] cxl: Fix kernel-doc warnings Dan Williams
2023-06-15 21:28 ` Dave Jiang
2023-06-22 13:50 ` Jonathan Cameron
2023-06-15 1:29 ` [PATCH v2 04/12] cxl: Remove leftover attribute documentation in 'struct cxl_dev_state' Dan Williams
2023-06-15 21:29 ` Dave Jiang
2023-06-22 13:50 ` Jonathan Cameron
2023-06-15 1:30 ` [PATCH v2 05/12] cxl/mbox: Move mailbox related driver state to its own data structure Dan Williams
2023-06-15 1:30 ` [PATCH v2 06/12] cxl/memdev: Make mailbox functionality optional Dan Williams
2023-06-15 21:30 ` Dave Jiang
2023-06-22 13:52 ` Jonathan Cameron
2023-06-15 1:30 ` [PATCH v2 07/12] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM} Dan Williams
2023-06-15 21:31 ` Dave Jiang [this message]
2023-06-15 1:30 ` [PATCH v2 08/12] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM Dan Williams
2023-06-15 21:32 ` Dave Jiang
2023-06-15 1:30 ` [PATCH v2 09/12] cxl/region: Manage decoder target_type at decoder-attach time Dan Williams
2023-06-15 1:30 ` [PATCH v2 10/12] cxl/pci: Unconditionally unmask 256B Flit errors Dan Williams
2023-06-15 21:34 ` Dave Jiang
2023-06-22 13:55 ` Jonathan Cameron
2023-06-15 1:30 ` [PATCH v2 11/12] cxl/port: Enumerate cxl link capabilities Dan Williams
2023-06-15 21:37 ` Dave Jiang
2023-06-16 0:07 ` Dan Williams
2023-06-16 19:16 ` Dan Williams
2023-06-22 14:04 ` Jonathan Cameron
2023-06-15 1:30 ` [PATCH v2 12/12] cxl/memdev: Formalize endpoint port linkage Dan Williams
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