RE: [PATCH v2 11/12] cxl/port: Enumerate cxl link capabilities

[Dan Williams <dan.j.williams@intel.com>]

Dan Williams wrote:
> Per CXL 3.0 9.14 "Back-Invalidation Configuration", in order to enable
> an HDM-DB range (CXL.mem region with device initiated back-invalidation
> support), all ports in the path between the endpoint and the host bridge
> must be in 256-bit flit-mode.
> 
> Even for typical Type-3 class devices it is useful to enumerate link
> capabilities through the topology for debug purposes.
> 
> See CXL 3.0 Table-64 "256B Flit Mode vs. 68B Flit Mode Operation", for
> how to determine 64B vs 256B Flit mode operation.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
>  drivers/cxl/core/pci.c  |  113 +++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/cxl/core/port.c |    6 ++
>  drivers/cxl/cxl.h       |    7 +++
>  drivers/cxl/cxlpci.h    |   24 +++++++++-
>  drivers/cxl/port.c      |    5 ++
>  5 files changed, 153 insertions(+), 2 deletions(-)

Going back over this again I noticed that it fails to actually store the
"features" in the port object, and it fails to claim that the root CXL
device can support all the capabilities. Here are those fixups to fold
in:

-- >8 --
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 7440f84be6c8..659da6cada6c 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -555,10 +555,8 @@ int cxl_probe_link(struct cxl_port *port)
 	dev = &pdev->dev;
 	dvsec = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
 					  CXL_DVSEC_FLEXBUS_PORT);
-	if (!dvsec) {
-		dev_err(dev, "Failed to enumerate port capabilities\n");
+	if (!dvsec)
 		return -ENXIO;
-	}
 
 	/*
 	 * Cache the link features for future determination of 256B Flit
@@ -617,7 +615,7 @@ int cxl_probe_link(struct cxl_port *port)
 	/* Enforce port features are plumbed through to the host bridge */
 	features &= parent_features;
 
-	dev_dbg(dev, "features:%s%s%s%s%s%s%s%s%s\n",
+	dev_dbg(&port->dev, "%s: features:%s%s%s%s%s%s%s%s%s\n", dev_name(dev),
 		features & CXL_DVSEC_FLEXBUS_CACHE_ENABLED ? " cache" : "",
 		features & CXL_DVSEC_FLEXBUS_IO_ENABLED ? " io" : "",
 		features & CXL_DVSEC_FLEXBUS_MEM_ENABLED ? " mem" : "",
@@ -628,6 +626,8 @@ int cxl_probe_link(struct cxl_port *port)
 		features & CXL_PORT_FEATURE_FLIT68 ? " flit68" : "",
 		features & CXL_PORT_FEATURE_FLIT256 ? " flit256" : "");
 
+	port->features = features;
+
 	return 0;
 }
 EXPORT_SYMBOL_NS_GPL(cxl_probe_link, CXL);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index bf8f25063914..05ec8c6e8a6d 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -670,7 +670,8 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
 	 * cxl_probe_link() will fix this up later in cxl_probe_link() for all
 	 * other ports.
 	 */
-	port->features = CXL_DVSEC_FLEXBUS_ENABLE_MASK;
+	port->features = CXL_DVSEC_FLEXBUS_ENABLE_MASK |
+			 CXL_PORT_FEATURE_FLIT68 | CXL_PORT_FEATURE_FLIT256;
 	port->component_reg_phys = component_reg_phys;
 	ida_init(&port->decoder_ida);
 	port->hdm_end = -1;
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 5ffe3c7d2f5e..a2641a3eecec 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -143,8 +143,10 @@ static int cxl_port_probe(struct device *dev)
 	int rc;
 
 	rc = cxl_probe_link(port);
-	if (rc)
+	if (rc) {
+		dev_err(dev, "Failed to enumerate port capabilities: %d\n", rc);
 		return rc;
+	}
 
 	if (is_cxl_endpoint(port))
 		return cxl_endpoint_port_probe(port);