Re: [PATCH 0/5] cxl/dcd: Add support for Dynamic Capacity Devices (DCD)

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Thu, 22 Jun 2023 16:07:36 +0100
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:

> On Thu, 15 Jun 2023 07:51:16 -0700
> Ira Weiny <ira.weiny@intel.com> wrote:
> 
> > ira.weiny@ wrote:  
> > > I'm submitting these on behalf of Navneet.  There was a round of
> > > internal discussion which left a few questions but we want to get the
> > > public discussion going.  A first public preview was posted by Dan.[1]    
> > 
> > Apologies for not being clear and marking these appropriately.  I
> > intended these to be RFC to get the discussion moving forward.  I somewhat
> > rushed the submission.  Depending on where the comments in this submission
> > go I'll try and make a better determination if the next submission is RFC
> > or can be a proper V1.  (Although b4 will mark them v2...  I'll have to
> > deal with that.)  
> 
> Make sure your SoB is added after Navneet to reflect that you are
> handling the posting to the mailing list even if you feel changes are insufficient
> to merit a Co-developed-by tag. (no idea who is doing what :)
> 
Ah. I see there are comments on no sign off. Hmm. If it's legally fine
and you post it as an RFC only I don't see a strong argument for not
keeping that chain intact.

Jonathan

> Jonathan
> 
> 
> > 
> > Ira
> >   
> > > 
> > > The series has been rebased on the type-2 work posted from Dan.[2]  As
> > > discussed in the community call, not all of that series is required for
> > > these patches.  This will get rebased on the subset of those patches he
> > > is targeting for 6.5.  The series was tested using Fan Ni's Qemu DCD
> > > series.[3]
> > > 
> > > [cover letter]
> > > 
> > > A Dynamic Capacity Device (DCD) (CXL 3.0 spec 9.13.3) is a CXL memory
> > > device that implements dynamic capacity.  Dynamic capacity feature
> > > allows memory capacity to change dynamically, without the need for
> > > resetting the device.
> > > 
> > > Provide initial patches to enable DCD on non interleaving regions.
> > > Details:
> > > 
> > > - Get the dynamic capacity region information from cxl device and add
> > >   the advertised DC memory to driver managed resources
> > > - Get the device dynamic capacity extent list from the device and
> > >   maintain it in the host and add the preallocated memory to the host
> > > - Dynamic capacity region support
> > > - DCD region provisioning via Dax
> > > - Dynamic capacity event records
> > >         a. Add capacity Events
> > > 	b. Release capacity events
> > > 	c. Add the memory to the host dc region
> > > 	d. Release the memory from the host dc region
> > > - Trace Dynamic Capacity events
> > > - Send add capacity response to device
> > > - Send release dynamic capacity to device
> > > 
> > > Cc: Navneet Singh <navneet.singh@intel.com>
> > > Cc: Fan Ni <fan.ni@samsung.com>
> > > Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > Cc: Ira Weiny <ira.weiny@intel.com>
> > > Cc: Dan Williams <dan.j.williams@intel.com>
> > > Cc: linux-cxl@vger.kernel.org
> > > 
> > > [1] https://lore.kernel.org/all/64326437c1496_934b2949f@dwillia2-mobl3.amr.corp.intel.com.notmuch/
> > > [2] https://lore.kernel.org/all/168592149709.1948938.8663425987110396027.stgit@dwillia2-xfh.jf.intel.com/
> > > [3] https://lore.kernel.org/all/6483946e8152f_f1132294a2@iweiny-mobl.notmuch/
> > > 
> > > ---
> > > Navneet Singh (5):
> > >       cxl/mem : Read Dynamic capacity configuration from the device
> > >       cxl/region: Add dynamic capacity cxl region support.
> > >       cxl/mem : Expose dynamic capacity configuration to userspace
> > >       cxl/mem: Add support to handle DCD add and release capacity events.
> > >       cxl/mem: Trace Dynamic capacity Event Record
> > > 
> > >  drivers/cxl/Kconfig       |  11 +
> > >  drivers/cxl/core/core.h   |   7 +
> > >  drivers/cxl/core/hdm.c    | 234 ++++++++++++++++++--
> > >  drivers/cxl/core/mbox.c   | 540 +++++++++++++++++++++++++++++++++++++++++++++-
> > >  drivers/cxl/core/memdev.c |  72 +++++++
> > >  drivers/cxl/core/port.c   |  18 ++
> > >  drivers/cxl/core/region.c | 337 ++++++++++++++++++++++++++++-
> > >  drivers/cxl/core/trace.h  |  68 +++++-
> > >  drivers/cxl/cxl.h         |  32 ++-
> > >  drivers/cxl/cxlmem.h      | 146 ++++++++++++-
> > >  drivers/cxl/pci.c         |  14 +-
> > >  drivers/dax/bus.c         |  11 +-
> > >  drivers/dax/bus.h         |   5 +-
> > >  drivers/dax/cxl.c         |   4 +
> > >  14 files changed, 1453 insertions(+), 46 deletions(-)
> > > ---
> > > base-commit: 034a16d0165be3e092d60685be7b1b05e6f3059b
> > > change-id: 20230604-dcd-type2-upstream-0cd15f6216fd
> > > 
> > > Best regards,
> > > -- 
> > > Ira Weiny <ira.weiny@intel.com>
> > >     
> > 
> >   
> 
>