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From: Terry Bowman <terry.bowman@amd.com>
To: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
	<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
	<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
	<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
	<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: [PATCH v10 01/15] cxl/port: Pre-initialize component register mappings
Date: Thu, 31 Aug 2023 10:20:17 -0500	[thread overview]
Message-ID: <20230831152031.184295-2-terry.bowman@amd.com> (raw)
In-Reply-To: <20230831152031.184295-1-terry.bowman@amd.com>

From: Robert Richter <rrichter@amd.com>

The component registers of a component may not exist and
cxl_setup_comp_regs() will fail for that reason. In another case,
Software may not use and set those registers up. cxl_setup_comp_regs()
is then called with a base address of CXL_RESOURCE_NONE. Both are
valid cases, but the function returns without initializing the
register map.

Now, a missing component register block is not necessarily a reason to
fail (feature is optional or its existence checked later). Change
cxl_setup_comp_regs() to also use components with the component
register block missing. Thus, always initialize struct
cxl_register_map with valid values, set @dev and make @resource
CXL_RESOURCE_NONE.

The change is in preparation of follow-on patches.

Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/cxl/core/port.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 724be8448eb4..6c06c36f8c7b 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -693,16 +693,18 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
 static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
 			       resource_size_t component_reg_phys)
 {
-	if (component_reg_phys == CXL_RESOURCE_NONE)
-		return 0;
-
 	*map = (struct cxl_register_map) {
 		.dev = dev,
-		.reg_type = CXL_REGLOC_RBI_COMPONENT,
+		.reg_type = CXL_REGLOC_RBI_EMPTY,
 		.resource = component_reg_phys,
-		.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
 	};
 
+	if (component_reg_phys == CXL_RESOURCE_NONE)
+		return 0;
+
+	map->reg_type = CXL_REGLOC_RBI_COMPONENT;
+	map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
+
 	return cxl_setup_regs(map);
 }
 
-- 
2.34.1


  reply	other threads:[~2023-08-31 15:21 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-31 15:20 [PATCH v10 00/15] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-08-31 15:20 ` Terry Bowman [this message]
2023-08-31 15:20 ` [PATCH v10 02/15] cxl/regs: Prepare for multiple users of register mappings Terry Bowman
2023-09-01  9:15   ` Jonathan Cameron
2023-09-02 13:54     ` Robert Richter
2023-08-31 15:20 ` [PATCH v10 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-08-31 15:20 ` [PATCH v10 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-08-31 18:34   ` Dan Williams
2023-09-15  0:15     ` Dan Williams
2023-09-15 21:53       ` Robert Richter
2023-09-15 22:54         ` Dan Williams
2023-08-31 15:20 ` [PATCH v10 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-08-31 15:20 ` [PATCH v10 06/15] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-08-31 15:20 ` [PATCH v10 07/15] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-08-31 18:51   ` Dan Williams
2023-09-05 16:55     ` Terry Bowman

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