From: Robert Richter <rrichter@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Terry Bowman <terry.bowman@amd.com>,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, bwidawsk@kernel.org,
dan.j.williams@intel.com, dave.jiang@intel.com,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
bhelgaas@google.com
Subject: Re: [PATCH v10 02/15] cxl/regs: Prepare for multiple users of register mappings
Date: Sat, 2 Sep 2023 15:54:58 +0200 [thread overview]
Message-ID: <ZPM+sp4LJy2EjByW@rric.localdomain> (raw)
In-Reply-To: <20230901101527.000031ba@Huawei.com>
On 01.09.23 10:15:27, Jonathan Cameron wrote:
> On Thu, 31 Aug 2023 10:20:18 -0500
> Terry Bowman <terry.bowman@amd.com> wrote:
>
> > From: Robert Richter <rrichter@amd.com>
> >
> > The function devm_cxl_iomap_block() is used to map register mappings
> > of CXL component or device registers. A @dev is used to unmap the IO
> > regions during device removal.
> >
> > Now, there are multiple devices using the register mappings. E.g. the
> > RAS cap of the Component Registers is used by cxl_pci, the HDM cap
> > used in cxl_mem. This could cause IO blocks not being freed and a
> > subsequent reinitialization to fail if the same device is used for
> > both.
> >
> > To prevent that, expand cxl_map_component_regs() to pass a @dev to be
> > used with devm to IO unmap. This allows to pass the device that
> > actually is creating and using the IO region.
> >
> > For symmetry also change the function i/f of cxl_map_device_regs().
> >
> > Signed-off-by: Robert Richter <rrichter@amd.com>
> > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> I was ambiguous in reply to previous, but my RB not valid here as it
> stands. Just replying so that doesn't get lost for v11!
Yes, sorry, I wrongly assumed it here. Will remove for v11.
Thanks,
-Robert
next prev parent reply other threads:[~2023-09-02 13:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-31 15:20 [PATCH v10 00/15] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-08-31 15:20 ` [PATCH v10 01/15] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-08-31 15:20 ` [PATCH v10 02/15] cxl/regs: Prepare for multiple users of " Terry Bowman
2023-09-01 9:15 ` Jonathan Cameron
2023-09-02 13:54 ` Robert Richter [this message]
2023-08-31 15:20 ` [PATCH v10 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-08-31 15:20 ` [PATCH v10 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-08-31 18:34 ` Dan Williams
2023-09-15 0:15 ` Dan Williams
2023-09-15 21:53 ` Robert Richter
2023-09-15 22:54 ` Dan Williams
2023-08-31 15:20 ` [PATCH v10 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-08-31 15:20 ` [PATCH v10 06/15] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-08-31 15:20 ` [PATCH v10 07/15] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-08-31 18:51 ` Dan Williams
2023-09-05 16:55 ` Terry Bowman
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