* [PATCH v4 1/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine
2026-08-28 15:12 [PATCH v4 0/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
@ 2026-08-28 15:13 ` Chen Pei
2026-08-28 15:13 ` [PATCH v4 2/6] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Chen Pei
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Chen Pei @ 2026-08-28 15:13 UTC (permalink / raw)
To: palmer, alistair.francis, mst, imammedo, sunilvl, jic23
Cc: pbonzini, liwei1518, daniel.barboza, zhiwei_liu, chao.liu,
anisinha, dave.jiang, alison.schofield, junjie.cao, guoren,
qemu-riscv, qemu-devel, linux-cxl
Enable CXL support on the RISC-V virt machine following the same
approach used by the ARM virt machine:
- Add PXB and ACPI_CXL Kconfig selections
- Add CXLState and PCIBus pointer to RISCVVirtState
- Register CXL machine properties via cxl_machine_init()
- Create CXL host register region above the PCIe high MMIO region
- Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at
machine_done time
- Map Fixed Memory Windows above the CXL host register region
- Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
hw/riscv/Kconfig | 2 ++
hw/riscv/virt-acpi-build.c | 20 ++++++++++++++++++++
hw/riscv/virt.c | 37 +++++++++++++++++++++++++++++++++++++
include/hw/riscv/virt.h | 3 +++
4 files changed, 62 insertions(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index de37c08cae..0ba3cd9e15 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -66,8 +66,10 @@ config RISCV_VIRT
select VIRTIO_MMIO
select FW_CFG_DMA
select PLATFORM_BUS
+ select PXB
select ACPI
select ACPI_PCI
+ select ACPI_CXL
config SHAKTI_C
bool
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 59c454f4f9..3188cdc5bf 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -29,12 +29,16 @@
#include "hw/acpi/aml-build.h"
#include "hw/acpi/pci.h"
#include "hw/acpi/utils.h"
+#include "hw/acpi/cxl.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/nvram/fw_cfg_acpi.h"
#include "hw/pci-host/gpex.h"
+#include "hw/pci/pci_bus.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/numa.h"
#include "hw/virtio/virtio-acpi.h"
+#include "hw/cxl/cxl.h"
+#include "hw/cxl/cxl_host.h"
#include "kvm/kvm_riscv.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
@@ -514,6 +518,17 @@ static void build_dsdt(GArray *table_data,
acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources * 2);
}
+ if (s->cxl_devices_state.is_enabled) {
+ Aml *cxl_dev = aml_device("CXLM");
+ aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017")));
+ Aml *method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(0x0B)));
+ aml_append(cxl_dev, method);
+ build_cxl_dsm_method(cxl_dev);
+
+ aml_append(scope, cxl_dev);
+ }
+
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
@@ -921,6 +936,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
s->oem_table_id);
}
+ if (s->cxl_devices_state.is_enabled) {
+ cxl_build_cedt(table_offsets, tables_blob, tables->linker,
+ s->oem_id, s->oem_table_id, &s->cxl_devices_state);
+ }
+
if (ms->numa_state->num_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, s);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 51bac47a91..e08c76af4d 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -55,6 +55,8 @@
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
+#include "hw/cxl/cxl.h"
+#include "hw/cxl/cxl_host.h"
#include "hw/acpi/aml-build.h"
#include "qapi/qapi-visit-common.h"
#include "hw/virtio/virtio-iommu.h"
@@ -1101,9 +1103,33 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
}
GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus;
+ s->pci_bus = PCI_HOST_BRIDGE(dev)->bus;
return dev;
}
+static void cxl_host_state_init(RISCVVirtState *s)
+{
+ MemoryRegion *sysmem = get_system_memory();
+ MemoryRegion *mr = &s->cxl_devices_state.host_mr;
+ hwaddr base;
+
+ if (!s->cxl_devices_state.is_enabled) {
+ return;
+ }
+
+ base = virt_high_pcie_memmap.base + virt_high_pcie_memmap.size;
+ base = ROUND_UP(base, 64 * KiB);
+
+ memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16);
+ memory_region_add_subregion(sysmem, base, mr);
+
+ /* Map the Fixed Memory Windows above the CXL host register region. */
+ base += memory_region_size(mr);
+ base = ROUND_UP(base, 256 * MiB);
+ cxl_fmws_set_memmap(base, UINT64_MAX);
+ cxl_fmws_update_mmio();
+}
+
static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base)
{
FWCfgState *fw_cfg;
@@ -1205,6 +1231,13 @@ static void virt_machine_done(Notifier *notifier, void *data)
machine_done);
MachineState *machine = MACHINE(s);
hwaddr start_addr = s->memmap[VIRT_DRAM].base;
+
+ cxl_hook_up_pxb_registers(s->pci_bus, &s->cxl_devices_state,
+ &error_fatal);
+
+ if (s->cxl_devices_state.is_enabled) {
+ cxl_fmws_link_targets(&error_fatal);
+ }
hwaddr firmware_end_addr;
vaddr kernel_start_addr;
const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
@@ -1451,6 +1484,8 @@ static void virt_machine_init(MachineState *machine)
ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
}
+ cxl_host_state_init(s);
+
/* register system main memory (actual RAM) */
memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base,
machine->ram);
@@ -1558,6 +1593,8 @@ static void virt_machine_instance_init(Object *obj)
s->acpi = ON_OFF_AUTO_AUTO;
s->iommu_sys = ON_OFF_AUTO_AUTO;
s->num_sources = VIRT_IRQCHIP_NUM_SOURCES;
+
+ cxl_machine_init(obj, &s->cxl_devices_state);
}
static char *virt_get_aia_guests(Object *obj, Error **errp)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 36a2def410..4cf930ab9f 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,6 +24,7 @@
#include "hw/core/sysbus.h"
#include "hw/block/flash.h"
#include "hw/intc/riscv_imsic.h"
+#include "hw/cxl/cxl.h"
#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
@@ -65,6 +66,8 @@ struct RISCVVirtState {
OnOffAuto iommu_sys;
uint16_t pci_iommu_bdf;
uint16_t num_sources;
+ CXLState cxl_devices_state;
+ PCIBus *pci_bus;
};
enum {
--
2.50.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 2/6] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency
2026-08-28 15:12 [PATCH v4 0/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
2026-08-28 15:13 ` [PATCH v4 1/6] " Chen Pei
@ 2026-08-28 15:13 ` Chen Pei
2026-08-28 15:13 ` [PATCH v4 3/6] hw/riscv/virt: Advertise the CXL host bridge to firmware via extra-pci-roots Chen Pei
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Chen Pei @ 2026-08-28 15:13 UTC (permalink / raw)
To: palmer, alistair.francis, mst, imammedo, sunilvl, jic23
Cc: pbonzini, liwei1518, daniel.barboza, zhiwei_liu, chao.liu,
anisinha, dave.jiang, alison.schofield, junjie.cao, guoren,
qemu-riscv, qemu-devel, linux-cxl, Sunil V L
On RISC-V QEMU virt platform with CXL enabled, the probe ordering
of acpi_pci_root (ACPI0016) and cxl_acpi (ACPI0017) is not
guaranteed. If cxl_acpi probes before acpi_pci_root has attached
the CXL host bridges, the CXL port topology will be incomplete
because to_cxl_host_bridge() silently skips devices whose PCI root
is not yet ready.
Add a _DEP object to the ACPI0017 device in the DSDT, declaring
its dependency on the ACPI0016 CXL host bridge devices. This tells
the OS to defer ACPI0017 enumeration until all ACPI0016 devices
have been attached by acpi_pci_root.
This pairs with kernel commit 3a59c3b772e5 ("ACPI: PCI: Clear _DEP
dependencies after PCI root bridge attach"), which calls
acpi_dev_clear_dependencies() in acpi_pci_root_add().
Note on kernel compatibility: this is a "new QEMU feature requires a
sufficiently new kernel" situation. Kernels that process _DEP but
lack the acpi_dev_clear_dependencies() call will leave the CXLM device
deferred, so CXL memory is unusable there; kernels old enough to ignore
_DEP entirely behave exactly as before this change. In neither case is
existing (non-CXL) PCIe affected.
The resulting DSDT fragment (iasl -d output) for a single CXL host
bridge at bus 0x0C looks like:
Device (CXLM)
{
Name (_HID, "ACPI0017")
Name (_DEP, Package (0x01)
{
\_SB.PC0C
})
Method (_STA, 0, NotSerialized)
{
Return (0x0B)
}
...
}
Reviewed-by: Sunil V L <sunilvl@oss.qualcomm.com>
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 3188cdc5bf..56292f04a7 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -521,6 +521,38 @@ static void build_dsdt(GArray *table_data,
if (s->cxl_devices_state.is_enabled) {
Aml *cxl_dev = aml_device("CXLM");
aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017")));
+
+ /*
+ * Declare a _DEP on every ACPI0016 CXL host bridge so the OS
+ * defers ACPI0017 enumeration until acpi_pci_root has attached
+ * the CXL host bridges. Without this, cxl_acpi may probe before
+ * to_cxl_host_bridge() can resolve the PCI root and the CXL
+ * port topology comes up empty.
+ */
+ if (s->pci_bus) {
+ PCIBus *bus;
+ uint32_t num_cxl_hbs = 0;
+
+ QLIST_FOREACH(bus, &s->pci_bus->child, sibling) {
+ if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) {
+ num_cxl_hbs++;
+ }
+ }
+
+ if (num_cxl_hbs > 0) {
+ Aml *dep_pkg = aml_package(num_cxl_hbs);
+
+ QLIST_FOREACH(bus, &s->pci_bus->child, sibling) {
+ if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) {
+ aml_append(dep_pkg,
+ aml_name("\\_SB.PC%.02X",
+ pci_bus_num(bus)));
+ }
+ }
+ aml_append(cxl_dev, aml_name_decl("_DEP", dep_pkg));
+ }
+ }
+
Aml *method = aml_method("_STA", 0, AML_NOTSERIALIZED);
aml_append(method, aml_return(aml_int(0x0B)));
aml_append(cxl_dev, method);
--
2.50.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 3/6] hw/riscv/virt: Advertise the CXL host bridge to firmware via extra-pci-roots
2026-08-28 15:12 [PATCH v4 0/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
2026-08-28 15:13 ` [PATCH v4 1/6] " Chen Pei
2026-08-28 15:13 ` [PATCH v4 2/6] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Chen Pei
@ 2026-08-28 15:13 ` Chen Pei
2026-08-28 15:13 ` [PATCH v4 4/6] tests/qtest: Prepare golden files for the RISC-V CXL ACPI test Chen Pei
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Chen Pei @ 2026-08-28 15:13 UTC (permalink / raw)
To: palmer, alistair.francis, mst, imammedo, sunilvl, jic23
Cc: pbonzini, liwei1518, daniel.barboza, zhiwei_liu, chao.liu,
anisinha, dave.jiang, alison.schofield, junjie.cao, guoren,
qemu-riscv, qemu-devel, linux-cxl
The pxb-cxl expander bridge presents as a class 0x0600 host bridge with
a type-0 header, so EDK2's PciBusDxe never recurses into it and never
assigns the CXL root port a memory window or bus numbers. As a result
build_crs() produces an empty _CRS for the ACPI0016 host bridge and the
CXL devices behind it are not enumerated by the OS.
Advertise the pxb-cxl expander root buses to firmware via the
etc/extra-pci-roots fw_cfg file, the same way arm/virt and x86 do, by
calling pci_bus_add_fw_cfg_extra_pci_roots() from virt_machine_done().
EDK2's PciBusDxe then enumerates behind the CXL host bridge and assigns
the root-port window and bus numbers. The ACPI tables are rebuilt when
the guest reads them (after that firmware enumeration), so build_crs()
then emits a correct _CRS for the ACPI0016 host bridge.
This approach also scales to multiple pxb-cxl host bridges (each gets
its own window from the shared aperture) and lets firmware size the
window to what is actually behind the bridge, rather than reserving a
fixed carve-out.
Verified by booting an RVA22 guest: the CXL root port and Type3 device
enumerate, and 'cxl enable-memdev' / 'cxl create-region' /
'daxctl online-memory' bring the CXL memory online as system RAM.
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
v4:
- Replaces the v3 QEMU-side firmware simulation with
pci_bus_add_fw_cfg_extra_pci_roots(), advertising the pxb-cxl
expander root buses to firmware via etc/extra-pci-roots. EDK2 then
enumerates behind the CXL host bridge and assigns the root-port
window and bus numbers, and build_crs() emits a correct _CRS. This
scales to multiple pxb-cxl and lets firmware size the window.
hw/riscv/virt.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e08c76af4d..67f512cde1 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1237,6 +1237,14 @@ static void virt_machine_done(Notifier *notifier, void *data)
if (s->cxl_devices_state.is_enabled) {
cxl_fmws_link_targets(&error_fatal);
+
+ /*
+ * Let firmware enumerate the pxb-cxl root buses and assign bus
+ * numbers and windows; build_crs() builds the ACPI0016 _CRS from
+ * the resulting state when the guest reads the ACPI tables.
+ */
+ pci_bus_add_fw_cfg_extra_pci_roots(s->fw_cfg, s->pci_bus,
+ &error_abort);
}
hwaddr firmware_end_addr;
vaddr kernel_start_addr;
--
2.50.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 4/6] tests/qtest: Prepare golden files for the RISC-V CXL ACPI test
2026-08-28 15:12 [PATCH v4 0/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
` (2 preceding siblings ...)
2026-08-28 15:13 ` [PATCH v4 3/6] hw/riscv/virt: Advertise the CXL host bridge to firmware via extra-pci-roots Chen Pei
@ 2026-08-28 15:13 ` Chen Pei
2026-08-28 15:13 ` [PATCH v4 5/6] tests/qtest: Add RISC-V ACPI bios tables test for CXL Chen Pei
2026-08-28 15:13 ` [PATCH v4 6/6] tests/qtest: Update RISC-V CXL ACPI golden master binaries Chen Pei
5 siblings, 0 replies; 7+ messages in thread
From: Chen Pei @ 2026-08-28 15:13 UTC (permalink / raw)
To: palmer, alistair.francis, mst, imammedo, sunilvl, jic23
Cc: pbonzini, liwei1518, daniel.barboza, zhiwei_liu, chao.liu,
anisinha, dave.jiang, alison.schofield, junjie.cao, guoren,
qemu-riscv, qemu-devel, linux-cxl
Add empty DSDT.cxl and CEDT.cxl golden files and list them in
bios-tables-test-allowed-diff.h, in preparation for the RISC-V CXL
bios-tables test added in the following patch. The populated golden
master binaries are committed separately in a final patch, following
the bios-tables-test update process.
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
v4:
- Split the CXL bios-tables test into the staged flow documented in
bios-tables-test.c: empty golden files + allowed-diff.h, then the test
code, then the populated golden master binaries with an emptied
allowed-diff.h in a final patch (matching how the riscv64 goldens were
originally added upstream).
tests/data/acpi/riscv64/virt/CEDT.cxl | 0
tests/data/acpi/riscv64/virt/DSDT.cxl | 0
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
3 files changed, 2 insertions(+)
create mode 100644 tests/data/acpi/riscv64/virt/CEDT.cxl
create mode 100644 tests/data/acpi/riscv64/virt/DSDT.cxl
diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv64/virt/CEDT.cxl
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/riscv64/virt/DSDT.cxl b/tests/data/acpi/riscv64/virt/DSDT.cxl
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..c05fb697a5 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,3 @@
/* List of comma-separated changed AML files to ignore */
+"riscv64/virt/DSDT.cxl",
+"riscv64/virt/CEDT.cxl",
--
2.50.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 5/6] tests/qtest: Add RISC-V ACPI bios tables test for CXL
2026-08-28 15:12 [PATCH v4 0/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
` (3 preceding siblings ...)
2026-08-28 15:13 ` [PATCH v4 4/6] tests/qtest: Prepare golden files for the RISC-V CXL ACPI test Chen Pei
@ 2026-08-28 15:13 ` Chen Pei
2026-08-28 15:13 ` [PATCH v4 6/6] tests/qtest: Update RISC-V CXL ACPI golden master binaries Chen Pei
5 siblings, 0 replies; 7+ messages in thread
From: Chen Pei @ 2026-08-28 15:13 UTC (permalink / raw)
To: palmer, alistair.francis, mst, imammedo, sunilvl, jic23
Cc: pbonzini, liwei1518, daniel.barboza, zhiwei_liu, chao.liu,
anisinha, dave.jiang, alison.schofield, junjie.cao, guoren,
qemu-riscv, qemu-devel, linux-cxl
Add test_acpi_riscv64_virt_tcg_cxl() to verify that enabling CXL on
the RISC-V virt machine produces correct ACPI tables, including the
ACPI0017 CXLM device with _DEP in the DSDT and the CEDT table.
The test boots with cxl=on, one pxb-cxl bus (bus_nr=12), a CXL root
port, a cxl-type3 device and a fixed memory window, mirroring the
existing x86 q35 CXL test pattern.
Since pxb-cxl is a root bus, using -cdrom causes QEMU to auto-plug the
cdrom drive into pxb-cxl, triggering "Only PCI/PCIe bridges can be
plugged into pxb-cxl". The ISO is instead attached explicitly via a
virtio-scsi-pci controller on pcie.0, following the same approach as
test_acpi_aarch64_virt_tcg_pxb().
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 5cc526510a..d2b18d8ecb 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2214,6 +2214,56 @@ static void test_acpi_riscv64_virt_tcg(void)
free_test_data(&data);
}
+#ifdef CONFIG_POSIX
+static void test_acpi_riscv64_virt_tcg_cxl(void)
+{
+ gchar *tmp_path = g_dir_make_tmp("qemu-test-cxl.XXXXXX", NULL);
+ gchar *params;
+
+ test_data data = {
+ .machine = "virt",
+ .arch = "riscv64",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-riscv-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd",
+ .ram_start = 0x80000000ULL,
+ .scan_len = 128ULL * MiB,
+ .variant = ".cxl",
+ };
+
+ /*
+ * While using -cdrom, the cdrom would auto-plug into pxb-cxl because
+ * its bus is also a root bus, triggering "Only PCI/PCIe bridges can be
+ * plugged into pxb-cxl". Attach the ISO explicitly to a scsi controller
+ * on pcie.0 instead, following the same pattern as
+ * test_acpi_aarch64_virt_tcg_pxb().
+ */
+ params = g_strdup_printf("-cpu rva22s64"
+ " -machine cxl=on"
+ " -device pcie-root-port,chassis=1,id=pci.1,bus=pcie.0"
+ " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
+ " -drive file=tests/data/uefi-boot-images/"
+ "bios-tables-test.riscv64.iso.qcow2,"
+ "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
+ " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
+ "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
+ " -object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M"
+ " -object memory-backend-file,id=lsa1,mem-path=%s,size=256M"
+ " -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1"
+ " -device cxl-rp,port=0,bus=cxl.1,id=rp1,chassis=0,slot=2"
+ " -device cxl-type3,bus=rp1,persistent-memdev=cxl-mem1,lsa=lsa1"
+ " -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,"
+ "cxl-fmw.0.interleave-granularity=8k",
+ tmp_path, tmp_path);
+ test_acpi_one(params, &data);
+
+ g_free(params);
+ g_assert(g_rmdir(tmp_path) == 0);
+ g_free(tmp_path);
+ free_test_data(&data);
+}
+#endif /* CONFIG_POSIX */
+
static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
@@ -2963,6 +3013,10 @@ int main(int argc, char *argv[])
test_acpi_riscv64_virt_tcg_numamem);
qtest_add_func("acpi/virt/acpispcr",
test_acpi_riscv64_virt_tcg_acpi_spcr);
+#ifdef CONFIG_POSIX
+ qtest_add_func("acpi/virt/cxl",
+ test_acpi_riscv64_virt_tcg_cxl);
+#endif
}
} else if (strcmp(arch, "loongarch64") == 0) {
if (has_tcg && qtest_has_machine("virt")) {
--
2.50.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 6/6] tests/qtest: Update RISC-V CXL ACPI golden master binaries
2026-08-28 15:12 [PATCH v4 0/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
` (4 preceding siblings ...)
2026-08-28 15:13 ` [PATCH v4 5/6] tests/qtest: Add RISC-V ACPI bios tables test for CXL Chen Pei
@ 2026-08-28 15:13 ` Chen Pei
5 siblings, 0 replies; 7+ messages in thread
From: Chen Pei @ 2026-08-28 15:13 UTC (permalink / raw)
To: palmer, alistair.francis, mst, imammedo, sunilvl, jic23
Cc: pbonzini, liwei1518, daniel.barboza, zhiwei_liu, chao.liu,
anisinha, dave.jiang, alison.schofield, junjie.cao, guoren,
qemu-riscv, qemu-devel, linux-cxl
Populate the DSDT.cxl and CEDT.cxl golden master binaries for the
RISC-V CXL bios-tables test and empty
bios-tables-test-allowed-diff.h, following the bios-tables-test update
process.
The expected AML added by this series is:
DSDT.cxl:
Device (PC0C) // ACPI0016 CXL host bridge (pxb-cxl, bus 0x0C)
Name (_CRS, ResourceTemplate () {
DWordMemory (... 0x40400000 .. 0x405FFFFF ...) // 32-bit MMIO
QWordMemory (... 0x400100000 .. 0x40020FFFF ...) // 64-bit MMIO
WordBusNumber (... 0x000C .. 0x000D ...)
})
Method (_OSC, ...) // PCI host bridge + CXL UUIDs
Device (CXLM) // ACPI0017 CXL memory controller
Name (_HID, "ACPI0017")
Name (_DEP, Package () { \_SB.PC0C })
Method (_STA, ...) / Method (_DSM, ...)
CEDT.cxl:
CHBS : CXL Host Bridge Structure, Register base 0x800000000
CFMWS: CXL Fixed Memory Window, base 0x810000000, size 4G
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
tests/data/acpi/riscv64/virt/CEDT.cxl | Bin 0 -> 108 bytes
tests/data/acpi/riscv64/virt/DSDT.cxl | Bin 0 -> 6331 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
3 files changed, 2 deletions(-)
diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv64/virt/CEDT.cxl
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..81d746dfb09ccb147e26bb64060404ca3191d097 100644
GIT binary patch
literal 108
zc-nJzbqUE~U|?VjaPoKd2v%^42yj*a0!E-1hz+6{7!(+IKx!BefCEf2LP-snumA^?
O0aMEg#QH!C(hmS*@&^F`
literal 0
Hc-jL100001
diff --git a/tests/data/acpi/riscv64/virt/DSDT.cxl b/tests/data/acpi/riscv64/virt/DSDT.cxl
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c42c37a6a25998a70c42098b500a5e7163ae1513 100644
GIT binary patch
literal 6331
zc-pO*%WoS+9LHzv^&{)GV>{0K-B#j&ioTAUrk5(V*J*1MC&rsTL@L=LO4T-~q`X8y
zh^mJ|BZO#!dg0=VsQd$*pa>+maI1t62qZZ5!VwM#3CYat+RlE{t<*zYX?DgtzwgXv
zyRkpnl<d;VS3^Ps9u=3ZQ}$HxT-BPAFHH!c`s$dxc}qKAw~O`F8>e&&K(v0UT#6U0
zYFQ5EM6`aoT#{|2u#$SlI5c!f6ROPn+B;soaqPrd>x3Kh!b0V=44RP<_DaEsMeCMT
z&}3V)Qz;{HvqzODlX92hnyj2FTb(V`Z0n4y%yzeM(k_ZUg~Ak~;S^dCYq`Rexo)MZ
z88HUiHA&Up3JXm$oK>Usl3hyA1X6uQGV@F8*DtSpSlPP$;L~rO|4d7dYU!aseC_2|
z);11bcy;~i8|zoruE}Nd$K;{~{Y<U1-NmKavRrg_chN3qXX&K#&s|z;13M8}zX;7Q
zV#*T{Xh#%P#Ef5r5%9}^CnM<1$oXaj{W9{N4BeY?#5Y6t%cy!XLf(v7-;9u7M#Ga4
z_GTRQ%?SHtY<e;x-i$fljEG;xbx%gLol({oVYTm$>QYtqPjqjNs;o^IF=zf%`!2K|
zdoL5N+cjHjM`eAYG>)3~iJIo9=T+2<Pn5b@yjcf)vJUuU<@~aOoORGA>mX+>d|b6)
zc|U!!M^#0+lr{rq;h_;#jm#|;mkiTg#Z(_EwbZaNuqoaWFUg;dl2{jSic4Zm9!2+u
zuv%N`TYSy9o{s6UR!gY=7UA|abzMc;RDC0$u1seTRA?d{*G)M~2zOq4q`4Cl?#QXj
z?GA%(zB4!ARL*oqnrCXjt;Fsy=vgJ`ROY%P%`-LVR%UmHLC-3>5S|_ALi0@3MTfF8
z^m2xXGen#r<_s}sm^j148D`Efb4G|WLYxuij4)@EIHSZFWzHyb_7G<earQ804|5vC
zX%MHuoCb5oh%-i<G3Jahr%9Y9ahl9&GH0AP<HQ+f&Ny=>h%-T)3Fb^NXD@N~5@#=S
z_A+OZIFrPgWX>dWrie2|oGIo^F=v`M)5Mu(&NOrO5oaH9_AzH4b7qJ$L!24r%rIv^
zarP5uKXdjo=KygI5a$4M4lw5+aSjsaAaf2f=MZrY5$6zd4l(C2aSjvbFmnzw=Lm6*
z5a$SUjxgsaagGw_D07Z7=NNI05$70ljxpyragGz`ICG9O=LB(15a$GQPB7;raZVEF
zBy&!7INdMqrI7LB`|@@$+rppEw_5eQ+n*9!&+eWPj%6z^Y_+DG<L)cvv>(Jpz;ygw
zenyFak^}p6wJM_4N^Q~UTTb5+nZ-nX*|zkp4PlkeW}8dq?d^+7)mJOO<^Gu*%ilfw
zdg0sSKVNX)js5i3#Y^9BRlYv{$w+ek$N#oA3|-dE$YWF<bDOGZywfly8_ndM?MvFb
zD%ClcZT8*Sc22wRB~`2D�|Ag=%-34b^Lw^d~N8$_Yp0Q3cGZx+985b!HWkN}ttK
zv$Jt8;jX3jnBCcMO%MAgjo3eF#6C(R_DLF-?pCd`=V}#j%yq{0Nc{?EFPs#PHFmF~
za>hwxtST%~mYz5ze<ONobA-nn;WbBi%@JgdAaewpBiI~4<_I!JusMRw5oC@aa|D|s
z*c?IT2r@^oIfBg*WR4(n1e+t+96{y?GDomEg3S?Rjv#Xcn<Lm9LFNcDN3c19%@Jgd
zAaewpBiI~4<_I!JusMRw5oC@aa|D|s*c?IT2r@^oIfBg*WR4(n1e+t+96{y?GDomE
zg3S?Rjv#Xcn<Lm9LFNcDN3c19%@JgdAaewpBiI~4<_I!JusMRw5oC@aa|D|s*c?IT
z2r@^oIfBg*WR4(n1e+t+96{y?GDomEg3S?Rjv#Xcn<Lm9LFNcDN3c19%@JgdAaewp
zBiI~4<_I!JusMRw5oC@aa|D|s*c?IT2r@^oIfBg*WR4(n1e+t+96{y?GDomEg3S?R
zjv#Xcn<Lm9<tiDoZWRk+N4Xx{ukyTUJm~135HUvry;>=xR?fGzGEZk3@=WVJx8IzX
zXEZa|(MtK{tX@I&IC`&&infaO?orXC)9#%;-Jb1y!FXPOwA_cKnZ*bTX~^G4pJ<*F
zPidZxXWlbO5HpACCA*?Gr`<Il&i(Mno_)J=d+^W7@OM_F*|U9F?4*L4+pONG=(Po#
zbh2afIRlSfC%9L#HNWSHzH_0RN19>l++u|u(y2cYloqOKQ#=2h`a6PpikIn85BtTA
v5zEY}{hCd<`@R3~`rp5Qel>sp@)u@o`J-BQzgjb~eOcQ{M*~_~m$LIeRS7jr
literal 0
Hc-jL100001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index c05fb697a5..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,3 +1 @@
/* List of comma-separated changed AML files to ignore */
-"riscv64/virt/DSDT.cxl",
-"riscv64/virt/CEDT.cxl",
--
2.50.1
^ permalink raw reply related [flat|nested] 7+ messages in thread