[PATCH 05/15] cxl/port: Split endpoint port probe on device type

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

CXL.cache devices (struct cxl_cachedev) don't support or need all of the
set up done by endpoint port probe for CXL.mem devices (struct
cxl_memdev). Split endpoint port probe on device type and refactor dport
RAS set up into a common routine. The CXL.cache endpoint probe function
will be used when cxl_cachedevs are added to the port heirarchy in a
later commit.

No functional change intended for cxl_memdev path.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/cache.c         |  4 +++
 drivers/cxl/core/cachedev.c | 11 ++++++
 drivers/cxl/core/port.c     |  6 ++++
 drivers/cxl/cxl.h           |  1 +
 drivers/cxl/cxlcache.h      |  2 ++
 drivers/cxl/port.c          | 69 ++++++++++++++++++++++++++-----------
 6 files changed, 73 insertions(+), 20 deletions(-)

diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c
index 1815ae3a37d5..2ab783f7c365 100644
--- a/drivers/cxl/cache.c
+++ b/drivers/cxl/cache.c
@@ -33,6 +33,10 @@ static int cxl_cache_probe(struct device *dev)
 	/* Disable CXL.cache until we can validate the device configuration */
 	cxl_clear_cache_enable(cxlds);
 
+	/* See comment in cxl_mem_probe() */
+	if (work_pending(&cxlcd->detach_work))
+		return -EBUSY;
+
 	rc = cxl_accel_read_cache_info(cxlds);
 	if (rc)
 		return rc;
diff --git a/drivers/cxl/core/cachedev.c b/drivers/cxl/core/cachedev.c
index 25a24c3bd817..2bd69133c631 100644
--- a/drivers/cxl/core/cachedev.c
+++ b/drivers/cxl/core/cachedev.c
@@ -43,6 +43,16 @@ bool is_cxl_cachedev(const struct device *dev)
 }
 EXPORT_SYMBOL_NS_GPL(is_cxl_cachedev, "CXL");
 
+static void detach_cachedev(struct work_struct *work)
+{
+	struct cxl_cachedev *cxlcd;
+
+	cxlcd = container_of(work, typeof(*cxlcd), detach_work);
+
+	device_release_driver(&cxlcd->dev);
+	put_device(&cxlcd->dev);
+}
+
 static struct lock_class_key cxl_cachedev_key;
 
 static struct cxl_cachedev *cxl_cachedev_alloc(struct cxl_dev_state *cxlds)
@@ -70,6 +80,7 @@ static struct cxl_cachedev *cxl_cachedev_alloc(struct cxl_dev_state *cxlds)
 	dev->bus = &cxl_bus_type;
 	dev->type = &cxl_cachedev_type;
 	device_set_pm_not_required(dev);
+	INIT_WORK(&cxlcd->detach_work, detach_cachedev);
 
 	return_ptr(cxlcd);
 }
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 506461d5db22..125e175b1c0d 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -2356,6 +2356,12 @@ bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd)
 }
 EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, "CXL");
 
+bool schedule_cxl_cachedev_detach(struct cxl_cachedev *cxlcd)
+{
+	return queue_work(cxl_bus_wq, &cxlcd->detach_work);
+}
+EXPORT_SYMBOL_NS_GPL(schedule_cxl_cachedev_detach, "CXL");
+
 static void add_latency(struct access_coordinate *c, long latency)
 {
 	for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 7d369030198a..5cc2fe844396 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -752,6 +752,7 @@ struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev,
 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
 				   struct cxl_dport **dport);
 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
+bool schedule_cxl_cachedev_detach(struct cxl_cachedev *cxlcd);
 
 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
 				     struct device *dport, int port_id,
diff --git a/drivers/cxl/cxlcache.h b/drivers/cxl/cxlcache.h
index be6dac93b91e..e9a4567b7f2c 100644
--- a/drivers/cxl/cxlcache.h
+++ b/drivers/cxl/cxlcache.h
@@ -9,6 +9,7 @@
  * a CXL device
  * @dev: driver core device object
  * @cxlds: device state backing this device
+ * @detach_work: active cachedev lost a port in its ancestry
  * @endpoint: connection to the CXL port topology for this device
  * @id: id number of this cachedev instance
  * @depth: endpoint port depth in hierarchy
@@ -16,6 +17,7 @@
 struct cxl_cachedev {
 	struct device dev;
 	struct cxl_dev_state *cxlds;
+	struct work_struct detach_work;
 	struct cxl_port *endpoint;
 	int id;
 	int depth;
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index edf0ff759fbf..7c93fabfb095 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -5,6 +5,7 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 
+#include "cxlcache.h"
 #include "cxlmem.h"
 #include "cxlpci.h"
 
@@ -26,9 +27,13 @@
  * PCIe topology.
  */
 
-static void schedule_detach(void *cxlmd)
+static void schedule_detach(void *ep_dev)
 {
-	schedule_cxl_memdev_detach(cxlmd);
+	if (is_cxl_memdev(ep_dev))
+		schedule_cxl_memdev_detach(ep_dev);
+
+	if (is_cxl_cachedev(ep_dev))
+		schedule_cxl_cachedev_detach(ep_dev);
 }
 
 static int discover_region(struct device *dev, void *unused)
@@ -118,24 +123,9 @@ static int cxl_ras_unmask(struct cxl_port *port)
 	return 0;
 }
 
-static int cxl_endpoint_port_probe(struct cxl_port *port)
+static void cxl_endpoint_setup_dport_ras(struct cxl_port *port)
 {
-	struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
 	struct cxl_dport *dport = port->parent_dport;
-	int rc;
-
-	/* Cache the data early to ensure is_visible() works */
-	read_cdat_data(port);
-	cxl_endpoint_parse_cdat(port);
-
-	get_device(&cxlmd->dev);
-	rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd);
-	if (rc)
-		return rc;
-
-	rc = devm_cxl_endpoint_decoders_setup(port);
-	if (rc)
-		return rc;
 
 	/*
 	 * With VH (CXL Virtual Host) topology the cxl_port::add_dport() method
@@ -151,6 +141,27 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
 	devm_cxl_port_ras_setup(port);
 	if (cxl_ras_unmask(port))
 		dev_dbg(&port->dev, "failed to unmask RAS interrupts\n");
+}
+
+static int cxl_mem_endpoint_port_probe(struct cxl_port *port)
+{
+	struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
+	int rc;
+
+	/* Cache the data early to ensure is_visible() works */
+	read_cdat_data(port);
+	cxl_endpoint_parse_cdat(port);
+
+	get_device(&cxlmd->dev);
+	rc = devm_add_action_or_reset(&port->dev, schedule_detach, &cxlmd->dev);
+	if (rc)
+		return rc;
+
+	rc = devm_cxl_endpoint_decoders_setup(port);
+	if (rc)
+		return rc;
+
+	cxl_endpoint_setup_dport_ras(port);
 
 	/*
 	 * Now that all endpoint decoders are successfully enumerated, try to
@@ -161,12 +172,30 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
 	return 0;
 }
 
+static int cxl_cache_endpoint_port_probe(struct cxl_port *port)
+{
+	struct cxl_cachedev *cxlcd = to_cxl_cachedev(port->uport_dev);
+	int rc;
+
+	get_device(&cxlcd->dev);
+	rc = devm_add_action_or_reset(&port->dev, schedule_detach,
+				      &cxlcd->dev);
+	if (rc)
+		return rc;
+
+	cxl_endpoint_setup_dport_ras(port);
+
+	return rc;
+}
+
 static int cxl_port_probe(struct device *dev)
 {
 	struct cxl_port *port = to_cxl_port(dev);
 
-	if (is_cxl_endpoint(port))
-		return cxl_endpoint_port_probe(port);
+	if (is_cxl_memdev(port->uport_dev))
+		return cxl_mem_endpoint_port_probe(port);
+	else if (is_cxl_cachedev(port->uport_dev))
+		return cxl_cache_endpoint_port_probe(port);
 	return cxl_switch_port_probe(port);
 }
 
-- 
2.53.0