From: sashiko-bot@kernel.org
To: "Ben Cheatham" <Benjamin.Cheatham@amd.com>
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH 12/15] cxl/cache: Add snoop filter creation and set up
Date: Wed, 23 Sep 2026 17:50:49 +0000 [thread overview]
Message-ID: <20260923175049.D202C1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260923173342.5584-13-Benjamin.Cheatham@amd.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] cxl/cache: devres leak on dport hot-remove due to devm group mismatch
--
commit a51df73f15bcf70227ccbfa7fe083fcb3c6ed6e3
Author: Ben Cheatham <Benjamin.Cheatham@amd.com>
cxl/cache: Add snoop filter creation and set up
This commit adds the capability to track the system's CXL snoop filters and
probes them during dport addition. Snoop filter capacity allocation will be
handled in a later patch.
> diff --git a/drivers/cxl/core/cache.c b/drivers/cxl/core/cache.c
> --- a/drivers/cxl/core/cache.c
> +++ b/drivers/cxl/core/cache.c
[ ... ]
> +int cxl_dport_probe_snoop_filter(struct cxl_dport *dport)
> +{
[ ... ]
> + rc = cxl_map_component_regs(&dport->reg_map, &dport->regs.component,
> + BIT(CXL_CM_CAP_CAP_ID_SNOOP));
[ ... ]
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -301,6 +301,16 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
> /* New dport added, update the decoder targets */
> cxl_port_update_decoder_targets(port, dport);
>
> + /*
> + * cxl_cachedevs won't probe if this fails, but it's not an error for
> + * cxl_memdevs
> + */
> + rc = cxl_dport_probe_snoop_filter(dport);
[Severity: Medium]
Does this code leak devres memory and virtual address space on dport
hot-remove?
This function call happens outside of the dport devres group, which was
already closed when __devm_cxl_add_dport() returned (and the temporary
port_dr_group is removed earlier in this function).
When cxl_dport_probe_snoop_filter() is called, it triggers a devm
allocation:
cxl_dport_probe_snoop_filter()
-> cxl_map_component_regs()
-> devm_cxl_iomap_block()
Because there is no active devres group specifically scoped to the dport
at this point, will this devm allocation attach directly to the parent
port instead? If so, the allocation won't be freed when the dport is
hot-removed, leading to a resource leak.
> + if (rc)
> + dev_info(dport->dport_dev,
> + "Failed to find or create a CXL snoop filter: %d\n",
> + rc);
> +
> dev_dbg(&port->dev, "dport%d:%s added\n", dport->port_id,
> dev_name(dport_dev));
>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260923173342.5584-1-Benjamin.Cheatham@amd.com?part=12
next prev parent reply other threads:[~2026-09-23 17:50 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 17:33 [PATCH 00/15] Add initial CXL.cache support Ben Cheatham
2026-09-23 17:33 ` [PATCH 01/15] cxl/core: Add CXL.cache device struct Ben Cheatham
2026-09-23 17:41 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 02/15] cxl/cache: Add cxl_cache driver Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 03/15] cxl/core: Change cxl_ep_load() to use device pointer parameter Ben Cheatham
2026-09-23 17:33 ` [PATCH 04/15] cxl/core: Update devm_cxl_enumerate_ports() for cxl_cachedevs Ben Cheatham
2026-09-23 17:33 ` [PATCH 05/15] cxl/port: Split endpoint port probe on device type Ben Cheatham
2026-09-23 17:46 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 06/15] cxl/core: Update devm_cxl_add_endpoint() for cxl_cachedevs Ben Cheatham
2026-09-23 17:51 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 07/15] cxl/cache: Verify port hierarchy has CXL.cache enabled Ben Cheatham
2026-09-23 17:33 ` [PATCH 08/15] cxl/core, cache: Add Cache ID register probing and init Ben Cheatham
2026-09-23 17:46 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 09/15] cxl/core: Add Cache ID verification Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 10/15] cxl/core: Add Cache ID allocation Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 11/15] cxl/core: Add support for HDM-D cache id programming Ben Cheatham
2026-09-23 17:51 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 12/15] cxl/cache: Add snoop filter creation and set up Ben Cheatham
2026-09-23 17:50 ` sashiko-bot [this message]
2026-09-23 17:33 ` [PATCH 13/15] cxl/cache: Add snoop filter allocation Ben Cheatham
2026-09-23 17:58 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 14/15] iommu, cxl: Configure IOMMU for CXL.cache Ben Cheatham
2026-09-23 17:57 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 15/15] cxl/cache: Enable CXL.cache on successful probe Ben Cheatham
2026-09-23 17:35 ` [PATCH 00/15] Add initial CXL.cache support Cheatham, Benjamin
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