Re: [PATCH 08/15] cxl/core, cache: Add Cache ID register probing and init

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] build: function redefinition in cache.c when CONFIG_CXL_CACHE=n
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commit 666bdbfb794604b7884fcb19d8260bded28d941b
Author: Ben Cheatham <Benjamin.Cheatham@amd.com>

cxl/core, cache: Add Cache ID register probing and init

The CXL Cache ID Route Table capability and CXL Cache ID Decoder
capability are optional capabilities required when more than one CXL.cache
device is enabled under a host bridge. This commit probes for these
registers and maps them if found during the cxl_port probe.

> diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
> index f51575abe5af4..33420aaf40db9 100644
> --- a/drivers/cxl/core/Makefile
> +++ b/drivers/cxl/core/Makefile
> @@ -15,6 +15,7 @@ cxl_core-y += pci.o
>  cxl_core-y += hdm.o
>  cxl_core-y += pmu.o
>  cxl_core-y += cdat.o
> +cxl_core-y += cache.o

[Severity: Low]
Will this cause a build failure when CONFIG_CXL_CACHE is disabled?

Because cache.o is added unconditionally here, drivers/cxl/core/cache.c is
compiled even when CONFIG_CXL_CACHE=n. This causes a function redefinition
error for cxl_port_map_cache_id_rt() and cxl_dport_map_cache_id_dc() since
they are also defined as static inline stubs in drivers/cxl/cxl.h:

#if IS_ENABLED(CONFIG_CXL_CACHE)
int cxl_port_map_cache_id_rt(struct cxl_port *port);
int cxl_dport_map_cache_id_dc(struct cxl_dport *dport);
#else
static inline int cxl_port_map_cache_id_rt(struct cxl_port *port)
{ return -ENXIO; }
static inline int cxl_dport_map_cache_id_dc(struct cxl_dport *dport)
{ return -ENXIO; }
#endif

Should cache.o be added to cxl_core-$(CONFIG_CXL_CACHE) instead of
cxl_core-y?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260923173342.5584-1-Benjamin.Cheatham@amd.com?part=8