From: <dan.j.williams@intel.com>
To: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>
Cc: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
Li Ming <ming.li@zohomail.com>
Subject: Re: [PATCH v7 05/10] cxl/test: Add cxl_test support for cxl_port_update_total_ports()
Date: Tue, 22 Jul 2025 09:24:06 -0700 [thread overview]
Message-ID: <687fbb263b892_134cc71006a@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250714223527.461147-6-dave.jiang@intel.com>
Dave Jiang wrote:
> In the delayed dport allocation scheme, the total number of dports
> need to be discovered during port probe. Add the mock function
> that does it for cxl_test.
Looks ok, but this coming after the core code adds the call means that
there is a cxl_test bisect break? I guess there is no clean way to avoid
that.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
next prev parent reply other threads:[~2025-07-22 16:24 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 22:35 [PATCH v7 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-07-14 22:35 ` [PATCH v7 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-07-21 11:33 ` Robert Richter
2025-07-21 20:18 ` dan.j.williams
2025-07-21 22:12 ` dan.j.williams
2025-07-21 23:18 ` Dave Jiang
2025-07-14 22:35 ` [PATCH v7 02/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-07-16 1:58 ` Alison Schofield
2025-07-21 20:23 ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 03/10] cxl: Add helper to reap dport Dave Jiang
2025-07-16 1:59 ` Alison Schofield
2025-07-21 20:24 ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 04/10] cxl: Defer dport allocation for switch ports Dave Jiang
2025-07-15 1:38 ` Li Ming
2025-07-16 2:00 ` Alison Schofield
2025-07-21 23:14 ` Robert Richter
2025-07-22 15:47 ` Dave Jiang
2025-07-22 15:50 ` dan.j.williams
2025-08-12 18:11 ` Dave Jiang
2025-07-14 22:35 ` [PATCH v7 05/10] cxl/test: Add cxl_test support for cxl_port_update_total_ports() Dave Jiang
2025-07-16 2:03 ` Alison Schofield
2025-07-22 16:24 ` dan.j.williams [this message]
2025-07-14 22:35 ` [PATCH v7 06/10] cxl/test: Add mock version of devm_cxl_add_dport_by_dev() Dave Jiang
2025-07-16 2:04 ` Alison Schofield
2025-07-22 17:06 ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-07-16 2:05 ` Alison Schofield
2025-07-21 23:18 ` Robert Richter
2025-07-21 23:25 ` Dave Jiang
2025-07-22 17:12 ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 08/10] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-07-16 2:06 ` Alison Schofield
2025-07-14 22:35 ` [PATCH v7 09/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-07-16 2:07 ` Alison Schofield
2025-07-22 18:31 ` dan.j.williams
2025-07-22 19:07 ` Dave Jiang
2025-07-22 19:28 ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 10/10] cxl: Remove devm_cxl_port_enumerate_dports() that is no longer used Dave Jiang
2025-07-16 2:09 ` Alison Schofield
2025-07-22 18:32 ` dan.j.williams
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