Linux CXL
 help / color / mirror / Atom feed
From: <dan.j.williams@intel.com>
To: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>
Cc: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
	<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
	<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
	Gregory Price <gourry@gourry.net>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Li Ming <ming.li@zohomail.com>
Subject: Re: [PATCH v7 07/10] cxl: Change sslbis handler to only handle single dport
Date: Tue, 22 Jul 2025 10:12:15 -0700	[thread overview]
Message-ID: <687fc66f5cf94_134cc71007a@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250714223527.461147-8-dave.jiang@intel.com>

Dave Jiang wrote:
> While cxl_switch_parse_cdat() is harmless to be run multiple times, it is
> not efficient in the current scheme where one dport is being updated at
> a time by the memdev probe path. Change the input parameter to the
> specific dport being updated to pick up the SSLBIS information for just
> that dport.
> 
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Li Ming <ming.li@zohomail.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  drivers/cxl/core/cdat.c | 23 ++++++++++-------------
>  drivers/cxl/core/port.c |  2 +-
>  drivers/cxl/cxl.h       |  2 +-
>  3 files changed, 12 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> index 0ccef2f2a26a..58c21a2f22c1 100644
> --- a/drivers/cxl/core/cdat.c
> +++ b/drivers/cxl/core/cdat.c
> @@ -440,8 +440,8 @@ static int cdat_sslbis_handler(union acpi_subtable_headers *header, void *arg,
>  	} *tbl = (struct acpi_cdat_sslbis_table *)header;
>  	int size = sizeof(header->cdat) + sizeof(tbl->sslbis_header);
>  	struct acpi_cdat_sslbis *sslbis;
> -	struct cxl_port *port = arg;
> -	struct device *dev = &port->dev;
> +	struct cxl_dport *dport = arg;
> +	struct device *dev = &dport->port->dev;
>  	int remain, entries, i;
>  	u16 len;
>  
> @@ -467,8 +467,6 @@ static int cdat_sslbis_handler(union acpi_subtable_headers *header, void *arg,
>  		u16 y = le16_to_cpu((__force __le16)tbl->entries[i].porty_id);
>  		__le64 le_base;
>  		__le16 le_val;
> -		struct cxl_dport *dport;
> -		unsigned long index;
>  		u16 dsp_id;
>  		u64 val;
>  
> @@ -499,28 +497,27 @@ static int cdat_sslbis_handler(union acpi_subtable_headers *header, void *arg,
>  		val = cdat_normalize(le16_to_cpu(le_val), le64_to_cpu(le_base),
>  				     sslbis->data_type);
>  
> -		xa_for_each(&port->dports, index, dport) {
> -			if (dsp_id == ACPI_CDAT_SSLBIS_ANY_PORT ||
> -			    dsp_id == dport->port_id) {
> -				cxl_access_coordinate_set(dport->coord,
> -							  sslbis->data_type,
> -							  val);
> -			}
> +		if (dsp_id == ACPI_CDAT_SSLBIS_ANY_PORT ||
> +		    dsp_id == dport->port_id) {
> +			cxl_access_coordinate_set(dport->coord,
> +						  sslbis->data_type, val);
> +			return 0;
>  		}
>  	}
>  
>  	return 0;
>  }
>  
> -void cxl_switch_parse_cdat(struct cxl_port *port)
> +void cxl_switch_parse_cdat(struct cxl_dport *dport)
>  {
> +	struct cxl_port *port = dport->port;
>  	int rc;
>  
>  	if (!port->cdat.table)
>  		return;
>  
>  	rc = cdat_table_parse(ACPI_CDAT_TYPE_SSLBIS, cdat_sslbis_handler,
> -			      port, port->cdat.table, port->cdat.length);
> +			      dport, port->cdat.table, port->cdat.length);
>  	rc = cdat_table_parse_output(rc);
>  	if (rc)
>  		dev_dbg(&port->dev, "Failed to parse SSLBIS: %d\n", rc);
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index c1de6872e57f..afeebb0ce4ab 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1614,7 +1614,7 @@ static int cxl_port_setup_with_dport(struct cxl_port *port,
>  {
>  	device_lock_assert(&port->dev);
>  
> -	cxl_switch_parse_cdat(port);
> +	cxl_switch_parse_cdat(dport);

Ah, I now realize I misread patch4 where I asked about the ordering of
this function relative to the update. The dport is already added at this
point.

>  
>  	return update_decoders_with_dport(port, dport);

More delayed realization... cxl_port_setup_with_dport() should be
"void", it never fails.

As for this patch, looks good.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>

  parent reply	other threads:[~2025-07-22 17:12 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-14 22:35 [PATCH v7 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-07-14 22:35 ` [PATCH v7 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-07-21 11:33   ` Robert Richter
2025-07-21 20:18   ` dan.j.williams
2025-07-21 22:12     ` dan.j.williams
2025-07-21 23:18       ` Dave Jiang
2025-07-14 22:35 ` [PATCH v7 02/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-07-16  1:58   ` Alison Schofield
2025-07-21 20:23   ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 03/10] cxl: Add helper to reap dport Dave Jiang
2025-07-16  1:59   ` Alison Schofield
2025-07-21 20:24   ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 04/10] cxl: Defer dport allocation for switch ports Dave Jiang
2025-07-15  1:38   ` Li Ming
2025-07-16  2:00   ` Alison Schofield
2025-07-21 23:14   ` Robert Richter
2025-07-22 15:47     ` Dave Jiang
2025-07-22 15:50   ` dan.j.williams
2025-08-12 18:11     ` Dave Jiang
2025-07-14 22:35 ` [PATCH v7 05/10] cxl/test: Add cxl_test support for cxl_port_update_total_ports() Dave Jiang
2025-07-16  2:03   ` Alison Schofield
2025-07-22 16:24   ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 06/10] cxl/test: Add mock version of devm_cxl_add_dport_by_dev() Dave Jiang
2025-07-16  2:04   ` Alison Schofield
2025-07-22 17:06   ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-07-16  2:05   ` Alison Schofield
2025-07-21 23:18   ` Robert Richter
2025-07-21 23:25     ` Dave Jiang
2025-07-22 17:12   ` dan.j.williams [this message]
2025-07-14 22:35 ` [PATCH v7 08/10] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-07-16  2:06   ` Alison Schofield
2025-07-14 22:35 ` [PATCH v7 09/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-07-16  2:07   ` Alison Schofield
2025-07-22 18:31   ` dan.j.williams
2025-07-22 19:07     ` Dave Jiang
2025-07-22 19:28       ` dan.j.williams
2025-07-14 22:35 ` [PATCH v7 10/10] cxl: Remove devm_cxl_port_enumerate_dports() that is no longer used Dave Jiang
2025-07-16  2:09   ` Alison Schofield
2025-07-22 18:32   ` dan.j.williams

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=687fc66f5cf94_134cc71007a@dwillia2-xfh.jf.intel.com.notmuch \
    --to=dan.j.williams@intel.com \
    --cc=alison.schofield@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=gourry@gourry.net \
    --cc=ira.weiny@intel.com \
    --cc=jonathan.cameron@huawei.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=ming.li@zohomail.com \
    --cc=vishal.l.verma@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox