Re: [PATCH v7 09/10] cxl: Move enumeration of hostbridge ports to the memdev probe path

[<dan.j.williams@intel.com>]

Dave Jiang wrote:
> 
> 
> On 7/22/25 11:31 AM, dan.j.williams@intel.com wrote:
> > Dave Jiang wrote:
> >> Current enuemration scheme in cxl_acpi module creates the ports under the
> >> root port by enumerating the hostbridges after the dports under the root
> >> port is created. However error messages "cxl portN: Couldn't locate the
> >> CXL.cache and CXL.mem capability array header" is observed when certain
> >> platform has PCIe hotplug option turned on in BIOS. If the cxl_acpi module
> >> probe is running before the CXL link between the endpoint device and the
> >> RP is established, then the platform may not have exposed DVSEC ID 3 and/or
> >> DVSEC ID 7 blocks which will trigger the error message. This behavior
> >> is defined by the spec and not a hardware quirk.
> >>
> >> Setup an association in cxl_port to tie the host bridge device to the
> >> associated cxl_root. The cxl_root provides a callback that's setup
> >> by the cxl_acpi probe function in order to create a port per host bridge
> >> that was previously done during cxl_acpi probe. Add the calling of the
> >> callback in devm_cxl_enumerate_ports(). The observed behavior is that
> >> ports that are not connected to endpoint device(s) are no longer
> >> enumerated. This should also remove any excessive noise of port probe
> >> failing on those inactive ports.
> > 
> > I do not understand the story here. Why is it necessary to hide host
> > bridge ports that do not have endpoints attached? I think that is
> > valuable information for hotplug to identify available ports.
> 
> It's not going out of the way to hide on purpose. It's more that this
> is the resulting behavior when we are setting up the hierarchy via the
> mem probe.

Right, but that feels like a step backwards in system observability.

> > 
> > Now, if the concern is that host bridge CXL component register
> > enumeration happens too early then the solution there is delay port
> > register setup until the first dport arrival.
> 
> Are you saying to just delay the RP register setup until when dports
> show up, leave the enumeration as is?

Right, cxl_port_setup_regs() moves out of cxl_port_add() and gets
triggered by first dport assignment to a port.