* [PATCH] cxl/pci: Remove endian confusion
@ 2022-12-06 4:28 Dan Williams
2022-12-06 6:43 ` Ira Weiny
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Dan Williams @ 2022-12-06 4:28 UTC (permalink / raw)
To: linux-cxl; +Cc: Jonathan Cameron, Dave Jiang, dave.jiang
readl() already handles endian conversion. That's the main difference
between readl() and __raw_readl(). This is benign on little-endian
systems, but big endian systems will end up byte-swabbing twice.
Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/pci.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index cced4a0df3d1..33083a522fd1 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -548,15 +548,14 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
return false;
addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
- status = le32_to_cpu((__force __le32)readl(addr));
+ status = readl(addr);
if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))
return false;
/* If multiple errors, log header points to first error from ctrl reg */
if (hweight32(status) > 1) {
addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
- fe = BIT(le32_to_cpu((__force __le32)readl(addr)) &
- CXL_RAS_CAP_CONTROL_FE_MASK);
+ fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
} else {
fe = status;
}
@@ -641,7 +640,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
return;
addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
- status = le32_to_cpu(readl(addr));
+ status = readl(addr);
if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
trace_cxl_aer_correctable_error(dev, status);
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] cxl/pci: Remove endian confusion
2022-12-06 4:28 [PATCH] cxl/pci: Remove endian confusion Dan Williams
@ 2022-12-06 6:43 ` Ira Weiny
2022-12-06 9:50 ` Jonathan Cameron
2022-12-06 17:04 ` Dave Jiang
2022-12-07 17:01 ` Christoph Hellwig
2 siblings, 1 reply; 5+ messages in thread
From: Ira Weiny @ 2022-12-06 6:43 UTC (permalink / raw)
To: Dan Williams; +Cc: linux-cxl, Jonathan Cameron, Dave Jiang
On Mon, Dec 05, 2022 at 08:28:40PM -0800, Dan Williams wrote:
> readl() already handles endian conversion. That's the main difference
> between readl() and __raw_readl(). This is benign on little-endian
> systems, but big endian systems will end up byte-swabbing twice.
>
> Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
> drivers/cxl/pci.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index cced4a0df3d1..33083a522fd1 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -548,15 +548,14 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> return false;
>
> addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
> - status = le32_to_cpu((__force __le32)readl(addr));
> + status = readl(addr);
> if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))
> return false;
>
> /* If multiple errors, log header points to first error from ctrl reg */
> if (hweight32(status) > 1) {
> addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> - fe = BIT(le32_to_cpu((__force __le32)readl(addr)) &
> - CXL_RAS_CAP_CONTROL_FE_MASK);
> + fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
> } else {
> fe = status;
> }
> @@ -641,7 +640,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
> return;
>
> addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
> - status = le32_to_cpu(readl(addr));
> + status = readl(addr);
> if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> trace_cxl_aer_correctable_error(dev, status);
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] cxl/pci: Remove endian confusion
2022-12-06 6:43 ` Ira Weiny
@ 2022-12-06 9:50 ` Jonathan Cameron
0 siblings, 0 replies; 5+ messages in thread
From: Jonathan Cameron @ 2022-12-06 9:50 UTC (permalink / raw)
To: Ira Weiny; +Cc: Dan Williams, linux-cxl, Dave Jiang
On Mon, 5 Dec 2022 22:43:41 -0800
Ira Weiny <ira.weiny@intel.com> wrote:
> On Mon, Dec 05, 2022 at 08:28:40PM -0800, Dan Williams wrote:
> > readl() already handles endian conversion. That's the main difference
> > between readl() and __raw_readl(). This is benign on little-endian
> > systems, but big endian systems will end up byte-swabbing twice.
> >
> > Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
> > Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Cc: Dave Jiang <dave.jiang@intel.com>
>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Gah. Hate endian mess. Anyone actually want big endian support? :)
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> > ---
> > drivers/cxl/pci.c | 7 +++----
> > 1 file changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index cced4a0df3d1..33083a522fd1 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -548,15 +548,14 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> > return false;
> >
> > addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
> > - status = le32_to_cpu((__force __le32)readl(addr));
> > + status = readl(addr);
> > if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))
> > return false;
> >
> > /* If multiple errors, log header points to first error from ctrl reg */
> > if (hweight32(status) > 1) {
> > addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> > - fe = BIT(le32_to_cpu((__force __le32)readl(addr)) &
> > - CXL_RAS_CAP_CONTROL_FE_MASK);
> > + fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
> > } else {
> > fe = status;
> > }
> > @@ -641,7 +640,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
> > return;
> >
> > addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
> > - status = le32_to_cpu(readl(addr));
> > + status = readl(addr);
> > if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> > writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> > trace_cxl_aer_correctable_error(dev, status);
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl/pci: Remove endian confusion
2022-12-06 4:28 [PATCH] cxl/pci: Remove endian confusion Dan Williams
2022-12-06 6:43 ` Ira Weiny
@ 2022-12-06 17:04 ` Dave Jiang
2022-12-07 17:01 ` Christoph Hellwig
2 siblings, 0 replies; 5+ messages in thread
From: Dave Jiang @ 2022-12-06 17:04 UTC (permalink / raw)
To: Dan Williams, linux-cxl; +Cc: Jonathan Cameron
On 12/5/2022 9:28 PM, Dan Williams wrote:
> readl() already handles endian conversion. That's the main difference
> between readl() and __raw_readl(). This is benign on little-endian
> systems, but big endian systems will end up byte-swabbing twice.
>
> Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Dave Jiang <dave.jiang@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/pci.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index cced4a0df3d1..33083a522fd1 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -548,15 +548,14 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> return false;
>
> addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
> - status = le32_to_cpu((__force __le32)readl(addr));
> + status = readl(addr);
> if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))
> return false;
>
> /* If multiple errors, log header points to first error from ctrl reg */
> if (hweight32(status) > 1) {
> addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> - fe = BIT(le32_to_cpu((__force __le32)readl(addr)) &
> - CXL_RAS_CAP_CONTROL_FE_MASK);
> + fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
> } else {
> fe = status;
> }
> @@ -641,7 +640,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
> return;
>
> addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
> - status = le32_to_cpu(readl(addr));
> + status = readl(addr);
> if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> trace_cxl_aer_correctable_error(dev, status);
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] cxl/pci: Remove endian confusion
2022-12-06 4:28 [PATCH] cxl/pci: Remove endian confusion Dan Williams
2022-12-06 6:43 ` Ira Weiny
2022-12-06 17:04 ` Dave Jiang
@ 2022-12-07 17:01 ` Christoph Hellwig
2 siblings, 0 replies; 5+ messages in thread
From: Christoph Hellwig @ 2022-12-07 17:01 UTC (permalink / raw)
To: Dan Williams; +Cc: linux-cxl, Jonathan Cameron, Dave Jiang
On Mon, Dec 05, 2022 at 08:28:40PM -0800, Dan Williams wrote:
> - status = le32_to_cpu((__force __le32)readl(addr));
> + status = readl(addr);
Those force casts should have been a giant warning flag..
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-12-07 17:02 UTC | newest]
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2022-12-06 4:28 [PATCH] cxl/pci: Remove endian confusion Dan Williams
2022-12-06 6:43 ` Ira Weiny
2022-12-06 9:50 ` Jonathan Cameron
2022-12-06 17:04 ` Dave Jiang
2022-12-07 17:01 ` Christoph Hellwig
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