From: Alejandro Lucero Palau <alucerop@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
alejandro.lucero-palau@amd.com
Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
dan.j.williams@intel.com, edward.cree@amd.com,
davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, dave.jiang@intel.com
Subject: Re: [PATCH v13 11/22] cxl: define a driver interface for HPA free space enumeration
Date: Thu, 17 Apr 2025 13:11:00 +0100 [thread overview]
Message-ID: <eb5f16f8-607a-4c71-8f81-5cdb4ff73a75@amd.com> (raw)
In-Reply-To: <20250415145016.00003725@huawei.com>
On 4/15/25 14:50, Jonathan Cameron wrote:
> On Mon, 14 Apr 2025 16:13:25 +0100
> alejandro.lucero-palau@amd.com wrote:
>
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> CXL region creation involves allocating capacity from device DPA
>> (device-physical-address space) and assigning it to decode a given HPA
>> (host-physical-address space). Before determining how much DPA to
>> allocate the amount of available HPA must be determined. Also, not all
>> HPA is created equal, some specifically targets RAM, some target PMEM,
>> some is prepared for device-memory flows like HDM-D and HDM-DB, and some
>> is host-only (HDM-H).
>>
>> Wrap all of those concerns into an API that retrieves a root decoder
>> (platform CXL window) that fits the specified constraints and the
>> capacity available for a new region.
>>
>> Add a complementary function for releasing the reference to such root
>> decoder.
>>
>> Based on https://lore.kernel.org/linux-cxl/168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com/
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> One trivial comment inline.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
>> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
>> index 80caaf14d08a..0a9eab4f8e2e 100644
>> --- a/drivers/cxl/core/region.c
>> +++ b/drivers/cxl/core/region.c
>> +static int find_max_hpa(struct device *dev, void *data)
>> +{
>> + struct cxlrd_max_context *ctx = data;
>> + struct cxl_switch_decoder *cxlsd;
>> + struct cxl_root_decoder *cxlrd;
>> + struct resource *res, *prev;
>> + struct cxl_decoder *cxld;
>> + resource_size_t max;
>> + int found = 0;
>> +
>> + if (!is_root_decoder(dev))
>> + return 0;
>> +
>> + cxlrd = to_cxl_root_decoder(dev);
>> + cxlsd = &cxlrd->cxlsd;
>> + cxld = &cxlsd->cxld;
>> +
>> + /*
>> + * None flags are declared as bitmaps but for the sake of better code
> None?
Not sure you refer to syntax or semantics here. Assuming is the former:
No flags fields?
>
>> + * used here as such, restricting the bitmap size to those bits used by
>> + * any Type2 device driver requester.
>> + */
>
next prev parent reply other threads:[~2025-04-17 12:11 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-14 15:13 [PATCH v13 00/22] Type2 device basic support alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 01/22] cxl: add type2 " alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 02/22] sfc: add cxl support alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 03/22] cxl: move pci generic code alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 04/22] cxl: move register/capability check to driver alejandro.lucero-palau
2025-04-14 17:18 ` Jonathan Cameron
2025-04-15 7:44 ` Alejandro Lucero Palau
2025-04-14 15:13 ` [PATCH v13 05/22] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-04-15 13:21 ` Jonathan Cameron
2025-04-17 12:07 ` Alejandro Lucero Palau
2025-04-14 15:13 ` [PATCH v13 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-04-15 13:25 ` Jonathan Cameron
2025-04-17 12:08 ` Alejandro Lucero Palau
2025-04-14 15:13 ` [PATCH v13 07/22] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-04-15 13:27 ` Jonathan Cameron
2025-04-14 15:13 ` [PATCH v13 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-04-15 13:28 ` Jonathan Cameron
2025-04-14 15:13 ` [PATCH v13 09/22] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 11/22] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-04-15 13:50 ` Jonathan Cameron
2025-04-17 12:11 ` Alejandro Lucero Palau [this message]
2025-04-17 16:36 ` Jonathan Cameron
2025-04-17 21:22 ` Alejandro Lucero Palau
2025-04-22 15:51 ` Jonathan Cameron
2025-04-14 15:13 ` [PATCH v13 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 13/22] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-04-15 17:19 ` kernel test robot
2025-04-15 17:40 ` kernel test robot
2025-04-15 19:02 ` kernel test robot
2025-04-14 15:13 ` [PATCH v13 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 15/22] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 16/22] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 17/22] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 18/22] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-04-15 13:55 ` Jonathan Cameron
2025-04-14 15:13 ` [PATCH v13 19/22] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 20/22] sfc: create cxl region alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 21/22] cxl: add function for obtaining region range alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-04-15 13:56 ` Jonathan Cameron
2025-04-14 15:20 ` [PATCH v13 00/22] Type2 device basic support Alejandro Lucero Palau
2025-04-14 21:21 ` Alison Schofield
2025-04-15 7:09 ` Alejandro Lucero Palau
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