Linux CXL
 help / color / mirror / Atom feed
From: Alejandro Lucero Palau <alucerop@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	alejandro.lucero-palau@amd.com
Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
	dan.j.williams@intel.com, edward.cree@amd.com,
	davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
	edumazet@google.com, dave.jiang@intel.com
Subject: Re: [PATCH v13 04/22] cxl: move register/capability check to driver
Date: Tue, 15 Apr 2025 08:44:18 +0100	[thread overview]
Message-ID: <fe89058c-cd98-4149-a37e-8b8052cffa17@amd.com> (raw)
In-Reply-To: <20250414181833.00003eca@huawei.com>


On 4/14/25 18:18, Jonathan Cameron wrote:
> On Mon, 14 Apr 2025 16:13:18 +0100
> alejandro.lucero-palau@amd.com wrote:
>
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Type3 has some mandatory capabilities which are optional for Type2.
>>
>> In order to support same register/capability discovery code for both
>> types, avoid any assumption about what capabilities should be there, and
>> export the capabilities found for the caller doing the capabilities
>> check based on the expected ones.
>>
>> Add a function for facilitating the report of capabiities missing the
>> expected ones.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Hi Alejandro.
>
> A request if we end up with a v14 - please add notes on what changed
> in each patch. It's really handy for reviewers to tell which patches
> they need to take another look at.   More info that we get from
> absence of our own tags!


Hi Jonathan,


Yes, I'll do so.


> One minor thing inline.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>

I'll do that change you suggest below as there will be an v14.


Thanks!


>> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
>> index 0996e228b26a..7d94e81b2e3b 100644
>> --- a/drivers/cxl/pci.c
>> +++ b/drivers/cxl/pci.c
>> @@ -836,6 +836,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>>   {
>>   	struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
>>   	struct cxl_dpa_info range_info = { 0 };
>> +	DECLARE_BITMAP(expected, CXL_MAX_CAPS);
> Trivial but can do
> 	DECLARE_BITMAP(expected, CXL_MAX_CAPS) = {};
> to avoid need for the zeroing below.
>
>> +	DECLARE_BITMAP(found, CXL_MAX_CAPS);
>>   	struct cxl_memdev_state *mds;
>>   	struct cxl_dev_state *cxlds;
>>   	struct cxl_register_map map;
>> @@ -871,7 +873,19 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>>   
>>   	cxlds->rcd = is_cxl_restricted(pdev);
>>   
>> -	rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
>> +	bitmap_zero(expected, CXL_MAX_CAPS);
>> +	bitmap_zero(found, CXL_MAX_CAPS);
>> +
>> +	/*
>> +	 * These are the mandatory capabilities for a Type3 device.
>> +	 * Only checking capabilities used by current Linux drivers.
>> +	 */
>> +	set_bit(CXL_DEV_CAP_HDM, expected);
>> +	set_bit(CXL_DEV_CAP_DEV_STATUS, expected);
>> +	set_bit(CXL_DEV_CAP_MAILBOX_PRIMARY, expected);
>> +	set_bit(CXL_DEV_CAP_MEMDEV, expected);
>> +
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>

  reply	other threads:[~2025-04-15  7:44 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-14 15:13 [PATCH v13 00/22] Type2 device basic support alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 01/22] cxl: add type2 " alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 02/22] sfc: add cxl support alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 03/22] cxl: move pci generic code alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 04/22] cxl: move register/capability check to driver alejandro.lucero-palau
2025-04-14 17:18   ` Jonathan Cameron
2025-04-15  7:44     ` Alejandro Lucero Palau [this message]
2025-04-14 15:13 ` [PATCH v13 05/22] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-04-15 13:21   ` Jonathan Cameron
2025-04-17 12:07     ` Alejandro Lucero Palau
2025-04-14 15:13 ` [PATCH v13 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-04-15 13:25   ` Jonathan Cameron
2025-04-17 12:08     ` Alejandro Lucero Palau
2025-04-14 15:13 ` [PATCH v13 07/22] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-04-15 13:27   ` Jonathan Cameron
2025-04-14 15:13 ` [PATCH v13 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-04-15 13:28   ` Jonathan Cameron
2025-04-14 15:13 ` [PATCH v13 09/22] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 11/22] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-04-15 13:50   ` Jonathan Cameron
2025-04-17 12:11     ` Alejandro Lucero Palau
2025-04-17 16:36       ` Jonathan Cameron
2025-04-17 21:22         ` Alejandro Lucero Palau
2025-04-22 15:51           ` Jonathan Cameron
2025-04-14 15:13 ` [PATCH v13 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 13/22] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-04-15 17:19   ` kernel test robot
2025-04-15 17:40   ` kernel test robot
2025-04-15 19:02   ` kernel test robot
2025-04-14 15:13 ` [PATCH v13 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 15/22] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 16/22] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 17/22] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 18/22] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-04-15 13:55   ` Jonathan Cameron
2025-04-14 15:13 ` [PATCH v13 19/22] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 20/22] sfc: create cxl region alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 21/22] cxl: add function for obtaining region range alejandro.lucero-palau
2025-04-14 15:13 ` [PATCH v13 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-04-15 13:56   ` Jonathan Cameron
2025-04-14 15:20 ` [PATCH v13 00/22] Type2 device basic support Alejandro Lucero Palau
2025-04-14 21:21 ` Alison Schofield
2025-04-15  7:09   ` Alejandro Lucero Palau

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=fe89058c-cd98-4149-a37e-8b8052cffa17@amd.com \
    --to=alucerop@amd.com \
    --cc=Jonathan.Cameron@huawei.com \
    --cc=alejandro.lucero-palau@amd.com \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=davem@davemloft.net \
    --cc=edumazet@google.com \
    --cc=edward.cree@amd.com \
    --cc=kuba@kernel.org \
    --cc=linux-cxl@vger.kernel.org \
    --cc=netdev@vger.kernel.org \
    --cc=pabeni@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox