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From: "Rob Herring (Arm)" <robh@kernel.org>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: devicetree@vger.kernel.org, Conor Dooley <conor@kernel.org>,
	 Emil Renner Berthing <kernel@esmil.dk>,
	Rob Herring <robh+dt@kernel.org>,
	 linux-kernel@vger.kernel.org,
	 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org,
	 Alexandre Ghiti <alexghiti@rivosinc.com>
Subject: Re: [PATCH 01/11] dt-bindings: riscv: Describe physical memory regions
Date: Fri, 01 Nov 2024 20:31:28 -0500	[thread overview]
Message-ID: <173051108892.583398.1565228083513288043.robh@kernel.org> (raw)
In-Reply-To: <20241102000843.1301099-2-samuel.holland@sifive.com>


On Fri, 01 Nov 2024 17:07:55 -0700, Samuel Holland wrote:
> Information about physical memory regions is needed by both the kernel
> and M-mode firmware. For example, the kernel needs to know about
> noncacheable aliases of cacheable memory in order to allocate coherent
> memory pages for DMA. M-mode firmware needs to know about aliases so it
> can protect itself from lower-privileged software. Firmware also needs
> to know the platform's Physical Address Width in order to efficiently
> implement Smmpt.
> 
> The RISC-V Privileged Architecture delegates the description of Physical
> Memory Attributes to the platform. On DT-based platforms, it makes sense
> to put this information in the devicetree.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
>  .../bindings/riscv/physical-memory.yaml       | 101 ++++++++++++++++++
>  include/dt-bindings/riscv/physical-memory.h   |  44 ++++++++
>  2 files changed, 145 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/physical-memory.yaml
>  create mode 100644 include/dt-bindings/riscv/physical-memory.h
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/physical-memory.example.dtb: /: compatible: 'oneOf' conditional failed, one must be fixed:
	['starfive,jh7100'] is too short
	'starfive,jh7100' is not one of ['beagle,beaglev-starlight-jh7100-r0', 'starfive,visionfive-v1']
	'starfive,jh7100' is not one of ['milkv,mars', 'pine64,star64', 'starfive,visionfive-2-v1.2a', 'starfive,visionfive-2-v1.3b']
	from schema $id: http://devicetree.org/schemas/riscv/starfive.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/physical-memory.example.dtb: /: 'model' is a required property
	from schema $id: http://devicetree.org/schemas/root-node.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241102000843.1301099-2-samuel.holland@sifive.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


  reply	other threads:[~2024-11-02  1:31 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-02  0:07 [PATCH 00/11] riscv: Memory type control for platforms with physical memory aliases Samuel Holland
2024-11-02  0:07 ` [PATCH 01/11] dt-bindings: riscv: Describe physical memory regions Samuel Holland
2024-11-02  1:31   ` Rob Herring (Arm) [this message]
2024-11-02  0:07 ` [PATCH 02/11] riscv: mm: Increment PFN in place when splitting mappings Samuel Holland
2024-11-05 10:25   ` Alexandre Ghiti
2024-11-02  0:07 ` [PATCH 03/11] riscv: mm: Deduplicate pgtable address conversion functions Samuel Holland
2024-11-05  9:58   ` Alexandre Ghiti
2024-11-02  0:07 ` [PATCH 04/11] riscv: mm: Deduplicate _PAGE_CHG_MASK definition Samuel Holland
2024-11-05 10:00   ` Alexandre Ghiti
2024-11-02  0:07 ` [PATCH 05/11] riscv: ptdump: Only show N and MT bits when enabled in the kernel Samuel Holland
2024-11-05 10:06   ` Alexandre Ghiti
2024-11-02  0:08 ` [PATCH 06/11] riscv: mm: Fix up memory types when writing page tables Samuel Holland
2024-11-05 11:03   ` Alexandre Ghiti
2025-10-09  2:12     ` Samuel Holland
2024-11-02  0:08 ` [PATCH 07/11] riscv: mm: Expose all page table bits to assembly code Samuel Holland
2024-11-02  0:08 ` [PATCH 08/11] riscv: alternative: Add an ALTERNATIVE_3 macro Samuel Holland
2024-11-15 13:05   ` Andrew Jones
2024-11-02  0:08 ` [PATCH 09/11] riscv: alternative: Allow calls with alternate link registers Samuel Holland
2024-11-02  0:08 ` [PATCH 10/11] riscv: mm: Use physical memory aliases to apply PMAs Samuel Holland
2024-11-02 15:28   ` kernel test robot
2024-11-05 13:21   ` Emil Renner Berthing
2024-11-02  0:08 ` [PATCH 11/11] riscv: dts: starfive: jh7100: Use physical memory ranges for DMA Samuel Holland
2024-11-04 15:26   ` Emil Renner Berthing
2025-09-22 23:55 ` [PATCH 00/11] riscv: Memory type control for platforms with physical memory aliases Bo Gan

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